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azt3328.c
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linux-6.19.14/sound/pci/azt3328.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* azt3328.c - driver for Aztech AZF3328 based soundcards (e.g. PCI168). 3 * Copyright (C) 2002, 2005 - 2011 by Andreas Mohr <andi AT lisas.de> 4 * 5 * Framework borrowed from Bart Hartgers's als4000.c. 6 * Driver developed on PCI168 AP(W) version (PCI rev. 10, subsystem ID 1801), 7 * found in a Fujitsu-Siemens PC ("Cordant", aluminum case). 8 * Other versions are: 9 * PCI168 A(W), sub ID 1800 10 * PCI168 A/AP, sub ID 8000 11 * Please give me feedback in case you try my driver with one of these!! 12 * 13 * Keywords: Windows XP Vista 168nt4-125.zip 168win95-125.zip PCI 168 download 14 * (XP/Vista do not support this card at all but every Linux distribution 15 * has very good support out of the box; 16 * just to make sure that the right people hit this and get to know that, 17 * despite the high level of Internet ignorance - as usual :-P - 18 * about very good support for this card - on Linux!) 19 * 20 * NOTES 21 * Since Aztech does not provide any chipset documentation, 22 * even on repeated request to various addresses, 23 * and the answer that was finally given was negative 24 * (and I was stupid enough to manage to get hold of a PCI168 soundcard 25 * in the first place >:-P}), 26 * I was forced to base this driver on reverse engineering 27 * (3 weeks' worth of evenings filled with driver work). 28 * (and no, I did NOT go the easy way: to pick up a SB PCI128 for 9 Euros) 29 * 30 * It is quite likely that the AZF3328 chip is the PCI cousin of the 31 * AZF3318 ("azt1020 pnp", "MM Pro 16") ISA chip, given very similar specs. 32 * 33 * The AZF3328 chip (note: AZF3328, *not* AZT3328, that's just the driver name 34 * for compatibility reasons) from Azfin (joint-venture of Aztech and Fincitec, 35 * Fincitec acquired by National Semiconductor in 2002, together with the 36 * Fincitec-related company ARSmikro) has the following features: 37 * 38 * - compatibility & compliance: 39 * - Microsoft PC 97 ("PC 97 Hardware Design Guide", 40 * http://www.microsoft.com/whdc/archive/pcguides.mspx) 41 * - Microsoft PC 98 Baseline Audio 42 * - MPU401 UART 43 * - Sound Blaster Emulation (DOS Box) 44 * - builtin AC97 conformant codec (SNR over 80dB) 45 * Note that "conformant" != "compliant"!! this chip's mixer register layout 46 * *differs* from the standard AC97 layout: 47 * they chose to not implement the headphone register (which is not a 48 * problem since it's merely optional), yet when doing this, they committed 49 * the grave sin of letting other registers follow immediately instead of 50 * keeping a headphone dummy register, thereby shifting the mixer register 51 * addresses illegally. So far unfortunately it looks like the very flexible 52 * ALSA AC97 support is still not enough to easily compensate for such a 53 * grave layout violation despite all tweaks and quirks mechanisms it offers. 54 * Well, not quite: now ac97 layer is much improved (bus-specific ops!), 55 * thus I was able to implement support - it's actually working quite well. 56 * An interesting item might be Aztech AMR 2800-W, since it's an AC97 57 * modem card which might reveal the Aztech-specific codec ID which 58 * we might want to pretend, too. Dito PCI168's brother, PCI368, 59 * where the advertising datasheet says it's AC97-based and has a 60 * Digital Enhanced Game Port. 61 * - builtin genuine OPL3 - verified to work fine, 20080506 62 * - full duplex 16bit playback/record at independent sampling rate 63 * - MPU401 (+ legacy address support, claimed by one official spec sheet) 64 * FIXME: how to enable legacy addr?? 65 * - game port (legacy address support) 66 * - builtin DirectInput support, helps reduce CPU overhead (interrupt-driven 67 * features supported). - See common term "Digital Enhanced Game Port"... 68 * (probably DirectInput 3.0 spec - confirm) 69 * - builtin 3D enhancement (said to be YAMAHA Ymersion) 70 * - built-in General DirectX timer having a 20 bits counter 71 * with 1us resolution (see below!) 72 * - I2S serial output port for external DAC 73 * [FIXME: 3.3V or 5V level? maximum rate is 66.2kHz right?] 74 * - supports 33MHz PCI spec 2.1, PCI power management 1.0, compliant with ACPI 75 * - supports hardware volume control 76 * - single chip low cost solution (128 pin QFP) 77 * - supports programmable Sub-vendor and Sub-system ID [24C02 SEEPROM chip] 78 * required for Microsoft's logo compliance (FIXME: where?) 79 * At least the Trident 4D Wave DX has one bit somewhere 80 * to enable writes to PCI subsystem VID registers, that should be it. 81 * This might easily be in extended PCI reg space, since PCI168 also has 82 * some custom data starting at 0x80. What kind of config settings 83 * are located in our extended PCI space anyway?? 84 * - PCI168 AP(W) card: power amplifier with 4 Watts/channel at 4 Ohms 85 * [TDA1517P chip] 86 * 87 * Note that this driver now is actually *better* than the Windows driver, 88 * since it additionally supports the card's 1MHz DirectX timer - just try 89 * the following snd-seq module parameters etc.: 90 * - options snd-seq seq_default_timer_class=2 seq_default_timer_sclass=0 91 * seq_default_timer_card=0 seq_client_load=1 seq_default_timer_device=0 92 * seq_default_timer_subdevice=0 seq_default_timer_resolution=1000000 93 * - "timidity -iAv -B2,8 -Os -EFreverb=0" 94 * - "pmidi -p 128:0 jazz.mid" 95 * 96 * OPL3 hardware playback testing, try something like: 97 * cat /proc/asound/hwdep 98 * and 99 * aconnect -o 100 * Then use 101 * sbiload -Dhw:x,y --opl3 /usr/share/sounds/opl3/std.o3 ......./drums.o3 102 * where x,y is the xx-yy number as given in hwdep. 103 * Then try 104 * pmidi -p a:b jazz.mid 105 * where a:b is the client number plus 0 usually, as given by aconnect above. 106 * Oh, and make sure to unmute the FM mixer control (doh!) 107 * NOTE: power use during OPL3 playback is _VERY_ high (70W --> 90W!) 108 * despite no CPU activity, possibly due to hindering ACPI idling somehow. 109 * Shouldn't be a problem of the AZF3328 chip itself, I'd hope. 110 * Higher PCM / FM mixer levels seem to conflict (causes crackling), 111 * at least sometimes. Maybe even use with hardware sequencer timer above :) 112 * adplay/adplug-utils might soon offer hardware-based OPL3 playback, too. 113 * 114 * Certain PCI versions of this card are susceptible to DMA traffic underruns 115 * in some systems (resulting in sound crackling/clicking/popping), 116 * probably because they don't have a DMA FIFO buffer or so. 117 * Overview (PCI ID/PCI subID/PCI rev.): 118 * - no DMA crackling on SiS735: 0x50DC/0x1801/16 119 * - unknown performance: 0x50DC/0x1801/10 120 * (well, it's not bad on an Athlon 1800 with now very optimized IRQ handler) 121 * 122 * Crackling happens with VIA chipsets or, in my case, an SiS735, which is 123 * supposed to be very fast and supposed to get rid of crackling much 124 * better than a VIA, yet ironically I still get crackling, like many other 125 * people with the same chipset. 126 * Possible remedies: 127 * - use speaker (amplifier) output instead of headphone output 128 * (in case crackling is due to overloaded output clipping) 129 * - plug card into a different PCI slot, preferably one that isn't shared 130 * too much (this helps a lot, but not completely!) 131 * - get rid of PCI VGA card, use AGP instead 132 * - upgrade or downgrade BIOS 133 * - fiddle with PCI latency settings (setpci -v -s BUSID latency_timer=XX) 134 * Not too helpful. 135 * - Disable ACPI/power management/"Auto Detect RAM/PCI Clk" in BIOS 136 * 137 * BUGS 138 * - full-duplex might *still* be problematic, however a recent test was fine 139 * - (non-bug) "Bass/Treble or 3D settings don't work" - they do get evaluated 140 * if you set PCM output switch to "pre 3D" instead of "post 3D". 141 * If this can't be set, then get a mixer application that Isn't Stupid (tm) 142 * (e.g. kmix, gamix) - unfortunately several are!! 143 * - locking is not entirely clean, especially the audio stream activity 144 * ints --> may be racy 145 * - an _unconnected_ secondary joystick at the gameport will be reported 146 * to be "active" (floating values, not precisely -1) due to the way we need 147 * to read the Digital Enhanced Game Port. Not sure whether it is fixable. 148 * 149 * TODO 150 * - use PCI_VDEVICE 151 * - verify driver status on x86_64 152 * - test multi-card driver operation 153 * - (ab)use 1MHz DirectX timer as kernel clocksource 154 * - test MPU401 MIDI playback etc. 155 * - add more power micro-management (disable various units of the card 156 * as long as they're unused, to improve audio quality and save power). 157 * However this requires more I/O ports which I haven't figured out yet 158 * and which thus might not even exist... 159 * The standard suspend/resume functionality could probably make use of 160 * some improvement, too... 161 * - figure out what all unknown port bits are responsible for 162 * - figure out some cleverly evil scheme to possibly make ALSA AC97 code 163 * fully accept our quite incompatible ""AC97"" mixer and thus save some 164 * code (but I'm not too optimistic that doing this is possible at all) 165 * - use MMIO (memory-mapped I/O)? Slightly faster access, e.g. for gameport. 166 */ 167 168#include <linux/io.h> 169#include <linux/init.h> 170#include <linux/bug.h> /* WARN_ONCE */ 171#include <linux/pci.h> 172#include <linux/delay.h> 173#include <linux/slab.h> 174#include <linux/gameport.h> 175#include <linux/module.h> 176#include <linux/dma-mapping.h> 177#include <sound/core.h> 178#include <sound/control.h> 179#include <sound/pcm.h> 180#include <sound/rawmidi.h> 181#include <sound/mpu401.h> 182#include <sound/opl3.h> 183#include <sound/initval.h> 184/* 185 * Config switch, to use ALSA's AC97 layer instead of old custom mixer crap. 186 * If the AC97 compatibility parts we needed to implement locally turn out 187 * to work nicely, then remove the old implementation eventually. 188 */ 189#define AZF_USE_AC97_LAYER 1 190 191#ifdef AZF_USE_AC97_LAYER 192#include <sound/ac97_codec.h> 193#endif 194#include "azt3328.h" 195 196MODULE_AUTHOR("Andreas Mohr <andi AT lisas.de>"); 197MODULE_DESCRIPTION("Aztech AZF3328 (PCI168)"); 198MODULE_LICENSE("GPL"); 199 200#if IS_REACHABLE(CONFIG_GAMEPORT) 201#define SUPPORT_GAMEPORT 1 202#endif 203 204/* === Debug settings === 205 Further diagnostic functionality than the settings below 206 does not need to be provided, since one can easily write a POSIX shell script 207 to dump the card's I/O ports (those listed in lspci -v -v): 208 dump() 209 { 210 local descr=$1; local addr=$2; local count=$3 211 212 echo "${descr}: ${count} @ ${addr}:" 213 dd if=/dev/port skip=`printf %d ${addr}` count=${count} bs=1 \ 214 2>/dev/null| hexdump -C 215 } 216 and then use something like 217 "dump joy200 0x200 8", "dump mpu388 0x388 4", "dump joy 0xb400 8", 218 "dump codec00 0xa800 32", "dump mixer 0xb800 64", "dump synth 0xbc00 8", 219 possibly within a "while true; do ... sleep 1; done" loop. 220 Tweaking ports could be done using 221 VALSTRING="`printf "%02x" $value`" 222 printf "\x""$VALSTRING"|dd of=/dev/port seek=`printf %d ${addr}` bs=1 \ 223 2>/dev/null 224*/ 225 226static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 227module_param_array(index, int, NULL, 0444); 228MODULE_PARM_DESC(index, "Index value for AZF3328 soundcard."); 229 230static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 231module_param_array(id, charp, NULL, 0444); 232MODULE_PARM_DESC(id, "ID string for AZF3328 soundcard."); 233 234static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 235module_param_array(enable, bool, NULL, 0444); 236MODULE_PARM_DESC(enable, "Enable AZF3328 soundcard."); 237 238static int seqtimer_scaling = 128; 239module_param(seqtimer_scaling, int, 0444); 240MODULE_PARM_DESC(seqtimer_scaling, "Set 1024000Hz sequencer timer scale factor (lockup danger!). Default 128."); 241 242enum snd_azf3328_codec_type { 243 /* warning: fixed indices (also used for bitmask checks!) */ 244 AZF_CODEC_PLAYBACK = 0, 245 AZF_CODEC_CAPTURE = 1, 246 AZF_CODEC_I2S_OUT = 2, 247}; 248 249struct snd_azf3328_codec_data { 250 unsigned long io_base; /* keep first! (avoid offset calc) */ 251 unsigned int dma_base; /* helper to avoid an indirection in hotpath */ 252 spinlock_t *lock; /* TODO: convert to our own per-codec lock member */ 253 struct snd_pcm_substream *substream; 254 bool running; 255 enum snd_azf3328_codec_type type; 256 const char *name; 257}; 258 259struct snd_azf3328 { 260 /* often-used fields towards beginning, then grouped */ 261 262 unsigned long ctrl_io; /* usually 0xb000, size 128 */ 263 unsigned long game_io; /* usually 0xb400, size 8 */ 264 unsigned long mpu_io; /* usually 0xb800, size 4 */ 265 unsigned long opl3_io; /* usually 0xbc00, size 8 */ 266 unsigned long mixer_io; /* usually 0xc000, size 64 */ 267 268 spinlock_t reg_lock; 269 270 struct snd_timer *timer; 271 272 struct snd_pcm *pcm[3]; 273 274 /* playback, recording and I2S out codecs */ 275 struct snd_azf3328_codec_data codecs[3]; 276 277#ifdef AZF_USE_AC97_LAYER 278 struct snd_ac97 *ac97; 279#endif 280 281 struct snd_card *card; 282 struct snd_rawmidi *rmidi; 283 284#ifdef SUPPORT_GAMEPORT 285 struct gameport *gameport; 286 u16 axes[4]; 287#endif 288 289 struct pci_dev *pci; 290 int irq; 291 292 /* register 0x6a is write-only, thus need to remember setting. 293 * If we need to add more registers here, then we might try to fold this 294 * into some transparent combined shadow register handling with 295 * CONFIG_PM register storage below, but that's slightly difficult. */ 296 u16 shadow_reg_ctrl_6AH; 297 298 /* register value containers for power management 299 * Note: not always full I/O range preserved (similar to Win driver!) */ 300 u32 saved_regs_ctrl[AZF_ALIGN(AZF_IO_SIZE_CTRL_PM) / 4]; 301 u32 saved_regs_game[AZF_ALIGN(AZF_IO_SIZE_GAME_PM) / 4]; 302 u32 saved_regs_mpu[AZF_ALIGN(AZF_IO_SIZE_MPU_PM) / 4]; 303 u32 saved_regs_opl3[AZF_ALIGN(AZF_IO_SIZE_OPL3_PM) / 4]; 304 u32 saved_regs_mixer[AZF_ALIGN(AZF_IO_SIZE_MIXER_PM) / 4]; 305}; 306 307static const struct pci_device_id snd_azf3328_ids[] = { 308 { 0x122D, 0x50DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* PCI168/3328 */ 309 { 0x122D, 0x80DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 3328 */ 310 { 0, } 311}; 312 313MODULE_DEVICE_TABLE(pci, snd_azf3328_ids); 314 315 316static int 317snd_azf3328_io_reg_setb(unsigned reg, u8 mask, bool do_set) 318{ 319 /* Well, strictly spoken, the inb/outb sequence isn't atomic 320 and would need locking. However we currently don't care 321 since it potentially complicates matters. */ 322 u8 prev = inb(reg), new; 323 324 new = (do_set) ? (prev|mask) : (prev & ~mask); 325 /* we need to always write the new value no matter whether it differs 326 * or not, since some register bits don't indicate their setting */ 327 outb(new, reg); 328 if (new != prev) 329 return 1; 330 331 return 0; 332} 333 334static inline void 335snd_azf3328_codec_outb(const struct snd_azf3328_codec_data *codec, 336 unsigned reg, 337 u8 value 338) 339{ 340 outb(value, codec->io_base + reg); 341} 342 343static inline u8 344snd_azf3328_codec_inb(const struct snd_azf3328_codec_data *codec, unsigned reg) 345{ 346 return inb(codec->io_base + reg); 347} 348 349static inline void 350snd_azf3328_codec_outw(const struct snd_azf3328_codec_data *codec, 351 unsigned reg, 352 u16 value 353) 354{ 355 outw(value, codec->io_base + reg); 356} 357 358static inline u16 359snd_azf3328_codec_inw(const struct snd_azf3328_codec_data *codec, unsigned reg) 360{ 361 return inw(codec->io_base + reg); 362} 363 364static inline void 365snd_azf3328_codec_outl_multi(const struct snd_azf3328_codec_data *codec, 366 unsigned reg, const void *buffer, int count 367) 368{ 369 unsigned long addr = codec->io_base + reg; 370 if (count) { 371 const u32 *buf = buffer; 372 do { 373 outl(*buf++, addr); 374 addr += 4; 375 } while (--count); 376 } 377} 378 379static inline u32 380snd_azf3328_codec_inl(const struct snd_azf3328_codec_data *codec, unsigned reg) 381{ 382 return inl(codec->io_base + reg); 383} 384 385static inline void 386snd_azf3328_ctrl_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value) 387{ 388 outb(value, chip->ctrl_io + reg); 389} 390 391static inline u8 392snd_azf3328_ctrl_inb(const struct snd_azf3328 *chip, unsigned reg) 393{ 394 return inb(chip->ctrl_io + reg); 395} 396 397static inline u16 398snd_azf3328_ctrl_inw(const struct snd_azf3328 *chip, unsigned reg) 399{ 400 return inw(chip->ctrl_io + reg); 401} 402 403static inline void 404snd_azf3328_ctrl_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value) 405{ 406 outw(value, chip->ctrl_io + reg); 407} 408 409static inline void 410snd_azf3328_ctrl_outl(const struct snd_azf3328 *chip, unsigned reg, u32 value) 411{ 412 outl(value, chip->ctrl_io + reg); 413} 414 415static inline void __maybe_unused 416snd_azf3328_game_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value) 417{ 418 outb(value, chip->game_io + reg); 419} 420 421static inline void __maybe_unused 422snd_azf3328_game_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value) 423{ 424 outw(value, chip->game_io + reg); 425} 426 427static inline u8 __maybe_unused 428snd_azf3328_game_inb(const struct snd_azf3328 *chip, unsigned reg) 429{ 430 return inb(chip->game_io + reg); 431} 432 433static inline u16 __maybe_unused 434snd_azf3328_game_inw(const struct snd_azf3328 *chip, unsigned reg) 435{ 436 return inw(chip->game_io + reg); 437} 438 439static inline void 440snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value) 441{ 442 outw(value, chip->mixer_io + reg); 443} 444 445static inline u16 446snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, unsigned reg) 447{ 448 return inw(chip->mixer_io + reg); 449} 450 451#define AZF_MUTE_BIT 0x80 452 453static bool 454snd_azf3328_mixer_mute_control(const struct snd_azf3328 *chip, 455 unsigned reg, bool do_mute 456) 457{ 458 unsigned long portbase = chip->mixer_io + reg + 1; 459 bool updated; 460 461 /* the mute bit is on the *second* (i.e. right) register of a 462 * left/right channel setting */ 463 updated = snd_azf3328_io_reg_setb(portbase, AZF_MUTE_BIT, do_mute); 464 465 /* indicate whether it was muted before */ 466 return (do_mute) ? !updated : updated; 467} 468 469static inline bool 470snd_azf3328_mixer_mute_control_master(const struct snd_azf3328 *chip, 471 bool do_mute 472) 473{ 474 return snd_azf3328_mixer_mute_control( 475 chip, 476 IDX_MIXER_PLAY_MASTER, 477 do_mute 478 ); 479} 480 481static inline bool 482snd_azf3328_mixer_mute_control_pcm(const struct snd_azf3328 *chip, 483 bool do_mute 484) 485{ 486 return snd_azf3328_mixer_mute_control( 487 chip, 488 IDX_MIXER_WAVEOUT, 489 do_mute 490 ); 491} 492 493static inline void 494snd_azf3328_mixer_reset(const struct snd_azf3328 *chip) 495{ 496 /* reset (close) mixer: 497 * first mute master volume, then reset 498 */ 499 snd_azf3328_mixer_mute_control_master(chip, 1); 500 snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000); 501} 502 503#ifdef AZF_USE_AC97_LAYER 504 505static inline void 506snd_azf3328_mixer_ac97_map_unsupported(const struct snd_azf3328 *chip, 507 unsigned short reg, const char *mode) 508{ 509 /* need to add some more or less clever emulation? */ 510 dev_warn(chip->card->dev, 511 "missing %s emulation for AC97 register 0x%02x!\n", 512 mode, reg); 513} 514 515/* 516 * Need to have _special_ AC97 mixer hardware register index mapper, 517 * to compensate for the issue of a rather AC97-incompatible hardware layout. 518 */ 519#define AZF_REG_MASK 0x3f 520#define AZF_AC97_REG_UNSUPPORTED 0x8000 521#define AZF_AC97_REG_REAL_IO_READ 0x4000 522#define AZF_AC97_REG_REAL_IO_WRITE 0x2000 523#define AZF_AC97_REG_REAL_IO_RW \ 524 (AZF_AC97_REG_REAL_IO_READ | AZF_AC97_REG_REAL_IO_WRITE) 525#define AZF_AC97_REG_EMU_IO_READ 0x0400 526#define AZF_AC97_REG_EMU_IO_WRITE 0x0200 527#define AZF_AC97_REG_EMU_IO_RW \ 528 (AZF_AC97_REG_EMU_IO_READ | AZF_AC97_REG_EMU_IO_WRITE) 529static unsigned short 530snd_azf3328_mixer_ac97_map_reg_idx(unsigned short reg) 531{ 532 static const struct { 533 unsigned short azf_reg; 534 } azf_reg_mapper[] = { 535 /* Especially when taking into consideration 536 * mono/stereo-based sequence of azf vs. AC97 control series, 537 * it's quite obvious that azf simply got rid 538 * of the AC97_HEADPHONE control at its intended offset, 539 * thus shifted _all_ controls by one, 540 * and _then_ simply added it as an FMSYNTH control at the end, 541 * to make up for the offset. 542 * This means we'll have to translate indices here as 543 * needed and then do some tiny AC97 patch action 544 * (snd_ac97_rename_vol_ctl() etc.) - that's it. 545 */ 546 { /* AC97_RESET */ IDX_MIXER_RESET 547 | AZF_AC97_REG_REAL_IO_WRITE 548 | AZF_AC97_REG_EMU_IO_READ }, 549 { /* AC97_MASTER */ IDX_MIXER_PLAY_MASTER }, 550 /* note large shift: AC97_HEADPHONE to IDX_MIXER_FMSYNTH! */ 551 { /* AC97_HEADPHONE */ IDX_MIXER_FMSYNTH }, 552 { /* AC97_MASTER_MONO */ IDX_MIXER_MODEMOUT }, 553 { /* AC97_MASTER_TONE */ IDX_MIXER_BASSTREBLE }, 554 { /* AC97_PC_BEEP */ IDX_MIXER_PCBEEP }, 555 { /* AC97_PHONE */ IDX_MIXER_MODEMIN }, 556 { /* AC97_MIC */ IDX_MIXER_MIC }, 557 { /* AC97_LINE */ IDX_MIXER_LINEIN }, 558 { /* AC97_CD */ IDX_MIXER_CDAUDIO }, 559 { /* AC97_VIDEO */ IDX_MIXER_VIDEO }, 560 { /* AC97_AUX */ IDX_MIXER_AUX }, 561 { /* AC97_PCM */ IDX_MIXER_WAVEOUT }, 562 { /* AC97_REC_SEL */ IDX_MIXER_REC_SELECT }, 563 { /* AC97_REC_GAIN */ IDX_MIXER_REC_VOLUME }, 564 { /* AC97_REC_GAIN_MIC */ AZF_AC97_REG_EMU_IO_RW }, 565 { /* AC97_GENERAL_PURPOSE */ IDX_MIXER_ADVCTL2 }, 566 { /* AC97_3D_CONTROL */ IDX_MIXER_ADVCTL1 }, 567 }; 568 569 unsigned short reg_azf = AZF_AC97_REG_UNSUPPORTED; 570 571 /* azf3328 supports the low-numbered and low-spec:ed range 572 of AC97 regs only */ 573 if (reg <= AC97_3D_CONTROL) { 574 unsigned short reg_idx = reg / 2; 575 reg_azf = azf_reg_mapper[reg_idx].azf_reg; 576 /* a translation-only entry means it's real read/write: */ 577 if (!(reg_azf & ~AZF_REG_MASK)) 578 reg_azf |= AZF_AC97_REG_REAL_IO_RW; 579 } else { 580 switch (reg) { 581 case AC97_POWERDOWN: 582 reg_azf = AZF_AC97_REG_EMU_IO_RW; 583 break; 584 case AC97_EXTENDED_ID: 585 reg_azf = AZF_AC97_REG_EMU_IO_READ; 586 break; 587 case AC97_EXTENDED_STATUS: 588 /* I don't know what the h*ll AC97 layer 589 * would consult this _extended_ register for 590 * given a base-AC97-advertised card, 591 * but let's just emulate it anyway :-P 592 */ 593 reg_azf = AZF_AC97_REG_EMU_IO_RW; 594 break; 595 case AC97_VENDOR_ID1: 596 case AC97_VENDOR_ID2: 597 reg_azf = AZF_AC97_REG_EMU_IO_READ; 598 break; 599 } 600 } 601 return reg_azf; 602} 603 604static const unsigned short 605azf_emulated_ac97_caps = 606 AC97_BC_DEDICATED_MIC | 607 AC97_BC_BASS_TREBLE | 608 /* Headphone is an FM Synth control here */ 609 AC97_BC_HEADPHONE | 610 /* no AC97_BC_LOUDNESS! */ 611 /* mask 0x7c00 is 612 vendor-specific 3D enhancement 613 vendor indicator. 614 Since there actually _is_ an 615 entry for Aztech Labs 616 (13), make damn sure 617 to indicate it. */ 618 (13 << 10); 619 620static const unsigned short 621azf_emulated_ac97_powerdown = 622 /* pretend everything to be active */ 623 AC97_PD_ADC_STATUS | 624 AC97_PD_DAC_STATUS | 625 AC97_PD_MIXER_STATUS | 626 AC97_PD_VREF_STATUS; 627 628/* 629 * Emulated, _inofficial_ vendor ID 630 * (there might be some devices such as the MR 2800-W 631 * which could reveal the real Aztech AC97 ID). 632 * We choose to use "AZT" prefix, and then use 1 to indicate PCI168 633 * (better don't use 0x68 since there's a PCI368 as well). 634 */ 635static const unsigned int 636azf_emulated_ac97_vendor_id = 0x415a5401; 637 638static unsigned short 639snd_azf3328_mixer_ac97_read(struct snd_ac97 *ac97, unsigned short reg_ac97) 640{ 641 const struct snd_azf3328 *chip = ac97->private_data; 642 unsigned short reg_azf = snd_azf3328_mixer_ac97_map_reg_idx(reg_ac97); 643 unsigned short reg_val = 0; 644 bool unsupported = false; 645 646 dev_dbg(chip->card->dev, "snd_azf3328_mixer_ac97_read reg_ac97 %u\n", 647 reg_ac97); 648 if (reg_azf & AZF_AC97_REG_UNSUPPORTED) 649 unsupported = true; 650 else { 651 if (reg_azf & AZF_AC97_REG_REAL_IO_READ) 652 reg_val = snd_azf3328_mixer_inw(chip, 653 reg_azf & AZF_REG_MASK); 654 else { 655 /* 656 * Proceed with dummy I/O read, 657 * to ensure compatible timing where this may matter. 658 * (ALSA AC97 layer usually doesn't call I/O functions 659 * due to intelligent I/O caching anyway) 660 * Choose a mixer register that's thoroughly unrelated 661 * to common audio (try to minimize distortion). 662 */ 663 snd_azf3328_mixer_inw(chip, IDX_MIXER_SOMETHING30H); 664 } 665 666 if (reg_azf & AZF_AC97_REG_EMU_IO_READ) { 667 switch (reg_ac97) { 668 case AC97_RESET: 669 reg_val |= azf_emulated_ac97_caps; 670 break; 671 case AC97_POWERDOWN: 672 reg_val |= azf_emulated_ac97_powerdown; 673 break; 674 case AC97_EXTENDED_ID: 675 case AC97_EXTENDED_STATUS: 676 /* AFAICS we simply can't support anything: */ 677 reg_val |= 0; 678 break; 679 case AC97_VENDOR_ID1: 680 reg_val = azf_emulated_ac97_vendor_id >> 16; 681 break; 682 case AC97_VENDOR_ID2: 683 reg_val = azf_emulated_ac97_vendor_id & 0xffff; 684 break; 685 default: 686 unsupported = true; 687 break; 688 } 689 } 690 } 691 if (unsupported) 692 snd_azf3328_mixer_ac97_map_unsupported(chip, reg_ac97, "read"); 693 694 return reg_val; 695} 696 697static void 698snd_azf3328_mixer_ac97_write(struct snd_ac97 *ac97, 699 unsigned short reg_ac97, unsigned short val) 700{ 701 const struct snd_azf3328 *chip = ac97->private_data; 702 unsigned short reg_azf = snd_azf3328_mixer_ac97_map_reg_idx(reg_ac97); 703 bool unsupported = false; 704 705 dev_dbg(chip->card->dev, 706 "snd_azf3328_mixer_ac97_write reg_ac97 %u val %u\n", 707 reg_ac97, val); 708 if (reg_azf & AZF_AC97_REG_UNSUPPORTED) 709 unsupported = true; 710 else { 711 if (reg_azf & AZF_AC97_REG_REAL_IO_WRITE) 712 snd_azf3328_mixer_outw( 713 chip, 714 reg_azf & AZF_REG_MASK, 715 val 716 ); 717 else 718 if (reg_azf & AZF_AC97_REG_EMU_IO_WRITE) { 719 switch (reg_ac97) { 720 case AC97_REC_GAIN_MIC: 721 case AC97_POWERDOWN: 722 case AC97_EXTENDED_STATUS: 723 /* 724 * Silently swallow these writes. 725 * Since for most registers our card doesn't 726 * actually support a comparable feature, 727 * this is exactly what we should do here. 728 * The AC97 layer's I/O caching probably 729 * automatically takes care of all the rest... 730 * (remembers written values etc.) 731 */ 732 break; 733 default: 734 unsupported = true; 735 break; 736 } 737 } 738 } 739 if (unsupported) 740 snd_azf3328_mixer_ac97_map_unsupported(chip, reg_ac97, "write"); 741} 742 743static int 744snd_azf3328_mixer_new(struct snd_azf3328 *chip) 745{ 746 struct snd_ac97_bus *bus; 747 struct snd_ac97_template ac97; 748 static const struct snd_ac97_bus_ops ops = { 749 .write = snd_azf3328_mixer_ac97_write, 750 .read = snd_azf3328_mixer_ac97_read, 751 }; 752 int rc; 753 754 memset(&ac97, 0, sizeof(ac97)); 755 ac97.scaps = AC97_SCAP_SKIP_MODEM 756 | AC97_SCAP_AUDIO /* we support audio! */ 757 | AC97_SCAP_NO_SPDIF; 758 ac97.private_data = chip; 759 ac97.pci = chip->pci; 760 761 /* 762 * ALSA's AC97 layer has terrible init crackling issues, 763 * unfortunately, and since it makes use of AC97_RESET, 764 * there's no use trying to mute Master Playback proactively. 765 */ 766 767 rc = snd_ac97_bus(chip->card, 0, &ops, NULL, &bus); 768 if (!rc) 769 rc = snd_ac97_mixer(bus, &ac97, &chip->ac97); 770 /* 771 * Make sure to complain loudly in case of AC97 init failure, 772 * since failure may happen quite often, 773 * due to this card being a very quirky AC97 "lookalike". 774 */ 775 if (rc) 776 dev_err(chip->card->dev, "AC97 init failed, err %d!\n", rc); 777 778 /* If we return an error here, then snd_card_free() should 779 * free up any ac97 codecs that got created, as well as the bus. 780 */ 781 return rc; 782} 783#else /* AZF_USE_AC97_LAYER */ 784static void 785snd_azf3328_mixer_write_volume_gradually(const struct snd_azf3328 *chip, 786 unsigned reg, 787 unsigned char dst_vol_left, 788 unsigned char dst_vol_right, 789 int chan_sel, int delay 790) 791{ 792 unsigned long portbase = chip->mixer_io + reg; 793 unsigned char curr_vol_left = 0, curr_vol_right = 0; 794 int left_change = 0, right_change = 0; 795 796 if (chan_sel & SET_CHAN_LEFT) { 797 curr_vol_left = inb(portbase + 1); 798 799 /* take care of muting flag contained in left channel */ 800 if (curr_vol_left & AZF_MUTE_BIT) 801 dst_vol_left |= AZF_MUTE_BIT; 802 else 803 dst_vol_left &= ~AZF_MUTE_BIT; 804 805 left_change = (curr_vol_left > dst_vol_left) ? -1 : 1; 806 } 807 808 if (chan_sel & SET_CHAN_RIGHT) { 809 curr_vol_right = inb(portbase + 0); 810 811 right_change = (curr_vol_right > dst_vol_right) ? -1 : 1; 812 } 813 814 do { 815 if (left_change) { 816 if (curr_vol_left != dst_vol_left) { 817 curr_vol_left += left_change; 818 outb(curr_vol_left, portbase + 1); 819 } else 820 left_change = 0; 821 } 822 if (right_change) { 823 if (curr_vol_right != dst_vol_right) { 824 curr_vol_right += right_change; 825 826 /* during volume change, the right channel is crackling 827 * somewhat more than the left channel, unfortunately. 828 * This seems to be a hardware issue. */ 829 outb(curr_vol_right, portbase + 0); 830 } else 831 right_change = 0; 832 } 833 if (delay) 834 mdelay(delay); 835 } while ((left_change) || (right_change)); 836} 837 838/* 839 * general mixer element 840 */ 841struct azf3328_mixer_reg { 842 unsigned reg; 843 unsigned int lchan_shift, rchan_shift; 844 unsigned int mask; 845 unsigned int invert: 1; 846 unsigned int stereo: 1; 847 unsigned int enum_c: 4; 848}; 849 850#define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \ 851 ((reg) | (lchan_shift << 8) | (rchan_shift << 12) | \ 852 (mask << 16) | \ 853 (invert << 24) | \ 854 (stereo << 25) | \ 855 (enum_c << 26)) 856 857static void snd_azf3328_mixer_reg_decode(struct azf3328_mixer_reg *r, unsigned long val) 858{ 859 r->reg = val & 0xff; 860 r->lchan_shift = (val >> 8) & 0x0f; 861 r->rchan_shift = (val >> 12) & 0x0f; 862 r->mask = (val >> 16) & 0xff; 863 r->invert = (val >> 24) & 1; 864 r->stereo = (val >> 25) & 1; 865 r->enum_c = (val >> 26) & 0x0f; 866} 867 868/* 869 * mixer switches/volumes 870 */ 871 872#define AZF3328_MIXER_SWITCH(xname, reg, shift, invert) \ 873{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 874 .info = snd_azf3328_info_mixer, \ 875 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ 876 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0x1, invert, 0, 0), \ 877} 878 879#define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \ 880{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 881 .info = snd_azf3328_info_mixer, \ 882 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ 883 .private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \ 884} 885 886#define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \ 887{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 888 .info = snd_azf3328_info_mixer, \ 889 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ 890 .private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \ 891} 892 893#define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \ 894{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 895 .info = snd_azf3328_info_mixer, \ 896 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ 897 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \ 898} 899 900#define AZF3328_MIXER_ENUM(xname, reg, enum_c, shift) \ 901{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 902 .info = snd_azf3328_info_mixer_enum, \ 903 .get = snd_azf3328_get_mixer_enum, .put = snd_azf3328_put_mixer_enum, \ 904 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0, 0, 0, enum_c), \ 905} 906 907static int 908snd_azf3328_info_mixer(struct snd_kcontrol *kcontrol, 909 struct snd_ctl_elem_info *uinfo) 910{ 911 struct azf3328_mixer_reg reg; 912 913 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 914 uinfo->type = reg.mask == 1 ? 915 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 916 uinfo->count = reg.stereo + 1; 917 uinfo->value.integer.min = 0; 918 uinfo->value.integer.max = reg.mask; 919 return 0; 920} 921 922static int 923snd_azf3328_get_mixer(struct snd_kcontrol *kcontrol, 924 struct snd_ctl_elem_value *ucontrol) 925{ 926 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); 927 struct azf3328_mixer_reg reg; 928 u16 oreg, val; 929 930 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 931 932 oreg = snd_azf3328_mixer_inw(chip, reg.reg); 933 val = (oreg >> reg.lchan_shift) & reg.mask; 934 if (reg.invert) 935 val = reg.mask - val; 936 ucontrol->value.integer.value[0] = val; 937 if (reg.stereo) { 938 val = (oreg >> reg.rchan_shift) & reg.mask; 939 if (reg.invert) 940 val = reg.mask - val; 941 ucontrol->value.integer.value[1] = val; 942 } 943 dev_dbg(chip->card->dev, 944 "get: %02x is %04x -> vol %02lx|%02lx (shift %02d|%02d, mask %02x, inv. %d, stereo %d)\n", 945 reg.reg, oreg, 946 ucontrol->value.integer.value[0], ucontrol->value.integer.value[1], 947 reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo); 948 return 0; 949} 950 951static int 952snd_azf3328_put_mixer(struct snd_kcontrol *kcontrol, 953 struct snd_ctl_elem_value *ucontrol) 954{ 955 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); 956 struct azf3328_mixer_reg reg; 957 u16 oreg, nreg, val; 958 959 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 960 oreg = snd_azf3328_mixer_inw(chip, reg.reg); 961 val = ucontrol->value.integer.value[0] & reg.mask; 962 if (reg.invert) 963 val = reg.mask - val; 964 nreg = oreg & ~(reg.mask << reg.lchan_shift); 965 nreg |= (val << reg.lchan_shift); 966 if (reg.stereo) { 967 val = ucontrol->value.integer.value[1] & reg.mask; 968 if (reg.invert) 969 val = reg.mask - val; 970 nreg &= ~(reg.mask << reg.rchan_shift); 971 nreg |= (val << reg.rchan_shift); 972 } 973 if (reg.mask >= 0x07) /* it's a volume control, so better take care */ 974 snd_azf3328_mixer_write_volume_gradually( 975 chip, reg.reg, nreg >> 8, nreg & 0xff, 976 /* just set both channels, doesn't matter */ 977 SET_CHAN_LEFT|SET_CHAN_RIGHT, 978 0); 979 else 980 snd_azf3328_mixer_outw(chip, reg.reg, nreg); 981 982 dev_dbg(chip->card->dev, 983 "put: %02x to %02lx|%02lx, oreg %04x; shift %02d|%02d -> nreg %04x; after: %04x\n", 984 reg.reg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1], 985 oreg, reg.lchan_shift, reg.rchan_shift, 986 nreg, snd_azf3328_mixer_inw(chip, reg.reg)); 987 return (nreg != oreg); 988} 989 990static int 991snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol, 992 struct snd_ctl_elem_info *uinfo) 993{ 994 static const char * const texts1[] = { 995 "Mic1", "Mic2" 996 }; 997 static const char * const texts2[] = { 998 "Mix", "Mic" 999 }; 1000 static const char * const texts3[] = { 1001 "Mic", "CD", "Video", "Aux", 1002 "Line", "Mix", "Mix Mono", "Phone" 1003 }; 1004 static const char * const texts4[] = { 1005 "pre 3D", "post 3D" 1006 }; 1007 struct azf3328_mixer_reg reg; 1008 const char * const *p = NULL; 1009 1010 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 1011 if (reg.reg == IDX_MIXER_ADVCTL2) { 1012 switch(reg.lchan_shift) { 1013 case 8: /* modem out sel */ 1014 p = texts1; 1015 break; 1016 case 9: /* mono sel source */ 1017 p = texts2; 1018 break; 1019 case 15: /* PCM Out Path */ 1020 p = texts4; 1021 break; 1022 } 1023 } else if (reg.reg == IDX_MIXER_REC_SELECT) 1024 p = texts3; 1025 1026 return snd_ctl_enum_info(uinfo, 1027 (reg.reg == IDX_MIXER_REC_SELECT) ? 2 : 1, 1028 reg.enum_c, p); 1029} 1030 1031static int 1032snd_azf3328_get_mixer_enum(struct snd_kcontrol *kcontrol, 1033 struct snd_ctl_elem_value *ucontrol) 1034{ 1035 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); 1036 struct azf3328_mixer_reg reg; 1037 unsigned short val; 1038 1039 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 1040 val = snd_azf3328_mixer_inw(chip, reg.reg); 1041 if (reg.reg == IDX_MIXER_REC_SELECT) { 1042 ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1); 1043 ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1); 1044 } else 1045 ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1); 1046 1047 dev_dbg(chip->card->dev, 1048 "get_enum: %02x is %04x -> %d|%d (shift %02d, enum_c %d)\n", 1049 reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1], 1050 reg.lchan_shift, reg.enum_c); 1051 return 0; 1052} 1053 1054static int 1055snd_azf3328_put_mixer_enum(struct snd_kcontrol *kcontrol, 1056 struct snd_ctl_elem_value *ucontrol) 1057{ 1058 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); 1059 struct azf3328_mixer_reg reg; 1060 u16 oreg, nreg, val; 1061 1062 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 1063 oreg = snd_azf3328_mixer_inw(chip, reg.reg); 1064 val = oreg; 1065 if (reg.reg == IDX_MIXER_REC_SELECT) { 1066 if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U || 1067 ucontrol->value.enumerated.item[1] > reg.enum_c - 1U) 1068 return -EINVAL; 1069 val = (ucontrol->value.enumerated.item[0] << 8) | 1070 (ucontrol->value.enumerated.item[1] << 0); 1071 } else { 1072 if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U) 1073 return -EINVAL; 1074 val &= ~((reg.enum_c - 1) << reg.lchan_shift); 1075 val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift); 1076 } 1077 snd_azf3328_mixer_outw(chip, reg.reg, val); 1078 nreg = val; 1079 1080 dev_dbg(chip->card->dev, 1081 "put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg); 1082 return (nreg != oreg); 1083} 1084 1085static const struct snd_kcontrol_new snd_azf3328_mixer_controls[] = { 1086 AZF3328_MIXER_SWITCH("Master Playback Switch", IDX_MIXER_PLAY_MASTER, 15, 1), 1087 AZF3328_MIXER_VOL_STEREO("Master Playback Volume", IDX_MIXER_PLAY_MASTER, 0x1f, 1), 1088 AZF3328_MIXER_SWITCH("PCM Playback Switch", IDX_MIXER_WAVEOUT, 15, 1), 1089 AZF3328_MIXER_VOL_STEREO("PCM Playback Volume", 1090 IDX_MIXER_WAVEOUT, 0x1f, 1), 1091 AZF3328_MIXER_SWITCH("PCM 3D Bypass Playback Switch", 1092 IDX_MIXER_ADVCTL2, 7, 1), 1093 AZF3328_MIXER_SWITCH("FM Playback Switch", IDX_MIXER_FMSYNTH, 15, 1), 1094 AZF3328_MIXER_VOL_STEREO("FM Playback Volume", IDX_MIXER_FMSYNTH, 0x1f, 1), 1095 AZF3328_MIXER_SWITCH("CD Playback Switch", IDX_MIXER_CDAUDIO, 15, 1), 1096 AZF3328_MIXER_VOL_STEREO("CD Playback Volume", IDX_MIXER_CDAUDIO, 0x1f, 1), 1097 AZF3328_MIXER_SWITCH("Capture Switch", IDX_MIXER_REC_VOLUME, 15, 1), 1098 AZF3328_MIXER_VOL_STEREO("Capture Volume", IDX_MIXER_REC_VOLUME, 0x0f, 0), 1099 AZF3328_MIXER_ENUM("Capture Source", IDX_MIXER_REC_SELECT, 8, 0), 1100 AZF3328_MIXER_SWITCH("Mic Playback Switch", IDX_MIXER_MIC, 15, 1), 1101 AZF3328_MIXER_VOL_MONO("Mic Playback Volume", IDX_MIXER_MIC, 0x1f, 1), 1102 AZF3328_MIXER_SWITCH("Mic Boost (+20dB)", IDX_MIXER_MIC, 6, 0), 1103 AZF3328_MIXER_SWITCH("Line Playback Switch", IDX_MIXER_LINEIN, 15, 1), 1104 AZF3328_MIXER_VOL_STEREO("Line Playback Volume", IDX_MIXER_LINEIN, 0x1f, 1), 1105 AZF3328_MIXER_SWITCH("Beep Playback Switch", IDX_MIXER_PCBEEP, 15, 1), 1106 AZF3328_MIXER_VOL_SPECIAL("Beep Playback Volume", IDX_MIXER_PCBEEP, 0x0f, 1, 1), 1107 AZF3328_MIXER_SWITCH("Video Playback Switch", IDX_MIXER_VIDEO, 15, 1), 1108 AZF3328_MIXER_VOL_STEREO("Video Playback Volume", IDX_MIXER_VIDEO, 0x1f, 1), 1109 AZF3328_MIXER_SWITCH("Aux Playback Switch", IDX_MIXER_AUX, 15, 1), 1110 AZF3328_MIXER_VOL_STEREO("Aux Playback Volume", IDX_MIXER_AUX, 0x1f, 1), 1111 AZF3328_MIXER_SWITCH("Modem Playback Switch", IDX_MIXER_MODEMOUT, 15, 1), 1112 AZF3328_MIXER_VOL_MONO("Modem Playback Volume", IDX_MIXER_MODEMOUT, 0x1f, 1), 1113 AZF3328_MIXER_SWITCH("Modem Capture Switch", IDX_MIXER_MODEMIN, 15, 1), 1114 AZF3328_MIXER_VOL_MONO("Modem Capture Volume", IDX_MIXER_MODEMIN, 0x1f, 1), 1115 AZF3328_MIXER_ENUM("Mic Select", IDX_MIXER_ADVCTL2, 2, 8), 1116 AZF3328_MIXER_ENUM("Mono Output Select", IDX_MIXER_ADVCTL2, 2, 9), 1117 AZF3328_MIXER_ENUM("PCM Output Route", IDX_MIXER_ADVCTL2, 2, 15), /* PCM Out Path, place in front since it controls *both* 3D and Bass/Treble! */ 1118 AZF3328_MIXER_VOL_SPECIAL("Tone Control - Treble", IDX_MIXER_BASSTREBLE, 0x07, 1, 0), 1119 AZF3328_MIXER_VOL_SPECIAL("Tone Control - Bass", IDX_MIXER_BASSTREBLE, 0x07, 9, 0), 1120 AZF3328_MIXER_SWITCH("3D Control - Switch", IDX_MIXER_ADVCTL2, 13, 0), 1121 AZF3328_MIXER_VOL_SPECIAL("3D Control - Width", IDX_MIXER_ADVCTL1, 0x07, 1, 0), /* "3D Width" */ 1122 AZF3328_MIXER_VOL_SPECIAL("3D Control - Depth", IDX_MIXER_ADVCTL1, 0x03, 8, 0), /* "Hifi 3D" */ 1123#if MIXER_TESTING 1124 AZF3328_MIXER_SWITCH("0", IDX_MIXER_ADVCTL2, 0, 0), 1125 AZF3328_MIXER_SWITCH("1", IDX_MIXER_ADVCTL2, 1, 0), 1126 AZF3328_MIXER_SWITCH("2", IDX_MIXER_ADVCTL2, 2, 0), 1127 AZF3328_MIXER_SWITCH("3", IDX_MIXER_ADVCTL2, 3, 0), 1128 AZF3328_MIXER_SWITCH("4", IDX_MIXER_ADVCTL2, 4, 0), 1129 AZF3328_MIXER_SWITCH("5", IDX_MIXER_ADVCTL2, 5, 0), 1130 AZF3328_MIXER_SWITCH("6", IDX_MIXER_ADVCTL2, 6, 0), 1131 AZF3328_MIXER_SWITCH("7", IDX_MIXER_ADVCTL2, 7, 0), 1132 AZF3328_MIXER_SWITCH("8", IDX_MIXER_ADVCTL2, 8, 0), 1133 AZF3328_MIXER_SWITCH("9", IDX_MIXER_ADVCTL2, 9, 0), 1134 AZF3328_MIXER_SWITCH("10", IDX_MIXER_ADVCTL2, 10, 0), 1135 AZF3328_MIXER_SWITCH("11", IDX_MIXER_ADVCTL2, 11, 0), 1136 AZF3328_MIXER_SWITCH("12", IDX_MIXER_ADVCTL2, 12, 0), 1137 AZF3328_MIXER_SWITCH("13", IDX_MIXER_ADVCTL2, 13, 0), 1138 AZF3328_MIXER_SWITCH("14", IDX_MIXER_ADVCTL2, 14, 0), 1139 AZF3328_MIXER_SWITCH("15", IDX_MIXER_ADVCTL2, 15, 0), 1140#endif 1141}; 1142 1143static const u16 snd_azf3328_init_values[][2] = { 1144 { IDX_MIXER_PLAY_MASTER, MIXER_MUTE_MASK|0x1f1f }, 1145 { IDX_MIXER_MODEMOUT, MIXER_MUTE_MASK|0x1f1f }, 1146 { IDX_MIXER_BASSTREBLE, 0x0000 }, 1147 { IDX_MIXER_PCBEEP, MIXER_MUTE_MASK|0x1f1f }, 1148 { IDX_MIXER_MODEMIN, MIXER_MUTE_MASK|0x1f1f }, 1149 { IDX_MIXER_MIC, MIXER_MUTE_MASK|0x001f }, 1150 { IDX_MIXER_LINEIN, MIXER_MUTE_MASK|0x1f1f }, 1151 { IDX_MIXER_CDAUDIO, MIXER_MUTE_MASK|0x1f1f }, 1152 { IDX_MIXER_VIDEO, MIXER_MUTE_MASK|0x1f1f }, 1153 { IDX_MIXER_AUX, MIXER_MUTE_MASK|0x1f1f }, 1154 { IDX_MIXER_WAVEOUT, MIXER_MUTE_MASK|0x1f1f }, 1155 { IDX_MIXER_FMSYNTH, MIXER_MUTE_MASK|0x1f1f }, 1156 { IDX_MIXER_REC_VOLUME, MIXER_MUTE_MASK|0x0707 }, 1157}; 1158 1159static int 1160snd_azf3328_mixer_new(struct snd_azf3328 *chip) 1161{ 1162 struct snd_card *card; 1163 const struct snd_kcontrol_new *sw; 1164 unsigned int idx; 1165 int err; 1166 1167 if (snd_BUG_ON(!chip || !chip->card)) 1168 return -EINVAL; 1169 1170 card = chip->card; 1171 1172 /* mixer reset */ 1173 snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000); 1174 1175 /* mute and zero volume channels */ 1176 for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_init_values); ++idx) { 1177 snd_azf3328_mixer_outw(chip, 1178 snd_azf3328_init_values[idx][0], 1179 snd_azf3328_init_values[idx][1]); 1180 } 1181 1182 /* add mixer controls */ 1183 sw = snd_azf3328_mixer_controls; 1184 for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_mixer_controls); 1185 ++idx, ++sw) { 1186 err = snd_ctl_add(chip->card, snd_ctl_new1(sw, chip)); 1187 if (err < 0) 1188 return err; 1189 } 1190 snd_component_add(card, "AZF3328 mixer"); 1191 strscpy(card->mixername, "AZF3328 mixer"); 1192 1193 return 0; 1194} 1195#endif /* AZF_USE_AC97_LAYER */ 1196 1197static void 1198snd_azf3328_codec_setfmt(struct snd_azf3328_codec_data *codec, 1199 enum azf_freq_t bitrate, 1200 unsigned int format_width, 1201 unsigned int channels 1202) 1203{ 1204 u16 val = 0xff00; 1205 u8 freq = 0; 1206 1207 switch (bitrate) { 1208 case AZF_FREQ_4000: freq = SOUNDFORMAT_FREQ_SUSPECTED_4000; break; 1209 case AZF_FREQ_4800: freq = SOUNDFORMAT_FREQ_SUSPECTED_4800; break; 1210 case AZF_FREQ_5512: 1211 /* the AZF3328 names it "5510" for some strange reason */ 1212 freq = SOUNDFORMAT_FREQ_5510; break; 1213 case AZF_FREQ_6620: freq = SOUNDFORMAT_FREQ_6620; break; 1214 case AZF_FREQ_8000: freq = SOUNDFORMAT_FREQ_8000; break; 1215 case AZF_FREQ_9600: freq = SOUNDFORMAT_FREQ_9600; break; 1216 case AZF_FREQ_11025: freq = SOUNDFORMAT_FREQ_11025; break; 1217 case AZF_FREQ_13240: freq = SOUNDFORMAT_FREQ_SUSPECTED_13240; break; 1218 case AZF_FREQ_16000: freq = SOUNDFORMAT_FREQ_16000; break; 1219 case AZF_FREQ_22050: freq = SOUNDFORMAT_FREQ_22050; break; 1220 case AZF_FREQ_32000: freq = SOUNDFORMAT_FREQ_32000; break; 1221 default: 1222 pr_warn("azf3328: unknown bitrate %d, assuming 44.1kHz!\n", bitrate); 1223 fallthrough; 1224 case AZF_FREQ_44100: freq = SOUNDFORMAT_FREQ_44100; break; 1225 case AZF_FREQ_48000: freq = SOUNDFORMAT_FREQ_48000; break; 1226 case AZF_FREQ_66200: freq = SOUNDFORMAT_FREQ_SUSPECTED_66200; break; 1227 } 1228 /* val = 0xff07; 3m27.993s (65301Hz; -> 64000Hz???) hmm, 66120, 65967, 66123 */ 1229 /* val = 0xff09; 17m15.098s (13123,478Hz; -> 12000Hz???) hmm, 13237.2Hz? */ 1230 /* val = 0xff0a; 47m30.599s (4764,891Hz; -> 4800Hz???) yup, 4803Hz */ 1231 /* val = 0xff0c; 57m0.510s (4010,263Hz; -> 4000Hz???) yup, 4003Hz */ 1232 /* val = 0xff05; 5m11.556s (... -> 44100Hz) */ 1233 /* val = 0xff03; 10m21.529s (21872,463Hz; -> 22050Hz???) */ 1234 /* val = 0xff0f; 20m41.883s (10937,993Hz; -> 11025Hz???) */ 1235 /* val = 0xff0d; 41m23.135s (5523,600Hz; -> 5512Hz???) */ 1236 /* val = 0xff0e; 28m30.777s (8017Hz; -> 8000Hz???) */ 1237 1238 val |= freq; 1239 1240 if (channels == 2) 1241 val |= SOUNDFORMAT_FLAG_2CHANNELS; 1242 1243 if (format_width == 16) 1244 val |= SOUNDFORMAT_FLAG_16BIT; 1245 1246 guard(spinlock_irqsave)(codec->lock); 1247 1248 /* set bitrate/format */ 1249 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_SOUNDFORMAT, val); 1250 1251 /* changing the bitrate/format settings switches off the 1252 * audio output with an annoying click in case of 8/16bit format change 1253 * (maybe shutting down DAC/ADC?), thus immediately 1254 * do some tweaking to reenable it and get rid of the clicking 1255 * (FIXME: yes, it works, but what exactly am I doing here?? :) 1256 * FIXME: does this have some side effects for full-duplex 1257 * or other dramatic side effects? */ 1258 /* do it for non-capture codecs only */ 1259 if (codec->type != AZF_CODEC_CAPTURE) 1260 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1261 snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS) | 1262 DMA_RUN_SOMETHING1 | 1263 DMA_RUN_SOMETHING2 | 1264 SOMETHING_ALMOST_ALWAYS_SET | 1265 DMA_EPILOGUE_SOMETHING | 1266 DMA_SOMETHING_ELSE 1267 ); 1268} 1269 1270static inline void 1271snd_azf3328_codec_setfmt_lowpower(struct snd_azf3328_codec_data *codec 1272) 1273{ 1274 /* choose lowest frequency for low power consumption. 1275 * While this will cause louder noise due to rather coarse frequency, 1276 * it should never matter since output should always 1277 * get disabled properly when idle anyway. */ 1278 snd_azf3328_codec_setfmt(codec, AZF_FREQ_4000, 8, 1); 1279} 1280 1281static void 1282snd_azf3328_ctrl_reg_6AH_update(struct snd_azf3328 *chip, 1283 unsigned bitmask, 1284 bool enable 1285) 1286{ 1287 bool do_mask = !enable; 1288 if (do_mask) 1289 chip->shadow_reg_ctrl_6AH |= bitmask; 1290 else 1291 chip->shadow_reg_ctrl_6AH &= ~bitmask; 1292 dev_dbg(chip->card->dev, 1293 "6AH_update mask 0x%04x do_mask %d: val 0x%04x\n", 1294 bitmask, do_mask, chip->shadow_reg_ctrl_6AH); 1295 snd_azf3328_ctrl_outw(chip, IDX_IO_6AH, chip->shadow_reg_ctrl_6AH); 1296} 1297 1298static inline void 1299snd_azf3328_ctrl_enable_codecs(struct snd_azf3328 *chip, bool enable) 1300{ 1301 dev_dbg(chip->card->dev, "codec_enable %d\n", enable); 1302 /* no idea what exactly is being done here, but I strongly assume it's 1303 * PM related */ 1304 snd_azf3328_ctrl_reg_6AH_update( 1305 chip, IO_6A_PAUSE_PLAYBACK_BIT8, enable 1306 ); 1307} 1308 1309static void 1310snd_azf3328_ctrl_codec_activity(struct snd_azf3328 *chip, 1311 enum snd_azf3328_codec_type codec_type, 1312 bool enable 1313) 1314{ 1315 struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type]; 1316 bool need_change = (codec->running != enable); 1317 1318 dev_dbg(chip->card->dev, 1319 "codec_activity: %s codec, enable %d, need_change %d\n", 1320 codec->name, enable, need_change 1321 ); 1322 if (need_change) { 1323 static const struct { 1324 enum snd_azf3328_codec_type other1; 1325 enum snd_azf3328_codec_type other2; 1326 } peer_codecs[3] = 1327 { { AZF_CODEC_CAPTURE, AZF_CODEC_I2S_OUT }, 1328 { AZF_CODEC_PLAYBACK, AZF_CODEC_I2S_OUT }, 1329 { AZF_CODEC_PLAYBACK, AZF_CODEC_CAPTURE } }; 1330 bool call_function; 1331 1332 if (enable) 1333 /* if enable codec, call enable_codecs func 1334 to enable codec supply... */ 1335 call_function = 1; 1336 else { 1337 /* ...otherwise call enable_codecs func 1338 (which globally shuts down operation of codecs) 1339 only in case the other codecs are currently 1340 not active either! */ 1341 call_function = 1342 ((!chip->codecs[peer_codecs[codec_type].other1] 1343 .running) 1344 && (!chip->codecs[peer_codecs[codec_type].other2] 1345 .running)); 1346 } 1347 if (call_function) 1348 snd_azf3328_ctrl_enable_codecs(chip, enable); 1349 1350 /* ...and adjust clock, too 1351 * (reduce noise and power consumption) */ 1352 if (!enable) 1353 snd_azf3328_codec_setfmt_lowpower(codec); 1354 codec->running = enable; 1355 } 1356} 1357 1358static void 1359snd_azf3328_codec_setdmaa(struct snd_azf3328 *chip, 1360 struct snd_azf3328_codec_data *codec, 1361 unsigned long addr, 1362 unsigned int period_bytes, 1363 unsigned int buffer_bytes 1364) 1365{ 1366 WARN_ONCE(period_bytes & 1, "odd period length!?\n"); 1367 WARN_ONCE(buffer_bytes != 2 * period_bytes, 1368 "missed our input expectations! %u vs. %u\n", 1369 buffer_bytes, period_bytes); 1370 if (!codec->running) { 1371 /* AZF3328 uses a two buffer pointer DMA transfer approach */ 1372 1373 /* width 32bit (prevent overflow): */ 1374 u32 area_length; 1375 struct codec_setup_io { 1376 u32 dma_start_1; 1377 u32 dma_start_2; 1378 u32 dma_lengths; 1379 } __packed setup_io; 1380 1381 area_length = buffer_bytes/2; 1382 1383 setup_io.dma_start_1 = addr; 1384 setup_io.dma_start_2 = addr+area_length; 1385 1386 dev_dbg(chip->card->dev, 1387 "setdma: buffers %08x[%u] / %08x[%u], %u, %u\n", 1388 setup_io.dma_start_1, area_length, 1389 setup_io.dma_start_2, area_length, 1390 period_bytes, buffer_bytes); 1391 1392 /* Hmm, are we really supposed to decrement this by 1?? 1393 Most definitely certainly not: configuring full length does 1394 work properly (i.e. likely better), and BTW we 1395 violated possibly differing frame sizes with this... 1396 1397 area_length--; |* max. index *| 1398 */ 1399 1400 /* build combined I/O buffer length word */ 1401 setup_io.dma_lengths = (area_length << 16) | (area_length); 1402 1403 guard(spinlock_irqsave)(codec->lock); 1404 snd_azf3328_codec_outl_multi( 1405 codec, IDX_IO_CODEC_DMA_START_1, &setup_io, 3 1406 ); 1407 } 1408} 1409 1410static int 1411snd_azf3328_pcm_prepare(struct snd_pcm_substream *substream) 1412{ 1413 struct snd_pcm_runtime *runtime = substream->runtime; 1414 struct snd_azf3328_codec_data *codec = runtime->private_data; 1415#if 0 1416 unsigned int size = snd_pcm_lib_buffer_bytes(substream); 1417 unsigned int count = snd_pcm_lib_period_bytes(substream); 1418#endif 1419 1420 codec->dma_base = runtime->dma_addr; 1421 1422#if 0 1423 snd_azf3328_codec_setfmt(codec, 1424 runtime->rate, 1425 snd_pcm_format_width(runtime->format), 1426 runtime->channels); 1427 snd_azf3328_codec_setdmaa(chip, codec, 1428 runtime->dma_addr, count, size); 1429#endif 1430 return 0; 1431} 1432 1433static int 1434snd_azf3328_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1435{ 1436 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream); 1437 struct snd_pcm_runtime *runtime = substream->runtime; 1438 struct snd_azf3328_codec_data *codec = runtime->private_data; 1439 int result = 0; 1440 u16 flags1; 1441 bool previously_muted = false; 1442 bool is_main_mixer_playback_codec = (AZF_CODEC_PLAYBACK == codec->type); 1443 1444 switch (cmd) { 1445 case SNDRV_PCM_TRIGGER_START: 1446 dev_dbg(chip->card->dev, "START PCM %s\n", codec->name); 1447 1448 if (is_main_mixer_playback_codec) { 1449 /* mute WaveOut (avoid clicking during setup) */ 1450 previously_muted = 1451 snd_azf3328_mixer_mute_control_pcm( 1452 chip, 1 1453 ); 1454 } 1455 1456 snd_azf3328_codec_setfmt(codec, 1457 runtime->rate, 1458 snd_pcm_format_width(runtime->format), 1459 runtime->channels); 1460 1461 scoped_guard(spinlock, codec->lock) { 1462 /* first, remember current value: */ 1463 flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS); 1464 1465 /* stop transfer */ 1466 flags1 &= ~DMA_RESUME; 1467 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1468 1469 /* FIXME: clear interrupts or what??? */ 1470 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_IRQTYPE, 0xffff); 1471 } 1472 1473 snd_azf3328_codec_setdmaa(chip, codec, runtime->dma_addr, 1474 snd_pcm_lib_period_bytes(substream), 1475 snd_pcm_lib_buffer_bytes(substream) 1476 ); 1477 1478 scoped_guard(spinlock, codec->lock) { 1479#ifdef WIN9X 1480 /* FIXME: enable playback/recording??? */ 1481 flags1 |= DMA_RUN_SOMETHING1 | DMA_RUN_SOMETHING2; 1482 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1483 1484 /* start transfer again */ 1485 /* FIXME: what is this value (0x0010)??? */ 1486 flags1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING; 1487 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1488#else /* NT4 */ 1489 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1490 0x0000); 1491 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1492 DMA_RUN_SOMETHING1); 1493 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1494 DMA_RUN_SOMETHING1 | 1495 DMA_RUN_SOMETHING2); 1496 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1497 DMA_RESUME | 1498 SOMETHING_ALMOST_ALWAYS_SET | 1499 DMA_EPILOGUE_SOMETHING | 1500 DMA_SOMETHING_ELSE); 1501#endif 1502 } 1503 snd_azf3328_ctrl_codec_activity(chip, codec->type, 1); 1504 1505 if (is_main_mixer_playback_codec) { 1506 /* now unmute WaveOut */ 1507 if (!previously_muted) 1508 snd_azf3328_mixer_mute_control_pcm( 1509 chip, 0 1510 ); 1511 } 1512 1513 dev_dbg(chip->card->dev, "PCM STARTED %s\n", codec->name); 1514 break; 1515 case SNDRV_PCM_TRIGGER_RESUME: 1516 dev_dbg(chip->card->dev, "PCM RESUME %s\n", codec->name); 1517 /* resume codec if we were active */ 1518 scoped_guard(spinlock, codec->lock) { 1519 if (codec->running) 1520 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1521 snd_azf3328_codec_inw( 1522 codec, IDX_IO_CODEC_DMA_FLAGS 1523 ) | DMA_RESUME 1524 ); 1525 } 1526 break; 1527 case SNDRV_PCM_TRIGGER_STOP: 1528 dev_dbg(chip->card->dev, "PCM STOP %s\n", codec->name); 1529 1530 if (is_main_mixer_playback_codec) { 1531 /* mute WaveOut (avoid clicking during setup) */ 1532 previously_muted = 1533 snd_azf3328_mixer_mute_control_pcm( 1534 chip, 1 1535 ); 1536 } 1537 1538 scoped_guard(spinlock, codec->lock) { 1539 /* first, remember current value: */ 1540 flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS); 1541 1542 /* stop transfer */ 1543 flags1 &= ~DMA_RESUME; 1544 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1545 1546 /* hmm, is this really required? we're resetting the same bit 1547 * immediately thereafter... */ 1548 flags1 |= DMA_RUN_SOMETHING1; 1549 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1550 1551 flags1 &= ~DMA_RUN_SOMETHING1; 1552 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1553 } 1554 snd_azf3328_ctrl_codec_activity(chip, codec->type, 0); 1555 1556 if (is_main_mixer_playback_codec) { 1557 /* now unmute WaveOut */ 1558 if (!previously_muted) 1559 snd_azf3328_mixer_mute_control_pcm( 1560 chip, 0 1561 ); 1562 } 1563 1564 dev_dbg(chip->card->dev, "PCM STOPPED %s\n", codec->name); 1565 break; 1566 case SNDRV_PCM_TRIGGER_SUSPEND: 1567 dev_dbg(chip->card->dev, "PCM SUSPEND %s\n", codec->name); 1568 /* make sure codec is stopped */ 1569 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1570 snd_azf3328_codec_inw( 1571 codec, IDX_IO_CODEC_DMA_FLAGS 1572 ) & ~DMA_RESUME 1573 ); 1574 break; 1575 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1576 WARN(1, "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n"); 1577 break; 1578 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1579 WARN(1, "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n"); 1580 break; 1581 default: 1582 WARN(1, "FIXME: unknown trigger mode!\n"); 1583 return -EINVAL; 1584 } 1585 1586 return result; 1587} 1588 1589static snd_pcm_uframes_t 1590snd_azf3328_pcm_pointer(struct snd_pcm_substream *substream 1591) 1592{ 1593 const struct snd_azf3328_codec_data *codec = 1594 substream->runtime->private_data; 1595 unsigned long result; 1596 snd_pcm_uframes_t frmres; 1597 1598 result = snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_CURRPOS); 1599 1600 /* calculate offset */ 1601#ifdef QUERY_HARDWARE 1602 result -= snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_START_1); 1603#else 1604 result -= codec->dma_base; 1605#endif 1606 frmres = bytes_to_frames( substream->runtime, result); 1607 dev_dbg(substream->pcm->card->dev, "%08li %s @ 0x%8lx, frames %8ld\n", 1608 jiffies, codec->name, result, frmres); 1609 return frmres; 1610} 1611 1612/******************************************************************/ 1613 1614#ifdef SUPPORT_GAMEPORT 1615static inline void 1616snd_azf3328_gameport_irq_enable(struct snd_azf3328 *chip, 1617 bool enable 1618) 1619{ 1620 snd_azf3328_io_reg_setb( 1621 chip->game_io+IDX_GAME_HWCONFIG, 1622 GAME_HWCFG_IRQ_ENABLE, 1623 enable 1624 ); 1625} 1626 1627static inline void 1628snd_azf3328_gameport_legacy_address_enable(struct snd_azf3328 *chip, 1629 bool enable 1630) 1631{ 1632 snd_azf3328_io_reg_setb( 1633 chip->game_io+IDX_GAME_HWCONFIG, 1634 GAME_HWCFG_LEGACY_ADDRESS_ENABLE, 1635 enable 1636 ); 1637} 1638 1639static void 1640snd_azf3328_gameport_set_counter_frequency(struct snd_azf3328 *chip, 1641 unsigned int freq_cfg 1642) 1643{ 1644 snd_azf3328_io_reg_setb( 1645 chip->game_io+IDX_GAME_HWCONFIG, 1646 0x02, 1647 (freq_cfg & 1) != 0 1648 ); 1649 snd_azf3328_io_reg_setb( 1650 chip->game_io+IDX_GAME_HWCONFIG, 1651 0x04, 1652 (freq_cfg & 2) != 0 1653 ); 1654} 1655 1656static inline void 1657snd_azf3328_gameport_axis_circuit_enable(struct snd_azf3328 *chip, bool enable) 1658{ 1659 snd_azf3328_ctrl_reg_6AH_update( 1660 chip, IO_6A_SOMETHING2_GAMEPORT, enable 1661 ); 1662} 1663 1664static inline void 1665snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip) 1666{ 1667 /* 1668 * skeleton handler only 1669 * (we do not want axis reading in interrupt handler - too much load!) 1670 */ 1671 dev_dbg(chip->card->dev, "gameport irq\n"); 1672 1673 /* this should ACK the gameport IRQ properly, hopefully. */ 1674 snd_azf3328_game_inw(chip, IDX_GAME_AXIS_VALUE); 1675} 1676 1677static int 1678snd_azf3328_gameport_open(struct gameport *gameport, int mode) 1679{ 1680 struct snd_azf3328 *chip = gameport_get_port_data(gameport); 1681 int res; 1682 1683 dev_dbg(chip->card->dev, "gameport_open, mode %d\n", mode); 1684 switch (mode) { 1685 case GAMEPORT_MODE_COOKED: 1686 case GAMEPORT_MODE_RAW: 1687 res = 0; 1688 break; 1689 default: 1690 res = -1; 1691 break; 1692 } 1693 1694 snd_azf3328_gameport_set_counter_frequency(chip, 1695 GAME_HWCFG_ADC_COUNTER_FREQ_STD); 1696 snd_azf3328_gameport_axis_circuit_enable(chip, (res == 0)); 1697 1698 return res; 1699} 1700 1701static void 1702snd_azf3328_gameport_close(struct gameport *gameport) 1703{ 1704 struct snd_azf3328 *chip = gameport_get_port_data(gameport); 1705 1706 dev_dbg(chip->card->dev, "gameport_close\n"); 1707 snd_azf3328_gameport_set_counter_frequency(chip, 1708 GAME_HWCFG_ADC_COUNTER_FREQ_1_200); 1709 snd_azf3328_gameport_axis_circuit_enable(chip, 0); 1710} 1711 1712static int 1713snd_azf3328_gameport_cooked_read(struct gameport *gameport, 1714 int *axes, 1715 int *buttons 1716) 1717{ 1718 struct snd_azf3328 *chip = gameport_get_port_data(gameport); 1719 int i; 1720 u8 val; 1721 1722 if (snd_BUG_ON(!chip)) 1723 return 0; 1724 1725 guard(spinlock_irqsave)(&chip->reg_lock); 1726 val = snd_azf3328_game_inb(chip, IDX_GAME_LEGACY_COMPATIBLE); 1727 *buttons = (~(val) >> 4) & 0xf; 1728 1729 /* ok, this one is a bit dirty: cooked_read is being polled by a timer, 1730 * thus we're atomic and cannot actively wait in here 1731 * (which would be useful for us since it probably would be better 1732 * to trigger a measurement in here, then wait a short amount of 1733 * time until it's finished, then read values of _this_ measurement). 1734 * 1735 * Thus we simply resort to reading values if they're available already 1736 * and trigger the next measurement. 1737 */ 1738 1739 val = snd_azf3328_game_inb(chip, IDX_GAME_AXES_CONFIG); 1740 if (val & GAME_AXES_SAMPLING_READY) { 1741 for (i = 0; i < ARRAY_SIZE(chip->axes); ++i) { 1742 /* configure the axis to read */ 1743 val = (i << 4) | 0x0f; 1744 snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val); 1745 1746 chip->axes[i] = snd_azf3328_game_inw( 1747 chip, IDX_GAME_AXIS_VALUE 1748 ); 1749 } 1750 } 1751 1752 /* trigger next sampling of axes, to be evaluated the next time we 1753 * enter this function */ 1754 1755 /* for some very, very strange reason we cannot enable 1756 * Measurement Ready monitoring for all axes here, 1757 * at least not when only one joystick connected */ 1758 val = 0x03; /* we're able to monitor axes 1 and 2 only */ 1759 snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val); 1760 1761 snd_azf3328_game_outw(chip, IDX_GAME_AXIS_VALUE, 0xffff); 1762 1763 for (i = 0; i < ARRAY_SIZE(chip->axes); i++) { 1764 axes[i] = chip->axes[i]; 1765 if (axes[i] == 0xffff) 1766 axes[i] = -1; 1767 } 1768 1769 dev_dbg(chip->card->dev, "cooked_read: axes %d %d %d %d buttons %d\n", 1770 axes[0], axes[1], axes[2], axes[3], *buttons); 1771 1772 return 0; 1773} 1774 1775static int 1776snd_azf3328_gameport(struct snd_azf3328 *chip, int dev) 1777{ 1778 struct gameport *gp; 1779 1780 chip->gameport = gp = gameport_allocate_port(); 1781 if (!gp) { 1782 dev_err(chip->card->dev, "cannot alloc memory for gameport\n"); 1783 return -ENOMEM; 1784 } 1785 1786 gameport_set_name(gp, "AZF3328 Gameport"); 1787 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); 1788 gameport_set_dev_parent(gp, &chip->pci->dev); 1789 gp->io = chip->game_io; 1790 gameport_set_port_data(gp, chip); 1791 1792 gp->open = snd_azf3328_gameport_open; 1793 gp->close = snd_azf3328_gameport_close; 1794 gp->fuzz = 16; /* seems ok */ 1795 gp->cooked_read = snd_azf3328_gameport_cooked_read; 1796 1797 /* DISABLE legacy address: we don't need it! */ 1798 snd_azf3328_gameport_legacy_address_enable(chip, 0); 1799 1800 snd_azf3328_gameport_set_counter_frequency(chip, 1801 GAME_HWCFG_ADC_COUNTER_FREQ_1_200); 1802 snd_azf3328_gameport_axis_circuit_enable(chip, 0); 1803 1804 gameport_register_port(chip->gameport); 1805 1806 return 0; 1807} 1808 1809static void 1810snd_azf3328_gameport_free(struct snd_azf3328 *chip) 1811{ 1812 if (chip->gameport) { 1813 gameport_unregister_port(chip->gameport); 1814 chip->gameport = NULL; 1815 } 1816 snd_azf3328_gameport_irq_enable(chip, 0); 1817} 1818#else 1819static inline int 1820snd_azf3328_gameport(struct snd_azf3328 *chip, int dev) { return -ENOSYS; } 1821static inline void 1822snd_azf3328_gameport_free(struct snd_azf3328 *chip) { } 1823static inline void 1824snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip) 1825{ 1826 dev_warn(chip->card->dev, "huh, game port IRQ occurred!?\n"); 1827} 1828#endif /* SUPPORT_GAMEPORT */ 1829 1830/******************************************************************/ 1831 1832static inline void 1833snd_azf3328_irq_log_unknown_type(struct snd_azf3328 *chip, u8 which) 1834{ 1835 dev_dbg(chip->card->dev, 1836 "unknown IRQ type (%x) occurred, please report!\n", 1837 which); 1838} 1839 1840static inline void 1841snd_azf3328_pcm_interrupt(struct snd_azf3328 *chip, 1842 const struct snd_azf3328_codec_data *first_codec, 1843 u8 status 1844) 1845{ 1846 u8 which; 1847 enum snd_azf3328_codec_type codec_type; 1848 const struct snd_azf3328_codec_data *codec = first_codec; 1849 1850 for (codec_type = AZF_CODEC_PLAYBACK; 1851 codec_type <= AZF_CODEC_I2S_OUT; 1852 ++codec_type, ++codec) { 1853 1854 /* skip codec if there's no interrupt for it */ 1855 if (!(status & (1 << codec_type))) 1856 continue; 1857 1858 scoped_guard(spinlock, codec->lock) { 1859 which = snd_azf3328_codec_inb(codec, IDX_IO_CODEC_IRQTYPE); 1860 /* ack all IRQ types immediately */ 1861 snd_azf3328_codec_outb(codec, IDX_IO_CODEC_IRQTYPE, which); 1862 } 1863 1864 if (codec->substream) { 1865 snd_pcm_period_elapsed(codec->substream); 1866 dev_dbg(chip->card->dev, "%s period done (#%x), @ %x\n", 1867 codec->name, 1868 which, 1869 snd_azf3328_codec_inl( 1870 codec, IDX_IO_CODEC_DMA_CURRPOS)); 1871 } else 1872 dev_warn(chip->card->dev, "irq handler problem!\n"); 1873 if (which & IRQ_SOMETHING) 1874 snd_azf3328_irq_log_unknown_type(chip, which); 1875 } 1876} 1877 1878static irqreturn_t 1879snd_azf3328_interrupt(int irq, void *dev_id) 1880{ 1881 struct snd_azf3328 *chip = dev_id; 1882 u8 status; 1883 static unsigned long irq_count; 1884 1885 status = snd_azf3328_ctrl_inb(chip, IDX_IO_IRQSTATUS); 1886 1887 /* fast path out, to ease interrupt sharing */ 1888 if (!(status & 1889 (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT 1890 |IRQ_GAMEPORT|IRQ_MPU401|IRQ_TIMER) 1891 )) 1892 return IRQ_NONE; /* must be interrupt for another device */ 1893 1894 dev_dbg(chip->card->dev, 1895 "irq_count %ld! IDX_IO_IRQSTATUS %04x\n", 1896 irq_count++ /* debug-only */, 1897 status); 1898 1899 if (status & IRQ_TIMER) { 1900 /* dev_dbg(chip->card->dev, "timer %ld\n", 1901 snd_azf3328_codec_inl(chip, IDX_IO_TIMER_VALUE) 1902 & TIMER_VALUE_MASK 1903 ); */ 1904 if (chip->timer) 1905 snd_timer_interrupt(chip->timer, chip->timer->sticks); 1906 /* ACK timer */ 1907 scoped_guard(spinlock, &chip->reg_lock) { 1908 snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x07); 1909 } 1910 dev_dbg(chip->card->dev, "timer IRQ\n"); 1911 } 1912 1913 if (status & (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT)) 1914 snd_azf3328_pcm_interrupt(chip, chip->codecs, status); 1915 1916 if (status & IRQ_GAMEPORT) 1917 snd_azf3328_gameport_interrupt(chip); 1918 1919 /* MPU401 has less critical IRQ requirements 1920 * than timer and playback/recording, right? */ 1921 if (status & IRQ_MPU401) { 1922 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data); 1923 1924 /* hmm, do we have to ack the IRQ here somehow? 1925 * If so, then I don't know how yet... */ 1926 dev_dbg(chip->card->dev, "MPU401 IRQ\n"); 1927 } 1928 return IRQ_HANDLED; 1929} 1930 1931/*****************************************************************/ 1932 1933/* as long as we think we have identical snd_pcm_hardware parameters 1934 for playback, capture and i2s out, we can use the same physical struct 1935 since the struct is simply being copied into a member. 1936*/ 1937static const struct snd_pcm_hardware snd_azf3328_hardware = 1938{ 1939 /* FIXME!! Correct? */ 1940 .info = SNDRV_PCM_INFO_MMAP | 1941 SNDRV_PCM_INFO_INTERLEAVED | 1942 SNDRV_PCM_INFO_MMAP_VALID, 1943 .formats = SNDRV_PCM_FMTBIT_S8 | 1944 SNDRV_PCM_FMTBIT_U8 | 1945 SNDRV_PCM_FMTBIT_S16_LE | 1946 SNDRV_PCM_FMTBIT_U16_LE, 1947 .rates = SNDRV_PCM_RATE_5512 | 1948 SNDRV_PCM_RATE_8000_48000 | 1949 SNDRV_PCM_RATE_KNOT, 1950 .rate_min = AZF_FREQ_4000, 1951 .rate_max = AZF_FREQ_66200, 1952 .channels_min = 1, 1953 .channels_max = 2, 1954 .buffer_bytes_max = (64*1024), 1955 .period_bytes_min = 1024, 1956 .period_bytes_max = (32*1024), 1957 /* We simply have two DMA areas (instead of a list of descriptors 1958 such as other cards); I believe that this is a fixed hardware 1959 attribute and there isn't much driver magic to be done to expand it. 1960 Thus indicate that we have at least and at most 2 periods. */ 1961 .periods_min = 2, 1962 .periods_max = 2, 1963 /* FIXME: maybe that card actually has a FIFO? 1964 * Hmm, it seems newer revisions do have one, but we still don't know 1965 * its size... */ 1966 .fifo_size = 0, 1967}; 1968 1969 1970static const unsigned int snd_azf3328_fixed_rates[] = { 1971 AZF_FREQ_4000, 1972 AZF_FREQ_4800, 1973 AZF_FREQ_5512, 1974 AZF_FREQ_6620, 1975 AZF_FREQ_8000, 1976 AZF_FREQ_9600, 1977 AZF_FREQ_11025, 1978 AZF_FREQ_13240, 1979 AZF_FREQ_16000, 1980 AZF_FREQ_22050, 1981 AZF_FREQ_32000, 1982 AZF_FREQ_44100, 1983 AZF_FREQ_48000, 1984 AZF_FREQ_66200 1985}; 1986 1987static const struct snd_pcm_hw_constraint_list snd_azf3328_hw_constraints_rates = { 1988 .count = ARRAY_SIZE(snd_azf3328_fixed_rates), 1989 .list = snd_azf3328_fixed_rates, 1990 .mask = 0, 1991}; 1992 1993/*****************************************************************/ 1994 1995static int 1996snd_azf3328_pcm_open(struct snd_pcm_substream *substream, 1997 enum snd_azf3328_codec_type codec_type 1998) 1999{ 2000 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream); 2001 struct snd_pcm_runtime *runtime = substream->runtime; 2002 struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type]; 2003 2004 codec->substream = substream; 2005 2006 /* same parameters for all our codecs - at least we think so... */ 2007 runtime->hw = snd_azf3328_hardware; 2008 2009 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 2010 &snd_azf3328_hw_constraints_rates); 2011 runtime->private_data = codec; 2012 return 0; 2013} 2014 2015static int 2016snd_azf3328_pcm_playback_open(struct snd_pcm_substream *substream) 2017{ 2018 return snd_azf3328_pcm_open(substream, AZF_CODEC_PLAYBACK); 2019} 2020 2021static int 2022snd_azf3328_pcm_capture_open(struct snd_pcm_substream *substream) 2023{ 2024 return snd_azf3328_pcm_open(substream, AZF_CODEC_CAPTURE); 2025} 2026 2027static int 2028snd_azf3328_pcm_i2s_out_open(struct snd_pcm_substream *substream) 2029{ 2030 return snd_azf3328_pcm_open(substream, AZF_CODEC_I2S_OUT); 2031} 2032 2033static int 2034snd_azf3328_pcm_close(struct snd_pcm_substream *substream 2035) 2036{ 2037 struct snd_azf3328_codec_data *codec = 2038 substream->runtime->private_data; 2039 2040 codec->substream = NULL; 2041 return 0; 2042} 2043 2044/******************************************************************/ 2045 2046static const struct snd_pcm_ops snd_azf3328_playback_ops = { 2047 .open = snd_azf3328_pcm_playback_open, 2048 .close = snd_azf3328_pcm_close, 2049 .prepare = snd_azf3328_pcm_prepare, 2050 .trigger = snd_azf3328_pcm_trigger, 2051 .pointer = snd_azf3328_pcm_pointer 2052}; 2053 2054static const struct snd_pcm_ops snd_azf3328_capture_ops = { 2055 .open = snd_azf3328_pcm_capture_open, 2056 .close = snd_azf3328_pcm_close, 2057 .prepare = snd_azf3328_pcm_prepare, 2058 .trigger = snd_azf3328_pcm_trigger, 2059 .pointer = snd_azf3328_pcm_pointer 2060}; 2061 2062static const struct snd_pcm_ops snd_azf3328_i2s_out_ops = { 2063 .open = snd_azf3328_pcm_i2s_out_open, 2064 .close = snd_azf3328_pcm_close, 2065 .prepare = snd_azf3328_pcm_prepare, 2066 .trigger = snd_azf3328_pcm_trigger, 2067 .pointer = snd_azf3328_pcm_pointer 2068}; 2069 2070static int 2071snd_azf3328_pcm(struct snd_azf3328 *chip) 2072{ 2073 /* pcm devices */ 2074 enum { AZF_PCMDEV_STD, AZF_PCMDEV_I2S_OUT, NUM_AZF_PCMDEVS }; 2075 2076 struct snd_pcm *pcm; 2077 int err; 2078 2079 err = snd_pcm_new(chip->card, "AZF3328 DSP", AZF_PCMDEV_STD, 2080 1, 1, &pcm); 2081 if (err < 0) 2082 return err; 2083 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 2084 &snd_azf3328_playback_ops); 2085 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, 2086 &snd_azf3328_capture_ops); 2087 2088 pcm->private_data = chip; 2089 pcm->info_flags = 0; 2090 strscpy(pcm->name, chip->card->shortname); 2091 /* same pcm object for playback/capture (see snd_pcm_new() above) */ 2092 chip->pcm[AZF_CODEC_PLAYBACK] = pcm; 2093 chip->pcm[AZF_CODEC_CAPTURE] = pcm; 2094 2095 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, 2096 64*1024, 64*1024); 2097 2098 err = snd_pcm_new(chip->card, "AZF3328 I2S OUT", AZF_PCMDEV_I2S_OUT, 2099 1, 0, &pcm); 2100 if (err < 0) 2101 return err; 2102 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 2103 &snd_azf3328_i2s_out_ops); 2104 2105 pcm->private_data = chip; 2106 pcm->info_flags = 0; 2107 strscpy(pcm->name, chip->card->shortname); 2108 chip->pcm[AZF_CODEC_I2S_OUT] = pcm; 2109 2110 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, 2111 64*1024, 64*1024); 2112 2113 return 0; 2114} 2115 2116/******************************************************************/ 2117 2118/*** NOTE: the physical timer resolution actually is 1024000 ticks per second 2119 *** (probably derived from main crystal via a divider of 24), 2120 *** but announcing those attributes to user-space would make programs 2121 *** configure the timer to a 1 tick value, resulting in an absolutely fatal 2122 *** timer IRQ storm. 2123 *** Thus I chose to announce a down-scaled virtual timer to the outside and 2124 *** calculate real timer countdown values internally. 2125 *** (the scale factor can be set via module parameter "seqtimer_scaling"). 2126 ***/ 2127 2128static int 2129snd_azf3328_timer_start(struct snd_timer *timer) 2130{ 2131 struct snd_azf3328 *chip; 2132 unsigned int delay; 2133 2134 chip = snd_timer_chip(timer); 2135 delay = ((timer->sticks * seqtimer_scaling) - 1) & TIMER_VALUE_MASK; 2136 if (delay < 49) { 2137 /* uhoh, that's not good, since user-space won't know about 2138 * this timing tweak 2139 * (we need to do it to avoid a lockup, though) */ 2140 2141 dev_dbg(chip->card->dev, "delay was too low (%d)!\n", delay); 2142 delay = 49; /* minimum time is 49 ticks */ 2143 } 2144 dev_dbg(chip->card->dev, "setting timer countdown value %d\n", delay); 2145 delay |= TIMER_COUNTDOWN_ENABLE | TIMER_IRQ_ENABLE; 2146 guard(spinlock_irqsave)(&chip->reg_lock); 2147 snd_azf3328_ctrl_outl(chip, IDX_IO_TIMER_VALUE, delay); 2148 return 0; 2149} 2150 2151static int 2152snd_azf3328_timer_stop(struct snd_timer *timer) 2153{ 2154 struct snd_azf3328 *chip; 2155 2156 chip = snd_timer_chip(timer); 2157 guard(spinlock_irqsave)(&chip->reg_lock); 2158 /* disable timer countdown and interrupt */ 2159 /* Hmm, should we write TIMER_IRQ_ACK here? 2160 YES indeed, otherwise a rogue timer operation - which prompts 2161 ALSA(?) to call repeated stop() in vain, but NOT start() - 2162 will never end (value 0x03 is kept shown in control byte). 2163 Simply manually poking 0x04 _once_ immediately successfully stops 2164 the hardware/ALSA interrupt activity. */ 2165 snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x04); 2166 return 0; 2167} 2168 2169 2170static int 2171snd_azf3328_timer_precise_resolution(struct snd_timer *timer, 2172 unsigned long *num, unsigned long *den) 2173{ 2174 *num = 1; 2175 *den = 1024000 / seqtimer_scaling; 2176 return 0; 2177} 2178 2179static struct snd_timer_hardware snd_azf3328_timer_hw = { 2180 .flags = SNDRV_TIMER_HW_AUTO, 2181 .resolution = 977, /* 1000000/1024000 = 0.9765625us */ 2182 .ticks = 1024000, /* max tick count, defined by the value register; actually it's not 1024000, but 1048576, but we don't care */ 2183 .start = snd_azf3328_timer_start, 2184 .stop = snd_azf3328_timer_stop, 2185 .precise_resolution = snd_azf3328_timer_precise_resolution, 2186}; 2187 2188static int 2189snd_azf3328_timer(struct snd_azf3328 *chip, int device) 2190{ 2191 struct snd_timer *timer = NULL; 2192 struct snd_timer_id tid; 2193 int err; 2194 2195 tid.dev_class = SNDRV_TIMER_CLASS_CARD; 2196 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE; 2197 tid.card = chip->card->number; 2198 tid.device = device; 2199 tid.subdevice = 0; 2200 2201 snd_azf3328_timer_hw.resolution *= seqtimer_scaling; 2202 snd_azf3328_timer_hw.ticks /= seqtimer_scaling; 2203 2204 err = snd_timer_new(chip->card, "AZF3328", &tid, &timer); 2205 if (err < 0) 2206 goto out; 2207 2208 strscpy(timer->name, "AZF3328 timer"); 2209 timer->private_data = chip; 2210 timer->hw = snd_azf3328_timer_hw; 2211 2212 chip->timer = timer; 2213 2214 snd_azf3328_timer_stop(timer); 2215 2216 err = 0; 2217 2218out: 2219 return err; 2220} 2221 2222/******************************************************************/ 2223 2224static void 2225snd_azf3328_free(struct snd_card *card) 2226{ 2227 struct snd_azf3328 *chip = card->private_data; 2228 2229 snd_azf3328_mixer_reset(chip); 2230 2231 snd_azf3328_timer_stop(chip->timer); 2232 snd_azf3328_gameport_free(chip); 2233} 2234 2235#if 0 2236/* check whether a bit can be modified */ 2237static void 2238snd_azf3328_test_bit(unsigned unsigned reg, int bit) 2239{ 2240 unsigned char val, valoff, valon; 2241 2242 val = inb(reg); 2243 2244 outb(val & ~(1 << bit), reg); 2245 valoff = inb(reg); 2246 2247 outb(val|(1 << bit), reg); 2248 valon = inb(reg); 2249 2250 outb(val, reg); 2251 2252 printk(KERN_DEBUG "reg %04x bit %d: %02x %02x %02x\n", 2253 reg, bit, val, valoff, valon 2254 ); 2255} 2256#endif 2257 2258static inline void 2259snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip) 2260{ 2261 u16 tmp; 2262 2263 dev_dbg(chip->card->dev, 2264 "ctrl_io 0x%lx, game_io 0x%lx, mpu_io 0x%lx, " 2265 "opl3_io 0x%lx, mixer_io 0x%lx, irq %d\n", 2266 chip->ctrl_io, chip->game_io, chip->mpu_io, 2267 chip->opl3_io, chip->mixer_io, chip->irq); 2268 2269 dev_dbg(chip->card->dev, 2270 "game %02x %02x %02x %02x %02x %02x\n", 2271 snd_azf3328_game_inb(chip, 0), 2272 snd_azf3328_game_inb(chip, 1), 2273 snd_azf3328_game_inb(chip, 2), 2274 snd_azf3328_game_inb(chip, 3), 2275 snd_azf3328_game_inb(chip, 4), 2276 snd_azf3328_game_inb(chip, 5)); 2277 2278 for (tmp = 0; tmp < 0x07; tmp += 1) 2279 dev_dbg(chip->card->dev, 2280 "mpu_io 0x%04x\n", inb(chip->mpu_io + tmp)); 2281 2282 for (tmp = 0; tmp <= 0x07; tmp += 1) 2283 dev_dbg(chip->card->dev, 2284 "0x%02x: game200 0x%04x, game208 0x%04x\n", 2285 tmp, inb(0x200 + tmp), inb(0x208 + tmp)); 2286 2287 for (tmp = 0; tmp <= 0x01; tmp += 1) 2288 dev_dbg(chip->card->dev, 2289 "0x%02x: mpu300 0x%04x, mpu310 0x%04x, mpu320 0x%04x, " 2290 "mpu330 0x%04x opl388 0x%04x opl38c 0x%04x\n", 2291 tmp, 2292 inb(0x300 + tmp), 2293 inb(0x310 + tmp), 2294 inb(0x320 + tmp), 2295 inb(0x330 + tmp), 2296 inb(0x388 + tmp), 2297 inb(0x38c + tmp)); 2298 2299 for (tmp = 0; tmp < AZF_IO_SIZE_CTRL; tmp += 2) 2300 dev_dbg(chip->card->dev, 2301 "ctrl 0x%02x: 0x%04x\n", 2302 tmp, snd_azf3328_ctrl_inw(chip, tmp)); 2303 2304 for (tmp = 0; tmp < AZF_IO_SIZE_MIXER; tmp += 2) 2305 dev_dbg(chip->card->dev, 2306 "mixer 0x%02x: 0x%04x\n", 2307 tmp, snd_azf3328_mixer_inw(chip, tmp)); 2308} 2309 2310static int 2311snd_azf3328_create(struct snd_card *card, 2312 struct pci_dev *pci, 2313 unsigned long device_type) 2314{ 2315 struct snd_azf3328 *chip = card->private_data; 2316 int err; 2317 u8 dma_init; 2318 enum snd_azf3328_codec_type codec_type; 2319 struct snd_azf3328_codec_data *codec_setup; 2320 2321 err = pcim_enable_device(pci); 2322 if (err < 0) 2323 return err; 2324 2325 spin_lock_init(&chip->reg_lock); 2326 chip->card = card; 2327 chip->pci = pci; 2328 chip->irq = -1; 2329 2330 /* check if we can restrict PCI DMA transfers to 24 bits */ 2331 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(24))) { 2332 dev_err(card->dev, 2333 "architecture does not support 24bit PCI busmaster DMA\n" 2334 ); 2335 return -ENXIO; 2336 } 2337 2338 err = pcim_request_all_regions(pci, "Aztech AZF3328"); 2339 if (err < 0) 2340 return err; 2341 2342 chip->ctrl_io = pci_resource_start(pci, 0); 2343 chip->game_io = pci_resource_start(pci, 1); 2344 chip->mpu_io = pci_resource_start(pci, 2); 2345 chip->opl3_io = pci_resource_start(pci, 3); 2346 chip->mixer_io = pci_resource_start(pci, 4); 2347 2348 codec_setup = &chip->codecs[AZF_CODEC_PLAYBACK]; 2349 codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_PLAYBACK; 2350 codec_setup->lock = &chip->reg_lock; 2351 codec_setup->type = AZF_CODEC_PLAYBACK; 2352 codec_setup->name = "PLAYBACK"; 2353 2354 codec_setup = &chip->codecs[AZF_CODEC_CAPTURE]; 2355 codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_CAPTURE; 2356 codec_setup->lock = &chip->reg_lock; 2357 codec_setup->type = AZF_CODEC_CAPTURE; 2358 codec_setup->name = "CAPTURE"; 2359 2360 codec_setup = &chip->codecs[AZF_CODEC_I2S_OUT]; 2361 codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_I2S_OUT; 2362 codec_setup->lock = &chip->reg_lock; 2363 codec_setup->type = AZF_CODEC_I2S_OUT; 2364 codec_setup->name = "I2S_OUT"; 2365 2366 if (devm_request_irq(&pci->dev, pci->irq, snd_azf3328_interrupt, 2367 IRQF_SHARED, KBUILD_MODNAME, chip)) { 2368 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); 2369 return -EBUSY; 2370 } 2371 chip->irq = pci->irq; 2372 card->sync_irq = chip->irq; 2373 card->private_free = snd_azf3328_free; 2374 pci_set_master(pci); 2375 2376 snd_azf3328_debug_show_ports(chip); 2377 2378 /* create mixer interface & switches */ 2379 err = snd_azf3328_mixer_new(chip); 2380 if (err < 0) 2381 return err; 2382 2383 /* standard codec init stuff */ 2384 /* default DMA init value */ 2385 dma_init = DMA_RUN_SOMETHING2|DMA_EPILOGUE_SOMETHING|DMA_SOMETHING_ELSE; 2386 2387 for (codec_type = AZF_CODEC_PLAYBACK; 2388 codec_type <= AZF_CODEC_I2S_OUT; ++codec_type) { 2389 struct snd_azf3328_codec_data *codec = 2390 &chip->codecs[codec_type]; 2391 2392 /* shutdown codecs to reduce power / noise */ 2393 /* have ...ctrl_codec_activity() act properly */ 2394 codec->running = true; 2395 snd_azf3328_ctrl_codec_activity(chip, codec_type, 0); 2396 2397 guard(spinlock_irq)(codec->lock); 2398 snd_azf3328_codec_outb(codec, IDX_IO_CODEC_DMA_FLAGS, 2399 dma_init); 2400 } 2401 2402 return 0; 2403} 2404 2405static int 2406__snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 2407{ 2408 static int dev; 2409 struct snd_card *card; 2410 struct snd_azf3328 *chip; 2411 struct snd_opl3 *opl3; 2412 int err; 2413 2414 if (dev >= SNDRV_CARDS) 2415 return -ENODEV; 2416 if (!enable[dev]) { 2417 dev++; 2418 return -ENOENT; 2419 } 2420 2421 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2422 sizeof(*chip), &card); 2423 if (err < 0) 2424 return err; 2425 chip = card->private_data; 2426 2427 strscpy(card->driver, "AZF3328"); 2428 strscpy(card->shortname, "Aztech AZF3328 (PCI168)"); 2429 2430 err = snd_azf3328_create(card, pci, pci_id->driver_data); 2431 if (err < 0) 2432 return err; 2433 2434 /* chose to use MPU401_HW_AZT2320 ID instead of MPU401_HW_MPU401, 2435 since our hardware ought to be similar, thus use same ID. */ 2436 err = snd_mpu401_uart_new( 2437 card, 0, 2438 MPU401_HW_AZT2320, chip->mpu_io, 2439 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK, 2440 -1, &chip->rmidi 2441 ); 2442 if (err < 0) { 2443 dev_err(card->dev, "no MPU-401 device at 0x%lx?\n", 2444 chip->mpu_io 2445 ); 2446 return err; 2447 } 2448 2449 err = snd_azf3328_timer(chip, 0); 2450 if (err < 0) 2451 return err; 2452 2453 err = snd_azf3328_pcm(chip); 2454 if (err < 0) 2455 return err; 2456 2457 if (snd_opl3_create(card, chip->opl3_io, chip->opl3_io+2, 2458 OPL3_HW_AUTO, 1, &opl3) < 0) { 2459 dev_err(card->dev, "no OPL3 device at 0x%lx-0x%lx?\n", 2460 chip->opl3_io, chip->opl3_io+2 2461 ); 2462 } else { 2463 /* need to use IDs 1, 2 since ID 0 is snd_azf3328_timer above */ 2464 err = snd_opl3_timer_new(opl3, 1, 2); 2465 if (err < 0) 2466 return err; 2467 err = snd_opl3_hwdep_new(opl3, 0, 1, NULL); 2468 if (err < 0) 2469 return err; 2470 opl3->private_data = chip; 2471 } 2472 2473 sprintf(card->longname, "%s at 0x%lx, irq %i", 2474 card->shortname, chip->ctrl_io, chip->irq); 2475 2476 err = snd_card_register(card); 2477 if (err < 0) 2478 return err; 2479 2480#ifdef MODULE 2481 dev_info(card->dev, 2482 "Sound driver for Aztech AZF3328-based soundcards such as PCI168.\n"); 2483 dev_info(card->dev, 2484 "Hardware was completely undocumented, unfortunately.\n"); 2485 dev_info(card->dev, 2486 "Feel free to contact andi AT lisas.de for bug reports etc.!\n"); 2487 dev_info(card->dev, 2488 "User-scalable sequencer timer set to %dHz (1024000Hz / %d).\n", 2489 1024000 / seqtimer_scaling, seqtimer_scaling); 2490#endif 2491 2492 snd_azf3328_gameport(chip, dev); 2493 2494 pci_set_drvdata(pci, card); 2495 dev++; 2496 return 0; 2497} 2498 2499static int 2500snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 2501{ 2502 return snd_card_free_on_error(&pci->dev, __snd_azf3328_probe(pci, pci_id)); 2503} 2504 2505static inline void 2506snd_azf3328_suspend_regs(const struct snd_azf3328 *chip, 2507 unsigned long io_addr, unsigned count, u32 *saved_regs) 2508{ 2509 unsigned reg; 2510 2511 for (reg = 0; reg < count; ++reg) { 2512 *saved_regs = inl(io_addr); 2513 dev_dbg(chip->card->dev, "suspend: io 0x%04lx: 0x%08x\n", 2514 io_addr, *saved_regs); 2515 ++saved_regs; 2516 io_addr += sizeof(*saved_regs); 2517 } 2518} 2519 2520static inline void 2521snd_azf3328_resume_regs(const struct snd_azf3328 *chip, 2522 const u32 *saved_regs, 2523 unsigned long io_addr, 2524 unsigned count 2525) 2526{ 2527 unsigned reg; 2528 2529 for (reg = 0; reg < count; ++reg) { 2530 outl(*saved_regs, io_addr); 2531 dev_dbg(chip->card->dev, 2532 "resume: io 0x%04lx: 0x%08x --> 0x%08x\n", 2533 io_addr, *saved_regs, inl(io_addr)); 2534 ++saved_regs; 2535 io_addr += sizeof(*saved_regs); 2536 } 2537} 2538 2539static inline void 2540snd_azf3328_suspend_ac97(struct snd_azf3328 *chip) 2541{ 2542#ifdef AZF_USE_AC97_LAYER 2543 snd_ac97_suspend(chip->ac97); 2544#else 2545 snd_azf3328_suspend_regs(chip, chip->mixer_io, 2546 ARRAY_SIZE(chip->saved_regs_mixer), chip->saved_regs_mixer); 2547 2548 /* make sure to disable master volume etc. to prevent looping sound */ 2549 snd_azf3328_mixer_mute_control_master(chip, 1); 2550 snd_azf3328_mixer_mute_control_pcm(chip, 1); 2551#endif /* AZF_USE_AC97_LAYER */ 2552} 2553 2554static inline void 2555snd_azf3328_resume_ac97(const struct snd_azf3328 *chip) 2556{ 2557#ifdef AZF_USE_AC97_LAYER 2558 snd_ac97_resume(chip->ac97); 2559#else 2560 snd_azf3328_resume_regs(chip, chip->saved_regs_mixer, chip->mixer_io, 2561 ARRAY_SIZE(chip->saved_regs_mixer)); 2562 2563 /* unfortunately with 32bit transfers, IDX_MIXER_PLAY_MASTER (0x02) 2564 and IDX_MIXER_RESET (offset 0x00) get touched at the same time, 2565 resulting in a mixer reset condition persisting until _after_ 2566 master vol was restored. Thus master vol needs an extra restore. */ 2567 outw(((u16 *)chip->saved_regs_mixer)[1], chip->mixer_io + 2); 2568#endif /* AZF_USE_AC97_LAYER */ 2569} 2570 2571static int 2572snd_azf3328_suspend(struct device *dev) 2573{ 2574 struct snd_card *card = dev_get_drvdata(dev); 2575 struct snd_azf3328 *chip = card->private_data; 2576 u16 *saved_regs_ctrl_u16; 2577 2578 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2579 2580 snd_azf3328_suspend_ac97(chip); 2581 2582 snd_azf3328_suspend_regs(chip, chip->ctrl_io, 2583 ARRAY_SIZE(chip->saved_regs_ctrl), chip->saved_regs_ctrl); 2584 2585 /* manually store the one currently relevant write-only reg, too */ 2586 saved_regs_ctrl_u16 = (u16 *)chip->saved_regs_ctrl; 2587 saved_regs_ctrl_u16[IDX_IO_6AH / 2] = chip->shadow_reg_ctrl_6AH; 2588 2589 snd_azf3328_suspend_regs(chip, chip->game_io, 2590 ARRAY_SIZE(chip->saved_regs_game), chip->saved_regs_game); 2591 snd_azf3328_suspend_regs(chip, chip->mpu_io, 2592 ARRAY_SIZE(chip->saved_regs_mpu), chip->saved_regs_mpu); 2593 snd_azf3328_suspend_regs(chip, chip->opl3_io, 2594 ARRAY_SIZE(chip->saved_regs_opl3), chip->saved_regs_opl3); 2595 return 0; 2596} 2597 2598static int 2599snd_azf3328_resume(struct device *dev) 2600{ 2601 struct snd_card *card = dev_get_drvdata(dev); 2602 const struct snd_azf3328 *chip = card->private_data; 2603 2604 snd_azf3328_resume_regs(chip, chip->saved_regs_game, chip->game_io, 2605 ARRAY_SIZE(chip->saved_regs_game)); 2606 snd_azf3328_resume_regs(chip, chip->saved_regs_mpu, chip->mpu_io, 2607 ARRAY_SIZE(chip->saved_regs_mpu)); 2608 snd_azf3328_resume_regs(chip, chip->saved_regs_opl3, chip->opl3_io, 2609 ARRAY_SIZE(chip->saved_regs_opl3)); 2610 2611 snd_azf3328_resume_ac97(chip); 2612 2613 snd_azf3328_resume_regs(chip, chip->saved_regs_ctrl, chip->ctrl_io, 2614 ARRAY_SIZE(chip->saved_regs_ctrl)); 2615 2616 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2617 return 0; 2618} 2619 2620static DEFINE_SIMPLE_DEV_PM_OPS(snd_azf3328_pm, snd_azf3328_suspend, snd_azf3328_resume); 2621 2622static struct pci_driver azf3328_driver = { 2623 .name = KBUILD_MODNAME, 2624 .id_table = snd_azf3328_ids, 2625 .probe = snd_azf3328_probe, 2626 .driver = { 2627 .pm = &snd_azf3328_pm, 2628 }, 2629}; 2630 2631module_pci_driver(azf3328_driver);
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