tegra.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 *
  4 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
  5 */
  6
  7#include <linux/clk.h>
  8#include <linux/clocksource.h>
  9#include <linux/completion.h>
 10#include <linux/delay.h>
 11#include <linux/dma-mapping.h>
 12#include <linux/init.h>
 13#include <linux/interrupt.h>
 14#include <linux/io.h>
 15#include <linux/kernel.h>
 16#include <linux/module.h>
 17#include <linux/moduleparam.h>
 18#include <linux/mutex.h>
 19#include <linux/of.h>
 20#include <linux/platform_device.h>
 21#include <linux/reset.h>
 22#include <linux/slab.h>
 23#include <linux/time.h>
 24#include <linux/string.h>
 25#include <linux/pm_runtime.h>
 26
 27#include <sound/core.h>
 28#include <sound/initval.h>
 29
 30#include <sound/hda_codec.h>
 31#include "hda_controller.h"
 32
 33/* Defines for Nvidia Tegra HDA support */
 34#define HDA_BAR0           0x8000
 35
 36#define HDA_CFG_CMD        0x1004
 37#define HDA_CFG_BAR0       0x1010
 38
 39#define HDA_ENABLE_IO_SPACE       (1 << 0)
 40#define HDA_ENABLE_MEM_SPACE      (1 << 1)
 41#define HDA_ENABLE_BUS_MASTER     (1 << 2)
 42#define HDA_ENABLE_SERR           (1 << 8)
 43#define HDA_DISABLE_INTR          (1 << 10)
 44#define HDA_BAR0_INIT_PROGRAM     0xFFFFFFFF
 45#define HDA_BAR0_FINAL_PROGRAM    (1 << 14)
 46
 47/* IPFS */
 48#define HDA_IPFS_CONFIG           0x180
 49#define HDA_IPFS_EN_FPCI          0x1
 50
 51#define HDA_IPFS_FPCI_BAR0        0x80
 52#define HDA_FPCI_BAR0_START       0x40
 53
 54#define HDA_IPFS_INTR_MASK        0x188
 55#define HDA_IPFS_EN_INTR          (1 << 16)
 56
 57/* FPCI */
 58#define FPCI_DBG_CFG_2		  0x10F4
 59#define FPCI_GCAP_NSDO_SHIFT	  18
 60#define FPCI_GCAP_NSDO_MASK	  (0x3 << FPCI_GCAP_NSDO_SHIFT)
 61
 62/* max number of SDs */
 63#define NUM_CAPTURE_SD 1
 64#define NUM_PLAYBACK_SD 1
 65
 66/*
 67 * Tegra194 does not reflect correct number of SDO lines. Below macro
 68 * is used to update the GCAP register to workaround the issue.
 69 */
 70#define TEGRA194_NUM_SDO_LINES	  4
 71
 72struct hda_tegra_soc {
 73	bool has_hda2codec_2x_reset;
 74	bool has_hda2hdmi;
 75	bool has_hda2codec_2x;
 76	bool input_stream;
 77	bool always_on;
 78	bool requires_init;
 79};
 80
 81struct hda_tegra {
 82	struct azx chip;
 83	struct device *dev;
 84	struct reset_control_bulk_data resets[3];
 85	struct clk_bulk_data clocks[3];
 86	unsigned int nresets;
 87	unsigned int nclocks;
 88	void __iomem *regs;
 89	struct work_struct probe_work;
 90	const struct hda_tegra_soc *soc;
 91};
 92
 93#ifdef CONFIG_PM
 94static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 95module_param(power_save, bint, 0644);
 96MODULE_PARM_DESC(power_save,
 97		 "Automatic power-saving timeout (in seconds, 0 = disable).");
 98#else
 99#define power_save	0
100#endif
101
102static const struct hda_controller_ops hda_tegra_ops; /* nothing special */
103
104static void hda_tegra_init(struct hda_tegra *hda)
105{
106	u32 v;
107
108	/* Enable PCI access */
109	v = readl(hda->regs + HDA_IPFS_CONFIG);
110	v |= HDA_IPFS_EN_FPCI;
111	writel(v, hda->regs + HDA_IPFS_CONFIG);
112
113	/* Enable MEM/IO space and bus master */
114	v = readl(hda->regs + HDA_CFG_CMD);
115	v &= ~HDA_DISABLE_INTR;
116	v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
117		HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
118	writel(v, hda->regs + HDA_CFG_CMD);
119
120	writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
121	writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
122	writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
123
124	v = readl(hda->regs + HDA_IPFS_INTR_MASK);
125	v |= HDA_IPFS_EN_INTR;
126	writel(v, hda->regs + HDA_IPFS_INTR_MASK);
127}
128
129/*
130 * power management
131 */
132static int hda_tegra_suspend(struct device *dev)
133{
134	struct snd_card *card = dev_get_drvdata(dev);
135	int rc;
136
137	rc = pm_runtime_force_suspend(dev);
138	if (rc < 0)
139		return rc;
140	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
141
142	return 0;
143}
144
145static int hda_tegra_resume(struct device *dev)
146{
147	struct snd_card *card = dev_get_drvdata(dev);
148	int rc;
149
150	rc = pm_runtime_force_resume(dev);
151	if (rc < 0)
152		return rc;
153	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
154
155	return 0;
156}
157
158static int hda_tegra_runtime_suspend(struct device *dev)
159{
160	struct snd_card *card = dev_get_drvdata(dev);
161	struct azx *chip = card->private_data;
162	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
163
164	if (chip && chip->running) {
165		/* enable controller wake up event */
166		azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
167			   STATESTS_INT_MASK);
168
169		azx_stop_chip(chip);
170		azx_enter_link_reset(chip);
171	}
172	clk_bulk_disable_unprepare(hda->nclocks, hda->clocks);
173
174	return 0;
175}
176
177static int hda_tegra_runtime_resume(struct device *dev)
178{
179	struct snd_card *card = dev_get_drvdata(dev);
180	struct azx *chip = card->private_data;
181	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
182	int rc;
183
184	if (!chip->running) {
185		rc = reset_control_bulk_assert(hda->nresets, hda->resets);
186		if (rc)
187			return rc;
188	}
189
190	rc = clk_bulk_prepare_enable(hda->nclocks, hda->clocks);
191	if (rc != 0)
192		return rc;
193	if (chip->running) {
194		if (hda->soc->requires_init)
195			hda_tegra_init(hda);
196
197		azx_init_chip(chip, 1);
198		/* disable controller wake up event*/
199		azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
200			   ~STATESTS_INT_MASK);
201	} else {
202		usleep_range(10, 100);
203
204		rc = reset_control_bulk_deassert(hda->nresets, hda->resets);
205		if (rc)
206			return rc;
207	}
208
209	return 0;
210}
211
212static const struct dev_pm_ops hda_tegra_pm = {
213	SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
214	RUNTIME_PM_OPS(hda_tegra_runtime_suspend, hda_tegra_runtime_resume, NULL)
215};
216
217static int hda_tegra_dev_disconnect(struct snd_device *device)
218{
219	struct azx *chip = device->device_data;
220
221	chip->bus.shutdown = 1;
222	return 0;
223}
224
225/*
226 * destructor
227 */
228static int hda_tegra_dev_free(struct snd_device *device)
229{
230	struct azx *chip = device->device_data;
231	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
232
233	cancel_work_sync(&hda->probe_work);
234	if (azx_bus(chip)->chip_init) {
235		azx_stop_all_streams(chip);
236		azx_stop_chip(chip);
237	}
238
239	azx_free_stream_pages(chip);
240	azx_free_streams(chip);
241	snd_hdac_bus_exit(azx_bus(chip));
242
243	return 0;
244}
245
246static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
247{
248	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
249	struct hdac_bus *bus = azx_bus(chip);
250	struct resource *res;
251
252	hda->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
253	if (IS_ERR(hda->regs))
254		return PTR_ERR(hda->regs);
255
256	bus->remap_addr = hda->regs + HDA_BAR0;
257	bus->addr = res->start + HDA_BAR0;
258
259	if (hda->soc->requires_init)
260		hda_tegra_init(hda);
261
262	return 0;
263}
264
265static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
266{
267	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
268	struct hdac_bus *bus = azx_bus(chip);
269	struct snd_card *card = chip->card;
270	int err;
271	unsigned short gcap;
272	int irq_id = platform_get_irq(pdev, 0);
273	const char *sname, *drv_name = "tegra-hda";
274	struct device_node *np = pdev->dev.of_node;
275
276	if (irq_id < 0)
277		return irq_id;
278
279	err = hda_tegra_init_chip(chip, pdev);
280	if (err)
281		return err;
282
283	err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
284			     IRQF_SHARED, KBUILD_MODNAME, chip);
285	if (err) {
286		dev_err(chip->card->dev,
287			"unable to request IRQ %d, disabling device\n",
288			irq_id);
289		return err;
290	}
291	bus->irq = irq_id;
292	bus->dma_stop_delay = 100;
293	card->sync_irq = bus->irq;
294
295	/*
296	 * Tegra194 has 4 SDO lines and the STRIPE can be used to
297	 * indicate how many of the SDO lines the stream should be
298	 * striped. But GCAP register does not reflect the true
299	 * capability of HW. Below workaround helps to fix this.
300	 *
301	 * GCAP_NSDO is bits 19:18 in T_AZA_DBG_CFG_2,
302	 * 0 for 1 SDO, 1 for 2 SDO, 2 for 4 SDO lines.
303	 */
304	if (of_device_is_compatible(np, "nvidia,tegra194-hda")) {
305		u32 val;
306
307		dev_info(card->dev, "Override SDO lines to %u\n",
308			 TEGRA194_NUM_SDO_LINES);
309
310		val = readl(hda->regs + FPCI_DBG_CFG_2) & ~FPCI_GCAP_NSDO_MASK;
311		val |= (TEGRA194_NUM_SDO_LINES >> 1) << FPCI_GCAP_NSDO_SHIFT;
312		writel(val, hda->regs + FPCI_DBG_CFG_2);
313	}
314
315	gcap = azx_readw(chip, GCAP);
316	dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
317
318	chip->align_buffer_size = 1;
319
320	/* read number of streams from GCAP register instead of using
321	 * hardcoded value
322	 */
323	chip->capture_streams = (gcap >> 8) & 0x0f;
324
325	/* The GCAP register on Tegra234 implies no Input Streams(ISS) support,
326	 * but the HW output stream descriptor programming should start with
327	 * offset 0x20*4 from base stream descriptor address. This will be a
328	 * problem while calculating the offset for output stream descriptor
329	 * which will be considering input stream also. So here output stream
330	 * starts with offset 0 which is wrong as HW register for output stream
331	 * offset starts with 4.
332	 */
333	if (!hda->soc->input_stream)
334		chip->capture_streams = 4;
335
336	chip->playback_streams = (gcap >> 12) & 0x0f;
337	if (!chip->playback_streams && !chip->capture_streams) {
338		/* gcap didn't give any info, switching to old method */
339		chip->playback_streams = NUM_PLAYBACK_SD;
340		chip->capture_streams = NUM_CAPTURE_SD;
341	}
342	chip->capture_index_offset = 0;
343	chip->playback_index_offset = chip->capture_streams;
344	chip->num_streams = chip->playback_streams + chip->capture_streams;
345
346	/* initialize streams */
347	err = azx_init_streams(chip);
348	if (err < 0) {
349		dev_err(card->dev, "failed to initialize streams: %d\n", err);
350		return err;
351	}
352
353	err = azx_alloc_stream_pages(chip);
354	if (err < 0) {
355		dev_err(card->dev, "failed to allocate stream pages: %d\n",
356			err);
357		return err;
358	}
359
360	/* initialize chip */
361	azx_init_chip(chip, 1);
362
363	/*
364	 * Playback (for 44.1K/48K, 2-channel, 16-bps) fails with
365	 * 4 SDO lines due to legacy design limitation. Following
366	 * is, from HD Audio Specification (Revision 1.0a), used to
367	 * control striping of the stream across multiple SDO lines
368	 * for sample rates <= 48K.
369	 *
370	 * { ((num_channels * bits_per_sample) / number of SDOs) >= 8 }
371	 *
372	 * Due to legacy design issue it is recommended that above
373	 * ratio must be greater than 8. Since number of SDO lines is
374	 * in powers of 2, next available ratio is 16 which can be
375	 * used as a limiting factor here.
376	 */
377	if (of_device_is_compatible(np, "nvidia,tegra30-hda"))
378		chip->bus.core.sdo_limit = 16;
379
380	/* codec detection */
381	if (!bus->codec_mask) {
382		dev_err(card->dev, "no codecs found!\n");
383		return -ENODEV;
384	}
385
386	/* driver name */
387	strscpy(card->driver, drv_name);
388	/* shortname for card */
389	sname = of_get_property(np, "nvidia,model", NULL);
390	if (!sname)
391		sname = drv_name;
392	if (strlen(sname) > sizeof(card->shortname))
393		dev_info(card->dev, "truncating shortname for card\n");
394	strscpy(card->shortname, sname);
395
396	/* longname for card */
397	snprintf(card->longname, sizeof(card->longname),
398		 "%s at 0x%lx irq %i",
399		 card->shortname, bus->addr, bus->irq);
400
401	return 0;
402}
403
404/*
405 * constructor
406 */
407
408static void hda_tegra_probe_work(struct work_struct *work);
409
410static int hda_tegra_create(struct snd_card *card,
411			    unsigned int driver_caps,
412			    struct hda_tegra *hda)
413{
414	static const struct snd_device_ops ops = {
415		.dev_disconnect = hda_tegra_dev_disconnect,
416		.dev_free = hda_tegra_dev_free,
417	};
418	struct azx *chip;
419	int err;
420
421	chip = &hda->chip;
422
423	mutex_init(&chip->open_mutex);
424	chip->card = card;
425	chip->ops = &hda_tegra_ops;
426	chip->driver_caps = driver_caps;
427	chip->driver_type = driver_caps & 0xff;
428	chip->dev_index = 0;
429	INIT_LIST_HEAD(&chip->pcm_list);
430
431	chip->codec_probe_mask = -1;
432
433	chip->single_cmd = false;
434	chip->snoop = true;
435
436	INIT_WORK(&hda->probe_work, hda_tegra_probe_work);
437
438	err = azx_bus_init(chip, NULL);
439	if (err < 0)
440		return err;
441
442	chip->bus.core.sync_write = 0;
443	chip->bus.core.needs_damn_long_delay = 1;
444	chip->bus.core.aligned_mmio = 1;
445
446	/*
447	 * HDA power domain and clocks are always on for Tegra264 and
448	 * the jack detection logic would work always, so no need of
449	 * jack polling mechanism running.
450	 */
451	if (!hda->soc->always_on) {
452		chip->jackpoll_interval = msecs_to_jiffies(5000);
453		chip->bus.jackpoll_in_suspend = 1;
454	}
455
456	err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
457	if (err < 0) {
458		dev_err(card->dev, "Error creating device\n");
459		return err;
460	}
461
462	return 0;
463}
464
465static const struct hda_tegra_soc tegra30_data = {
466	.has_hda2codec_2x_reset = true,
467	.has_hda2hdmi = true,
468	.has_hda2codec_2x = true,
469	.input_stream = true,
470	.always_on = false,
471	.requires_init = true,
472};
473
474static const struct hda_tegra_soc tegra194_data = {
475	.has_hda2codec_2x_reset = false,
476	.has_hda2hdmi = true,
477	.has_hda2codec_2x = true,
478	.input_stream = true,
479	.always_on = false,
480	.requires_init = true,
481};
482
483static const struct hda_tegra_soc tegra234_data = {
484	.has_hda2codec_2x_reset = true,
485	.has_hda2hdmi = false,
486	.has_hda2codec_2x = true,
487	.input_stream = false,
488	.always_on = false,
489	.requires_init = true,
490};
491
492static const struct hda_tegra_soc tegra264_data = {
493	.has_hda2codec_2x_reset = true,
494	.has_hda2hdmi = false,
495	.has_hda2codec_2x = false,
496	.input_stream = false,
497	.always_on = true,
498	.requires_init = false,
499};
500
501static const struct of_device_id hda_tegra_match[] = {
502	{ .compatible = "nvidia,tegra30-hda", .data = &tegra30_data },
503	{ .compatible = "nvidia,tegra194-hda", .data = &tegra194_data },
504	{ .compatible = "nvidia,tegra234-hda", .data = &tegra234_data },
505	{ .compatible = "nvidia,tegra264-hda", .data = &tegra264_data },
506	{},
507};
508MODULE_DEVICE_TABLE(of, hda_tegra_match);
509
510static int hda_tegra_probe(struct platform_device *pdev)
511{
512	const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR |
513					  AZX_DCAPS_PM_RUNTIME |
514					  AZX_DCAPS_4K_BDLE_BOUNDARY;
515	struct snd_card *card;
516	struct azx *chip;
517	struct hda_tegra *hda;
518	int err;
519
520	hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
521	if (!hda)
522		return -ENOMEM;
523	hda->dev = &pdev->dev;
524	chip = &hda->chip;
525
526	hda->soc = of_device_get_match_data(&pdev->dev);
527
528	err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
529			   THIS_MODULE, 0, &card);
530	if (err < 0) {
531		dev_err(&pdev->dev, "Error creating card!\n");
532		return err;
533	}
534
535	hda->resets[hda->nresets++].id = "hda";
536
537	/*
538	 * "hda2hdmi" is not applicable for Tegra234. This is because the
539	 * codec is separate IP and not under display SOR partition now.
540	 */
541	if (hda->soc->has_hda2hdmi)
542		hda->resets[hda->nresets++].id = "hda2hdmi";
543
544	/*
545	 * "hda2codec_2x" reset is not present on Tegra194. Though DT would
546	 * be updated to reflect this, but to have backward compatibility
547	 * below is necessary.
548	 */
549	if (hda->soc->has_hda2codec_2x_reset)
550		hda->resets[hda->nresets++].id = "hda2codec_2x";
551
552	err = devm_reset_control_bulk_get_exclusive(&pdev->dev, hda->nresets,
553						    hda->resets);
554	if (err)
555		goto out_free;
556
557	hda->clocks[hda->nclocks++].id = "hda";
558	if (hda->soc->has_hda2hdmi)
559		hda->clocks[hda->nclocks++].id = "hda2hdmi";
560
561	if (hda->soc->has_hda2codec_2x)
562		hda->clocks[hda->nclocks++].id = "hda2codec_2x";
563
564	err = devm_clk_bulk_get(&pdev->dev, hda->nclocks, hda->clocks);
565	if (err < 0)
566		goto out_free;
567
568	err = hda_tegra_create(card, driver_flags, hda);
569	if (err < 0)
570		goto out_free;
571	card->private_data = chip;
572
573	dev_set_drvdata(&pdev->dev, card);
574
575	pm_runtime_enable(hda->dev);
576	if (!azx_has_pm_runtime(chip))
577		pm_runtime_forbid(hda->dev);
578
579	schedule_work(&hda->probe_work);
580
581	return 0;
582
583out_free:
584	snd_card_free(card);
585	return err;
586}
587
588static void hda_tegra_probe_work(struct work_struct *work)
589{
590	struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work);
591	struct azx *chip = &hda->chip;
592	struct platform_device *pdev = to_platform_device(hda->dev);
593	int err;
594
595	pm_runtime_get_sync(hda->dev);
596	err = hda_tegra_first_init(chip, pdev);
597	if (err < 0)
598		goto out_free;
599
600	/* create codec instances */
601	err = azx_probe_codecs(chip, 8);
602	if (err < 0)
603		goto out_free;
604
605	err = azx_codec_configure(chip);
606	if (err < 0)
607		goto out_free;
608
609	err = snd_card_register(chip->card);
610	if (err < 0)
611		goto out_free;
612
613	chip->running = 1;
614	snd_hda_set_power_save(&chip->bus, power_save * 1000);
615
616 out_free:
617	pm_runtime_put(hda->dev);
618	return; /* no error return from async probe */
619}
620
621static void hda_tegra_remove(struct platform_device *pdev)
622{
623	snd_card_free(dev_get_drvdata(&pdev->dev));
624	pm_runtime_disable(&pdev->dev);
625}
626
627static void hda_tegra_shutdown(struct platform_device *pdev)
628{
629	struct snd_card *card = dev_get_drvdata(&pdev->dev);
630	struct azx *chip;
631
632	if (!card)
633		return;
634	chip = card->private_data;
635	if (chip && chip->running)
636		azx_stop_chip(chip);
637}
638
639static struct platform_driver tegra_platform_hda = {
640	.driver = {
641		.name = "tegra-hda",
642		.pm = pm_ptr(&hda_tegra_pm),
643		.of_match_table = hda_tegra_match,
644	},
645	.probe = hda_tegra_probe,
646	.remove = hda_tegra_remove,
647	.shutdown = hda_tegra_shutdown,
648};
649module_platform_driver(tegra_platform_hda);
650
651MODULE_DESCRIPTION("Tegra HDA bus driver");
652MODULE_LICENSE("GPL v2");