controller.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 *
   4 *  Implementation of primary alsa driver code base for Intel HD Audio.
   5 *
   6 *  Copyright(c) 2004 Intel Corporation
   7 *
   8 *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9 *                     PeiSen Hou <pshou@realtek.com.tw>
  10 */
  11
  12#include <linux/clocksource.h>
  13#include <linux/delay.h>
  14#include <linux/interrupt.h>
  15#include <linux/kernel.h>
  16#include <linux/module.h>
  17#include <linux/pm_runtime.h>
  18#include <linux/slab.h>
  19
  20#ifdef CONFIG_X86
  21/* for art-tsc conversion */
  22#include <asm/tsc.h>
  23#endif
  24
  25#include <sound/core.h>
  26#include <sound/initval.h>
  27#include <sound/pcm_params.h>
  28#include "hda_controller.h"
  29#include "hda_local.h"
  30
  31#define CREATE_TRACE_POINTS
  32#include "controller_trace.h"
  33
  34/* DSP lock helpers */
  35#ifdef CONFIG_SND_HDA_DSP_LOADER
  36#define guard_dsp_lock(dev)	guard(snd_hdac_dsp_lock)(azx_stream(dev))
  37#else
  38#define guard_dsp_lock(dev)	do {} while (0)
  39#endif
  40#define dsp_is_locked(dev)	snd_hdac_stream_is_locked(azx_stream(dev))
  41
  42/* assign a stream for the PCM */
  43static inline struct azx_dev *
  44azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
  45{
  46	struct hdac_stream *s;
  47
  48	s = snd_hdac_stream_assign(azx_bus(chip), substream);
  49	if (!s)
  50		return NULL;
  51	return stream_to_azx_dev(s);
  52}
  53
  54/* release the assigned stream */
  55static inline void azx_release_device(struct azx_dev *azx_dev)
  56{
  57	snd_hdac_stream_release(azx_stream(azx_dev));
  58}
  59
  60static inline struct hda_pcm_stream *
  61to_hda_pcm_stream(struct snd_pcm_substream *substream)
  62{
  63	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
  64	return &apcm->info->stream[substream->stream];
  65}
  66
  67static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
  68				u64 nsec)
  69{
  70	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
  71	struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
  72	u64 codec_frames, codec_nsecs;
  73
  74	if (!hinfo->ops.get_delay)
  75		return nsec;
  76
  77	codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
  78	codec_nsecs = div_u64(codec_frames * 1000000000LL,
  79			      substream->runtime->rate);
  80
  81	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  82		return nsec + codec_nsecs;
  83
  84	return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
  85}
  86
  87/*
  88 * PCM ops
  89 */
  90
  91static int azx_pcm_close(struct snd_pcm_substream *substream)
  92{
  93	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
  94	struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
  95	struct azx *chip = apcm->chip;
  96	struct azx_dev *azx_dev = get_azx_dev(substream);
  97
  98	trace_azx_pcm_close(chip, azx_dev);
  99	scoped_guard(mutex, &chip->open_mutex) {
 100		azx_release_device(azx_dev);
 101		if (hinfo->ops.close)
 102			hinfo->ops.close(hinfo, apcm->codec, substream);
 103		snd_hda_power_down(apcm->codec);
 104	}
 105	snd_hda_codec_pcm_put(apcm->info);
 106	return 0;
 107}
 108
 109static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
 110			     struct snd_pcm_hw_params *hw_params)
 111{
 112	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 113	struct azx *chip = apcm->chip;
 114	struct azx_dev *azx_dev = get_azx_dev(substream);
 115	struct hdac_stream *hdas = azx_stream(azx_dev);
 116
 117	trace_azx_pcm_hw_params(chip, azx_dev);
 118	guard_dsp_lock(azx_dev);
 119	if (dsp_is_locked(azx_dev))
 120		return -EBUSY;
 121
 122	/* Set up BDLEs here, return -ENOMEM if too many BDLEs are required */
 123	hdas->bufsize = params_buffer_bytes(hw_params);
 124	hdas->period_bytes = params_period_bytes(hw_params);
 125	hdas->format_val = 0;
 126	hdas->no_period_wakeup =
 127		(hw_params->info & SNDRV_PCM_INFO_NO_PERIOD_WAKEUP) &&
 128		(hw_params->flags & SNDRV_PCM_HW_PARAMS_NO_PERIOD_WAKEUP);
 129	if (snd_hdac_stream_setup_periods(hdas) < 0)
 130		return -ENOMEM;
 131
 132	return 0;
 133}
 134
 135static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
 136{
 137	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 138	struct azx_dev *azx_dev = get_azx_dev(substream);
 139	struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 140
 141	/* reset BDL address */
 142	guard_dsp_lock(azx_dev);
 143	if (!dsp_is_locked(azx_dev))
 144		snd_hdac_stream_cleanup(azx_stream(azx_dev));
 145
 146	snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
 147
 148	azx_stream(azx_dev)->prepared = 0;
 149	return 0;
 150}
 151
 152static int azx_pcm_prepare(struct snd_pcm_substream *substream)
 153{
 154	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 155	struct azx *chip = apcm->chip;
 156	struct azx_dev *azx_dev = get_azx_dev(substream);
 157	struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 158	struct snd_pcm_runtime *runtime = substream->runtime;
 159	unsigned int format_val, stream_tag, bits;
 160	int err;
 161	struct hda_spdif_out *spdif =
 162		snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
 163	unsigned short ctls = spdif ? spdif->ctls : 0;
 164
 165	trace_azx_pcm_prepare(chip, azx_dev);
 166	guard_dsp_lock(azx_dev);
 167	if (dsp_is_locked(azx_dev))
 168		return -EBUSY;
 169
 170	snd_hdac_stream_reset(azx_stream(azx_dev));
 171	bits = snd_hdac_stream_format_bits(runtime->format, SNDRV_PCM_SUBFORMAT_STD, hinfo->maxbps);
 172
 173	format_val = snd_hdac_spdif_stream_format(runtime->channels, bits, runtime->rate, ctls);
 174	if (!format_val) {
 175		dev_err(chip->card->dev,
 176			"invalid format_val, rate=%d, ch=%d, format=%d\n",
 177			runtime->rate, runtime->channels, runtime->format);
 178		return -EINVAL;
 179	}
 180
 181	err = snd_hdac_stream_set_params(azx_stream(azx_dev), format_val);
 182	if (err < 0)
 183		return err;
 184
 185	snd_hdac_stream_setup(azx_stream(azx_dev), false);
 186
 187	stream_tag = azx_dev->core.stream_tag;
 188	/* CA-IBG chips need the playback stream starting from 1 */
 189	if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
 190	    stream_tag > chip->capture_streams)
 191		stream_tag -= chip->capture_streams;
 192	err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
 193				     azx_dev->core.format_val, substream);
 194	if (err < 0)
 195		return err;
 196
 197	azx_stream(azx_dev)->prepared = 1;
 198	return 0;
 199}
 200
 201static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 202{
 203	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 204	struct azx *chip = apcm->chip;
 205	struct hdac_bus *bus = azx_bus(chip);
 206	struct azx_dev *azx_dev;
 207	struct snd_pcm_substream *s;
 208	struct hdac_stream *hstr;
 209	bool start;
 210	int sbits = 0;
 211	int sync_reg;
 212
 213	azx_dev = get_azx_dev(substream);
 214	trace_azx_pcm_trigger(chip, azx_dev, cmd);
 215
 216	hstr = azx_stream(azx_dev);
 217	if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
 218		sync_reg = AZX_REG_OLD_SSYNC;
 219	else
 220		sync_reg = AZX_REG_SSYNC;
 221
 222	if (dsp_is_locked(azx_dev) || !hstr->prepared)
 223		return -EPIPE;
 224
 225	switch (cmd) {
 226	case SNDRV_PCM_TRIGGER_START:
 227	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 228	case SNDRV_PCM_TRIGGER_RESUME:
 229		start = true;
 230		break;
 231	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 232	case SNDRV_PCM_TRIGGER_SUSPEND:
 233	case SNDRV_PCM_TRIGGER_STOP:
 234		start = false;
 235		break;
 236	default:
 237		return -EINVAL;
 238	}
 239
 240	snd_pcm_group_for_each_entry(s, substream) {
 241		if (s->pcm->card != substream->pcm->card)
 242			continue;
 243		azx_dev = get_azx_dev(s);
 244		sbits |= 1 << azx_dev->core.index;
 245		snd_pcm_trigger_done(s, substream);
 246	}
 247
 248	scoped_guard(spinlock, &bus->reg_lock) {
 249		/* first, set SYNC bits of corresponding streams */
 250		snd_hdac_stream_sync_trigger(hstr, true, sbits, sync_reg);
 251
 252		snd_pcm_group_for_each_entry(s, substream) {
 253			if (s->pcm->card != substream->pcm->card)
 254				continue;
 255			azx_dev = get_azx_dev(s);
 256			if (start) {
 257				azx_dev->insufficient = 1;
 258				snd_hdac_stream_start(azx_stream(azx_dev));
 259			} else {
 260				snd_hdac_stream_stop(azx_stream(azx_dev));
 261			}
 262		}
 263	}
 264
 265	snd_hdac_stream_sync(hstr, start, sbits);
 266
 267	guard(spinlock)(&bus->reg_lock);
 268	/* reset SYNC bits */
 269	snd_hdac_stream_sync_trigger(hstr, false, sbits, sync_reg);
 270	snd_hdac_stream_timecounter_init(hstr, sbits, start);
 271	return 0;
 272}
 273
 274unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev)
 275{
 276	return snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 277}
 278EXPORT_SYMBOL_GPL(azx_get_pos_lpib);
 279
 280unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev)
 281{
 282	return snd_hdac_stream_get_pos_posbuf(azx_stream(azx_dev));
 283}
 284EXPORT_SYMBOL_GPL(azx_get_pos_posbuf);
 285
 286unsigned int azx_get_position(struct azx *chip,
 287			      struct azx_dev *azx_dev)
 288{
 289	struct snd_pcm_substream *substream = azx_dev->core.substream;
 290	unsigned int pos;
 291	int stream = substream->stream;
 292	int delay = 0;
 293
 294	if (chip->get_position[stream])
 295		pos = chip->get_position[stream](chip, azx_dev);
 296	else /* use the position buffer as default */
 297		pos = azx_get_pos_posbuf(chip, azx_dev);
 298
 299	if (pos >= azx_dev->core.bufsize)
 300		pos = 0;
 301
 302	if (substream->runtime) {
 303		struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 304		struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 305
 306		if (chip->get_delay[stream])
 307			delay += chip->get_delay[stream](chip, azx_dev, pos);
 308		if (hinfo->ops.get_delay)
 309			delay += hinfo->ops.get_delay(hinfo, apcm->codec,
 310						      substream);
 311		substream->runtime->delay = delay;
 312	}
 313
 314	trace_azx_get_position(chip, azx_dev, pos, delay);
 315	return pos;
 316}
 317EXPORT_SYMBOL_GPL(azx_get_position);
 318
 319static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
 320{
 321	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 322	struct azx *chip = apcm->chip;
 323	struct azx_dev *azx_dev = get_azx_dev(substream);
 324	return bytes_to_frames(substream->runtime,
 325			       azx_get_position(chip, azx_dev));
 326}
 327
 328/*
 329 * azx_scale64: Scale base by mult/div while not overflowing sanely
 330 *
 331 * Derived from scale64_check_overflow in kernel/time/timekeeping.c
 332 *
 333 * The tmestamps for a 48Khz stream can overflow after (2^64/10^9)/48K which
 334 * is about 384307 ie ~4.5 days.
 335 *
 336 * This scales the calculation so that overflow will happen but after 2^64 /
 337 * 48000 secs, which is pretty large!
 338 *
 339 * In caln below:
 340 *	base may overflow, but since there isn’t any additional division
 341 *	performed on base it’s OK
 342 *	rem can’t overflow because both are 32-bit values
 343 */
 344
 345#ifdef CONFIG_X86
 346static u64 azx_scale64(u64 base, u32 num, u32 den)
 347{
 348	u64 rem;
 349
 350	rem = do_div(base, den);
 351
 352	base *= num;
 353	rem *= num;
 354
 355	do_div(rem, den);
 356
 357	return base + rem;
 358}
 359
 360static int azx_get_sync_time(ktime_t *device,
 361		struct system_counterval_t *system, void *ctx)
 362{
 363	struct snd_pcm_substream *substream = ctx;
 364	struct azx_dev *azx_dev = get_azx_dev(substream);
 365	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 366	struct azx *chip = apcm->chip;
 367	struct snd_pcm_runtime *runtime;
 368	u64 ll_counter, ll_counter_l, ll_counter_h;
 369	u64 tsc_counter, tsc_counter_l, tsc_counter_h;
 370	u32 wallclk_ctr, wallclk_cycles;
 371	bool direction;
 372	u32 dma_select;
 373	u32 timeout;
 374	u32 retry_count = 0;
 375
 376	runtime = substream->runtime;
 377
 378	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 379		direction = 1;
 380	else
 381		direction = 0;
 382
 383	/* 0th stream tag is not used, so DMA ch 0 is for 1st stream tag */
 384	do {
 385		timeout = 100;
 386		dma_select = (direction << GTSCC_CDMAS_DMA_DIR_SHIFT) |
 387					(azx_dev->core.stream_tag - 1);
 388		snd_hdac_chip_writel(azx_bus(chip), GTSCC, dma_select);
 389
 390		/* Enable the capture */
 391		snd_hdac_chip_updatel(azx_bus(chip), GTSCC, 0, GTSCC_TSCCI_MASK);
 392
 393		while (timeout) {
 394			if (snd_hdac_chip_readl(azx_bus(chip), GTSCC) &
 395						GTSCC_TSCCD_MASK)
 396				break;
 397
 398			timeout--;
 399		}
 400
 401		if (!timeout) {
 402			dev_err(chip->card->dev, "GTSCC capture Timedout!\n");
 403			return -EIO;
 404		}
 405
 406		/* Read wall clock counter */
 407		wallclk_ctr = snd_hdac_chip_readl(azx_bus(chip), WALFCC);
 408
 409		/* Read TSC counter */
 410		tsc_counter_l = snd_hdac_chip_readl(azx_bus(chip), TSCCL);
 411		tsc_counter_h = snd_hdac_chip_readl(azx_bus(chip), TSCCU);
 412
 413		/* Read Link counter */
 414		ll_counter_l = snd_hdac_chip_readl(azx_bus(chip), LLPCL);
 415		ll_counter_h = snd_hdac_chip_readl(azx_bus(chip), LLPCU);
 416
 417		/* Ack: registers read done */
 418		snd_hdac_chip_writel(azx_bus(chip), GTSCC, GTSCC_TSCCD_SHIFT);
 419
 420		tsc_counter = (tsc_counter_h << TSCCU_CCU_SHIFT) |
 421						tsc_counter_l;
 422
 423		ll_counter = (ll_counter_h << LLPC_CCU_SHIFT) |	ll_counter_l;
 424		wallclk_cycles = wallclk_ctr & WALFCC_CIF_MASK;
 425
 426		/*
 427		 * An error occurs near frame "rollover". The clocks in
 428		 * frame value indicates whether this error may have
 429		 * occurred. Here we use the value of 10 i.e.,
 430		 * HDA_MAX_CYCLE_OFFSET
 431		 */
 432		if (wallclk_cycles < HDA_MAX_CYCLE_VALUE - HDA_MAX_CYCLE_OFFSET
 433					&& wallclk_cycles > HDA_MAX_CYCLE_OFFSET)
 434			break;
 435
 436		/*
 437		 * Sleep before we read again, else we may again get
 438		 * value near to MAX_CYCLE. Try to sleep for different
 439		 * amount of time so we dont hit the same number again
 440		 */
 441		udelay(retry_count++);
 442
 443	} while (retry_count != HDA_MAX_CYCLE_READ_RETRY);
 444
 445	if (retry_count == HDA_MAX_CYCLE_READ_RETRY) {
 446		dev_err_ratelimited(chip->card->dev,
 447			"Error in WALFCC cycle count\n");
 448		return -EIO;
 449	}
 450
 451	*device = ns_to_ktime(azx_scale64(ll_counter,
 452				NSEC_PER_SEC, runtime->rate));
 453	*device = ktime_add_ns(*device, (wallclk_cycles * NSEC_PER_SEC) /
 454			       ((HDA_MAX_CYCLE_VALUE + 1) * runtime->rate));
 455
 456	system->cycles = tsc_counter;
 457	system->cs_id = CSID_X86_ART;
 458
 459	return 0;
 460}
 461
 462#else
 463static int azx_get_sync_time(ktime_t *device,
 464		struct system_counterval_t *system, void *ctx)
 465{
 466	return -ENXIO;
 467}
 468#endif
 469
 470static int azx_get_crosststamp(struct snd_pcm_substream *substream,
 471			      struct system_device_crosststamp *xtstamp)
 472{
 473	return get_device_system_crosststamp(azx_get_sync_time,
 474					substream, NULL, xtstamp);
 475}
 476
 477static inline bool is_link_time_supported(struct snd_pcm_runtime *runtime,
 478				struct snd_pcm_audio_tstamp_config *ts)
 479{
 480	if (runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME)
 481		if (ts->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED)
 482			return true;
 483
 484	return false;
 485}
 486
 487static int azx_get_time_info(struct snd_pcm_substream *substream,
 488			struct timespec64 *system_ts, struct timespec64 *audio_ts,
 489			struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
 490			struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
 491{
 492	struct azx_dev *azx_dev = get_azx_dev(substream);
 493	struct snd_pcm_runtime *runtime = substream->runtime;
 494	struct system_device_crosststamp xtstamp;
 495	int ret;
 496	u64 nsec;
 497
 498	if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
 499		(audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
 500
 501		snd_pcm_gettime(substream->runtime, system_ts);
 502
 503		nsec = timecounter_read(&azx_dev->core.tc);
 504		if (audio_tstamp_config->report_delay)
 505			nsec = azx_adjust_codec_delay(substream, nsec);
 506
 507		*audio_ts = ns_to_timespec64(nsec);
 508
 509		audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
 510		audio_tstamp_report->accuracy_report = 1; /* rest of structure is valid */
 511		audio_tstamp_report->accuracy = 42; /* 24 MHz WallClock == 42ns resolution */
 512
 513	} else if (is_link_time_supported(runtime, audio_tstamp_config)) {
 514
 515		ret = azx_get_crosststamp(substream, &xtstamp);
 516		if (ret)
 517			return ret;
 518
 519		switch (runtime->tstamp_type) {
 520		case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC:
 521			return -EINVAL;
 522
 523		case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW:
 524			*system_ts = ktime_to_timespec64(xtstamp.sys_monoraw);
 525			break;
 526
 527		default:
 528			*system_ts = ktime_to_timespec64(xtstamp.sys_realtime);
 529			break;
 530
 531		}
 532
 533		*audio_ts = ktime_to_timespec64(xtstamp.device);
 534
 535		audio_tstamp_report->actual_type =
 536			SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED;
 537		audio_tstamp_report->accuracy_report = 1;
 538		/* 24 MHz WallClock == 42ns resolution */
 539		audio_tstamp_report->accuracy = 42;
 540
 541	} else {
 542		audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
 543	}
 544
 545	return 0;
 546}
 547
 548static const struct snd_pcm_hardware azx_pcm_hw = {
 549	.info =			(SNDRV_PCM_INFO_MMAP |
 550				 SNDRV_PCM_INFO_INTERLEAVED |
 551				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
 552				 SNDRV_PCM_INFO_MMAP_VALID |
 553				 /* No full-resume yet implemented */
 554				 /* SNDRV_PCM_INFO_RESUME |*/
 555				 SNDRV_PCM_INFO_PAUSE |
 556				 SNDRV_PCM_INFO_SYNC_START |
 557				 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
 558				 SNDRV_PCM_INFO_HAS_LINK_ATIME |
 559				 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
 560	.formats =		SNDRV_PCM_FMTBIT_S16_LE,
 561	.rates =		SNDRV_PCM_RATE_48000,
 562	.rate_min =		48000,
 563	.rate_max =		48000,
 564	.channels_min =		2,
 565	.channels_max =		2,
 566	.buffer_bytes_max =	AZX_MAX_BUF_SIZE,
 567	.period_bytes_min =	128,
 568	.period_bytes_max =	AZX_MAX_BUF_SIZE / 2,
 569	.periods_min =		2,
 570	.periods_max =		AZX_MAX_FRAG,
 571	.fifo_size =		0,
 572};
 573
 574static int azx_pcm_open(struct snd_pcm_substream *substream)
 575{
 576	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 577	struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 578	struct azx *chip = apcm->chip;
 579	struct azx_dev *azx_dev;
 580	struct snd_pcm_runtime *runtime = substream->runtime;
 581	int err;
 582	int buff_step;
 583
 584	snd_hda_codec_pcm_get(apcm->info);
 585	mutex_lock(&chip->open_mutex);
 586	azx_dev = azx_assign_device(chip, substream);
 587	trace_azx_pcm_open(chip, azx_dev);
 588	if (azx_dev == NULL) {
 589		err = -EBUSY;
 590		goto unlock;
 591	}
 592	runtime->private_data = azx_dev;
 593
 594	runtime->hw = azx_pcm_hw;
 595	if (chip->gts_present)
 596		runtime->hw.info |= SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME;
 597	runtime->hw.channels_min = hinfo->channels_min;
 598	runtime->hw.channels_max = hinfo->channels_max;
 599	runtime->hw.formats = hinfo->formats;
 600	runtime->hw.rates = hinfo->rates;
 601	snd_pcm_limit_hw_rates(runtime);
 602	snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
 603
 604	/* avoid wrap-around with wall-clock */
 605	snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
 606				     20,
 607				     178000000);
 608
 609	if (chip->align_buffer_size)
 610		/* constrain buffer sizes to be multiple of 128
 611		   bytes. This is more efficient in terms of memory
 612		   access but isn't required by the HDA spec and
 613		   prevents users from specifying exact period/buffer
 614		   sizes. For example for 44.1kHz, a period size set
 615		   to 20ms will be rounded to 19.59ms. */
 616		buff_step = 128;
 617	else
 618		/* Don't enforce steps on buffer sizes, still need to
 619		   be multiple of 4 bytes (HDA spec). Tested on Intel
 620		   HDA controllers, may not work on all devices where
 621		   option needs to be disabled */
 622		buff_step = 4;
 623
 624	snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
 625				   buff_step);
 626	snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
 627				   buff_step);
 628	snd_hda_power_up(apcm->codec);
 629	if (hinfo->ops.open)
 630		err = hinfo->ops.open(hinfo, apcm->codec, substream);
 631	else
 632		err = -ENODEV;
 633	if (err < 0) {
 634		azx_release_device(azx_dev);
 635		goto powerdown;
 636	}
 637	snd_pcm_limit_hw_rates(runtime);
 638	/* sanity check */
 639	if (snd_BUG_ON(!runtime->hw.channels_min) ||
 640	    snd_BUG_ON(!runtime->hw.channels_max) ||
 641	    snd_BUG_ON(!runtime->hw.formats) ||
 642	    snd_BUG_ON(!runtime->hw.rates)) {
 643		azx_release_device(azx_dev);
 644		if (hinfo->ops.close)
 645			hinfo->ops.close(hinfo, apcm->codec, substream);
 646		err = -EINVAL;
 647		goto powerdown;
 648	}
 649
 650	/* disable LINK_ATIME timestamps for capture streams
 651	   until we figure out how to handle digital inputs */
 652	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 653		runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
 654		runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
 655	}
 656
 657	snd_pcm_set_sync(substream);
 658	mutex_unlock(&chip->open_mutex);
 659	return 0;
 660
 661 powerdown:
 662	snd_hda_power_down(apcm->codec);
 663 unlock:
 664	mutex_unlock(&chip->open_mutex);
 665	snd_hda_codec_pcm_put(apcm->info);
 666	return err;
 667}
 668
 669static const struct snd_pcm_ops azx_pcm_ops = {
 670	.open = azx_pcm_open,
 671	.close = azx_pcm_close,
 672	.hw_params = azx_pcm_hw_params,
 673	.hw_free = azx_pcm_hw_free,
 674	.prepare = azx_pcm_prepare,
 675	.trigger = azx_pcm_trigger,
 676	.pointer = azx_pcm_pointer,
 677	.get_time_info =  azx_get_time_info,
 678};
 679
 680static void azx_pcm_free(struct snd_pcm *pcm)
 681{
 682	struct azx_pcm *apcm = pcm->private_data;
 683	if (apcm) {
 684		list_del(&apcm->list);
 685		apcm->info->pcm = NULL;
 686		kfree(apcm);
 687	}
 688}
 689
 690#define MAX_PREALLOC_SIZE	(32 * 1024 * 1024)
 691
 692int snd_hda_attach_pcm_stream(struct hda_bus *_bus, struct hda_codec *codec,
 693			      struct hda_pcm *cpcm)
 694{
 695	struct hdac_bus *bus = &_bus->core;
 696	struct azx *chip = bus_to_azx(bus);
 697	struct snd_pcm *pcm;
 698	struct azx_pcm *apcm;
 699	int pcm_dev = cpcm->device;
 700	unsigned int size;
 701	int s, err;
 702	int type = SNDRV_DMA_TYPE_DEV_SG;
 703
 704	list_for_each_entry(apcm, &chip->pcm_list, list) {
 705		if (apcm->pcm->device == pcm_dev) {
 706			dev_err(chip->card->dev, "PCM %d already exists\n",
 707				pcm_dev);
 708			return -EBUSY;
 709		}
 710	}
 711	err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
 712			  cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
 713			  cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
 714			  &pcm);
 715	if (err < 0)
 716		return err;
 717	strscpy(pcm->name, cpcm->name, sizeof(pcm->name));
 718	apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
 719	if (apcm == NULL) {
 720		snd_device_free(chip->card, pcm);
 721		return -ENOMEM;
 722	}
 723	apcm->chip = chip;
 724	apcm->pcm = pcm;
 725	apcm->codec = codec;
 726	apcm->info = cpcm;
 727	pcm->private_data = apcm;
 728	pcm->private_free = azx_pcm_free;
 729	if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
 730		pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
 731	list_add_tail(&apcm->list, &chip->pcm_list);
 732	cpcm->pcm = pcm;
 733	for (s = 0; s < 2; s++) {
 734		if (cpcm->stream[s].substreams)
 735			snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
 736	}
 737	/* buffer pre-allocation */
 738	size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
 739	if (size > MAX_PREALLOC_SIZE)
 740		size = MAX_PREALLOC_SIZE;
 741	if (chip->uc_buffer)
 742		type = SNDRV_DMA_TYPE_DEV_WC_SG;
 743	snd_pcm_set_managed_buffer_all(pcm, type, chip->card->dev,
 744				       size, MAX_PREALLOC_SIZE);
 745	return 0;
 746}
 747
 748static unsigned int azx_command_addr(u32 cmd)
 749{
 750	unsigned int addr = cmd >> 28;
 751
 752	if (addr >= AZX_MAX_CODECS) {
 753		snd_BUG();
 754		addr = 0;
 755	}
 756
 757	return addr;
 758}
 759
 760/* receive a response */
 761static int azx_rirb_get_response(struct hdac_bus *bus, unsigned int addr,
 762				 unsigned int *res)
 763{
 764	struct azx *chip = bus_to_azx(bus);
 765	struct hda_bus *hbus = &chip->bus;
 766	int err;
 767
 768 again:
 769	err = snd_hdac_bus_get_response(bus, addr, res);
 770	if (!err)
 771		return 0;
 772
 773	if (hbus->no_response_fallback)
 774		return -EIO;
 775
 776	if (!bus->polling_mode) {
 777		dev_warn(chip->card->dev,
 778			 "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
 779			 bus->last_cmd[addr]);
 780		bus->polling_mode = 1;
 781		goto again;
 782	}
 783
 784	if (chip->msi) {
 785		dev_warn(chip->card->dev,
 786			 "No response from codec, disabling MSI: last cmd=0x%08x\n",
 787			 bus->last_cmd[addr]);
 788		if (chip->ops->disable_msi_reset_irq &&
 789		    chip->ops->disable_msi_reset_irq(chip) < 0)
 790			return -EIO;
 791		goto again;
 792	}
 793
 794	if (chip->probing) {
 795		/* If this critical timeout happens during the codec probing
 796		 * phase, this is likely an access to a non-existing codec
 797		 * slot.  Better to return an error and reset the system.
 798		 */
 799		return -EIO;
 800	}
 801
 802	/* no fallback mechanism? */
 803	if (!chip->fallback_to_single_cmd)
 804		return -EIO;
 805
 806	/* a fatal communication error; need either to reset or to fallback
 807	 * to the single_cmd mode
 808	 */
 809	if (hbus->allow_bus_reset && !hbus->response_reset && !hbus->in_reset) {
 810		hbus->response_reset = 1;
 811		dev_err(chip->card->dev,
 812			"No response from codec, resetting bus: last cmd=0x%08x\n",
 813			bus->last_cmd[addr]);
 814		return -EAGAIN; /* give a chance to retry */
 815	}
 816
 817	dev_err(chip->card->dev,
 818		"azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
 819		bus->last_cmd[addr]);
 820	chip->single_cmd = 1;
 821	hbus->response_reset = 0;
 822	snd_hdac_bus_stop_cmd_io(bus);
 823	return -EIO;
 824}
 825
 826/*
 827 * Use the single immediate command instead of CORB/RIRB for simplicity
 828 *
 829 * Note: according to Intel, this is not preferred use.  The command was
 830 *       intended for the BIOS only, and may get confused with unsolicited
 831 *       responses.  So, we shouldn't use it for normal operation from the
 832 *       driver.
 833 *       I left the codes, however, for debugging/testing purposes.
 834 */
 835
 836/* receive a response */
 837static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 838{
 839	int timeout = 50;
 840
 841	while (timeout--) {
 842		/* check IRV busy bit */
 843		if (azx_readw(chip, IRS) & AZX_IRS_VALID) {
 844			/* reuse rirb.res as the response return value */
 845			azx_bus(chip)->rirb.res[addr] = azx_readl(chip, IR);
 846			return 0;
 847		}
 848		udelay(1);
 849	}
 850	if (printk_ratelimit())
 851		dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
 852			azx_readw(chip, IRS));
 853	azx_bus(chip)->rirb.res[addr] = -1;
 854	return -EIO;
 855}
 856
 857/* send a command */
 858static int azx_single_send_cmd(struct hdac_bus *bus, u32 val)
 859{
 860	struct azx *chip = bus_to_azx(bus);
 861	unsigned int addr = azx_command_addr(val);
 862	int timeout = 50;
 863
 864	bus->last_cmd[azx_command_addr(val)] = val;
 865	while (timeout--) {
 866		/* check ICB busy bit */
 867		if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) {
 868			/* Clear IRV valid bit */
 869			azx_writew(chip, IRS, azx_readw(chip, IRS) |
 870				   AZX_IRS_VALID);
 871			azx_writel(chip, IC, val);
 872			azx_writew(chip, IRS, azx_readw(chip, IRS) |
 873				   AZX_IRS_BUSY);
 874			return azx_single_wait_for_response(chip, addr);
 875		}
 876		udelay(1);
 877	}
 878	if (printk_ratelimit())
 879		dev_dbg(chip->card->dev,
 880			"send_cmd timeout: IRS=0x%x, val=0x%x\n",
 881			azx_readw(chip, IRS), val);
 882	return -EIO;
 883}
 884
 885/* receive a response */
 886static int azx_single_get_response(struct hdac_bus *bus, unsigned int addr,
 887				   unsigned int *res)
 888{
 889	if (res)
 890		*res = bus->rirb.res[addr];
 891	return 0;
 892}
 893
 894/*
 895 * The below are the main callbacks from hda_codec.
 896 *
 897 * They are just the skeleton to call sub-callbacks according to the
 898 * current setting of chip->single_cmd.
 899 */
 900
 901/* send a command */
 902static int azx_send_cmd(struct hdac_bus *bus, unsigned int val)
 903{
 904	struct azx *chip = bus_to_azx(bus);
 905
 906	if (chip->disabled)
 907		return 0;
 908	if (chip->single_cmd || bus->use_pio_for_commands)
 909		return azx_single_send_cmd(bus, val);
 910	else
 911		return snd_hdac_bus_send_cmd(bus, val);
 912}
 913
 914/* get a response */
 915static int azx_get_response(struct hdac_bus *bus, unsigned int addr,
 916			    unsigned int *res)
 917{
 918	struct azx *chip = bus_to_azx(bus);
 919
 920	if (chip->disabled)
 921		return 0;
 922	if (chip->single_cmd || bus->use_pio_for_commands)
 923		return azx_single_get_response(bus, addr, res);
 924	else
 925		return azx_rirb_get_response(bus, addr, res);
 926}
 927
 928static const struct hdac_bus_ops bus_core_ops = {
 929	.command = azx_send_cmd,
 930	.get_response = azx_get_response,
 931};
 932
 933#ifdef CONFIG_SND_HDA_DSP_LOADER
 934/*
 935 * DSP loading code (e.g. for CA0132)
 936 */
 937
 938/* use the first stream for loading DSP */
 939static struct azx_dev *
 940azx_get_dsp_loader_dev(struct azx *chip)
 941{
 942	struct hdac_bus *bus = azx_bus(chip);
 943	struct hdac_stream *s;
 944
 945	list_for_each_entry(s, &bus->stream_list, list)
 946		if (s->index == chip->playback_index_offset)
 947			return stream_to_azx_dev(s);
 948
 949	return NULL;
 950}
 951
 952int snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format,
 953				   unsigned int byte_size,
 954				   struct snd_dma_buffer *bufp)
 955{
 956	struct hdac_bus *bus = &codec->bus->core;
 957	struct azx *chip = bus_to_azx(bus);
 958	struct azx_dev *azx_dev;
 959	struct hdac_stream *hstr;
 960	bool saved = false;
 961	int err;
 962
 963	azx_dev = azx_get_dsp_loader_dev(chip);
 964	hstr = azx_stream(azx_dev);
 965	scoped_guard(spinlock_irq, &bus->reg_lock) {
 966		if (hstr->opened) {
 967			chip->saved_azx_dev = *azx_dev;
 968			saved = true;
 969		}
 970	}
 971
 972	err = snd_hdac_dsp_prepare(hstr, format, byte_size, bufp);
 973	if (err < 0) {
 974		guard(spinlock_irq)(&bus->reg_lock);
 975		if (saved)
 976			*azx_dev = chip->saved_azx_dev;
 977		return err;
 978	}
 979
 980	hstr->prepared = 0;
 981	return err;
 982}
 983EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_prepare);
 984
 985void snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start)
 986{
 987	struct hdac_bus *bus = &codec->bus->core;
 988	struct azx *chip = bus_to_azx(bus);
 989	struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
 990
 991	snd_hdac_dsp_trigger(azx_stream(azx_dev), start);
 992}
 993EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_trigger);
 994
 995void snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec,
 996				    struct snd_dma_buffer *dmab)
 997{
 998	struct hdac_bus *bus = &codec->bus->core;
 999	struct azx *chip = bus_to_azx(bus);
1000	struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1001	struct hdac_stream *hstr = azx_stream(azx_dev);
1002
1003	if (!dmab->area || !hstr->locked)
1004		return;
1005
1006	snd_hdac_dsp_cleanup(hstr, dmab);
1007	guard(spinlock_irq)(&bus->reg_lock);
1008	if (hstr->opened)
1009		*azx_dev = chip->saved_azx_dev;
1010	hstr->locked = false;
1011}
1012EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_cleanup);
1013#endif /* CONFIG_SND_HDA_DSP_LOADER */
1014
1015/*
1016 * reset and start the controller registers
1017 */
1018void azx_init_chip(struct azx *chip, bool full_reset)
1019{
1020	if (snd_hdac_bus_init_chip(azx_bus(chip), full_reset)) {
1021		/* correct RINTCNT for CXT */
1022		if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1023			azx_writew(chip, RINTCNT, 0xc0);
1024	}
1025}
1026EXPORT_SYMBOL_GPL(azx_init_chip);
1027
1028void azx_stop_all_streams(struct azx *chip)
1029{
1030	struct hdac_bus *bus = azx_bus(chip);
1031
1032	snd_hdac_stop_streams(bus);
1033}
1034EXPORT_SYMBOL_GPL(azx_stop_all_streams);
1035
1036void azx_stop_chip(struct azx *chip)
1037{
1038	snd_hdac_bus_stop_chip(azx_bus(chip));
1039}
1040EXPORT_SYMBOL_GPL(azx_stop_chip);
1041
1042/*
1043 * interrupt handler
1044 */
1045static void stream_update(struct hdac_bus *bus, struct hdac_stream *s)
1046{
1047	struct azx *chip = bus_to_azx(bus);
1048	struct azx_dev *azx_dev = stream_to_azx_dev(s);
1049
1050	/* check whether this IRQ is really acceptable */
1051	if (!chip->ops->position_check ||
1052	    chip->ops->position_check(chip, azx_dev)) {
1053		spin_unlock(&bus->reg_lock);
1054		snd_pcm_period_elapsed(azx_stream(azx_dev)->substream);
1055		spin_lock(&bus->reg_lock);
1056	}
1057}
1058
1059irqreturn_t azx_interrupt(int irq, void *dev_id)
1060{
1061	struct azx *chip = dev_id;
1062	struct hdac_bus *bus = azx_bus(chip);
1063	u32 status;
1064	bool active, handled = false;
1065	int repeat = 0; /* count for avoiding endless loop */
1066
1067	if (azx_has_pm_runtime(chip))
1068		if (!pm_runtime_active(chip->card->dev))
1069			return IRQ_NONE;
1070
1071	guard(spinlock)(&bus->reg_lock);
1072
1073	if (chip->disabled)
1074		return IRQ_NONE;
1075
1076	do {
1077		status = azx_readl(chip, INTSTS);
1078		if (status == 0 || status == 0xffffffff)
1079			break;
1080
1081		handled = true;
1082		active = false;
1083		if (snd_hdac_bus_handle_stream_irq(bus, status, stream_update))
1084			active = true;
1085
1086		status = azx_readb(chip, RIRBSTS);
1087		if (status & RIRB_INT_MASK) {
1088			/*
1089			 * Clearing the interrupt status here ensures that no
1090			 * interrupt gets masked after the RIRB wp is read in
1091			 * snd_hdac_bus_update_rirb. This avoids a possible
1092			 * race condition where codec response in RIRB may
1093			 * remain unserviced by IRQ, eventually falling back
1094			 * to polling mode in azx_rirb_get_response.
1095			 */
1096			azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1097			active = true;
1098			if (status & RIRB_INT_RESPONSE) {
1099				if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1100					udelay(80);
1101				snd_hdac_bus_update_rirb(bus);
1102			}
1103		}
1104	} while (active && ++repeat < 10);
1105
1106	return IRQ_RETVAL(handled);
1107}
1108EXPORT_SYMBOL_GPL(azx_interrupt);
1109
1110/*
1111 * Codec initerface
1112 */
1113
1114/*
1115 * Probe the given codec address
1116 */
1117static int probe_codec(struct azx *chip, int addr)
1118{
1119	unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1120		(AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1121	struct hdac_bus *bus = azx_bus(chip);
1122	int err;
1123	unsigned int res = -1;
1124
1125	scoped_guard(mutex, &bus->cmd_mutex) {
1126		chip->probing = 1;
1127		azx_send_cmd(bus, cmd);
1128		err = azx_get_response(bus, addr, &res);
1129		chip->probing = 0;
1130	}
1131	if (err < 0 || res == -1)
1132		return -EIO;
1133	dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
1134	return 0;
1135}
1136
1137void snd_hda_bus_reset(struct hda_bus *bus)
1138{
1139	struct azx *chip = bus_to_azx(&bus->core);
1140
1141	bus->in_reset = 1;
1142	azx_stop_chip(chip);
1143	azx_init_chip(chip, true);
1144	if (bus->core.chip_init)
1145		snd_hda_bus_reset_codecs(bus);
1146	bus->in_reset = 0;
1147}
1148
1149/* HD-audio bus initialization */
1150int azx_bus_init(struct azx *chip, const char *model)
1151{
1152	struct hda_bus *bus = &chip->bus;
1153	int err;
1154
1155	err = snd_hdac_bus_init(&bus->core, chip->card->dev, &bus_core_ops);
1156	if (err < 0)
1157		return err;
1158
1159	bus->card = chip->card;
1160	mutex_init(&bus->prepare_mutex);
1161	bus->pci = chip->pci;
1162	bus->modelname = model;
1163	bus->mixer_assigned = -1;
1164	bus->core.snoop = azx_snoop(chip);
1165	if (chip->get_position[0] != azx_get_pos_lpib ||
1166	    chip->get_position[1] != azx_get_pos_lpib)
1167		bus->core.use_posbuf = true;
1168	bus->core.bdl_pos_adj = chip->bdl_pos_adj;
1169	if (chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)
1170		bus->core.corbrp_self_clear = true;
1171
1172	if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY)
1173		bus->core.align_bdle_4k = true;
1174
1175	if (chip->driver_caps & AZX_DCAPS_PIO_COMMANDS)
1176		bus->core.use_pio_for_commands = true;
1177
1178	/* enable sync_write flag for stable communication as default */
1179	bus->core.sync_write = 1;
1180
1181	return 0;
1182}
1183EXPORT_SYMBOL_GPL(azx_bus_init);
1184
1185/* Probe codecs */
1186int azx_probe_codecs(struct azx *chip, unsigned int max_slots)
1187{
1188	struct hdac_bus *bus = azx_bus(chip);
1189	int c, codecs, err;
1190
1191	codecs = 0;
1192	if (!max_slots)
1193		max_slots = AZX_DEFAULT_CODECS;
1194
1195	/* First try to probe all given codec slots */
1196	for (c = 0; c < max_slots; c++) {
1197		if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1198			if (probe_codec(chip, c) < 0) {
1199				/* Some BIOSen give you wrong codec addresses
1200				 * that don't exist
1201				 */
1202				dev_warn(chip->card->dev,
1203					 "Codec #%d probe error; disabling it...\n", c);
1204				bus->codec_mask &= ~(1 << c);
1205				/* no codecs */
1206				if (bus->codec_mask == 0)
1207					break;
1208				/* More badly, accessing to a non-existing
1209				 * codec often screws up the controller chip,
1210				 * and disturbs the further communications.
1211				 * Thus if an error occurs during probing,
1212				 * better to reset the controller chip to
1213				 * get back to the sanity state.
1214				 */
1215				azx_stop_chip(chip);
1216				azx_init_chip(chip, true);
1217			}
1218		}
1219	}
1220
1221	/* Then create codec instances */
1222	for (c = 0; c < max_slots; c++) {
1223		if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1224			struct hda_codec *codec;
1225			err = snd_hda_codec_new(&chip->bus, chip->card, c, &codec);
1226			if (err < 0)
1227				continue;
1228			codec->jackpoll_interval = chip->jackpoll_interval;
1229			codec->beep_mode = chip->beep_mode;
1230			codec->ctl_dev_id = chip->ctl_dev_id;
1231			codecs++;
1232		}
1233	}
1234	if (!codecs) {
1235		dev_err(chip->card->dev, "no codecs initialized\n");
1236		return -ENXIO;
1237	}
1238	return 0;
1239}
1240EXPORT_SYMBOL_GPL(azx_probe_codecs);
1241
1242/* configure each codec instance */
1243int azx_codec_configure(struct azx *chip)
1244{
1245	struct hda_codec *codec, *next;
1246	int success = 0;
1247
1248	list_for_each_codec(codec, &chip->bus) {
1249		if (!snd_hda_codec_configure(codec))
1250			success++;
1251	}
1252
1253	if (success) {
1254		/* unregister failed codecs if any codec has been probed */
1255		list_for_each_codec_safe(codec, next, &chip->bus) {
1256			if (!codec->configured) {
1257				codec_err(codec, "Unable to configure, disabling\n");
1258				snd_hdac_device_unregister(&codec->core);
1259			}
1260		}
1261	}
1262
1263	return success ? 0 : -ENODEV;
1264}
1265EXPORT_SYMBOL_GPL(azx_codec_configure);
1266
1267static int stream_direction(struct azx *chip, unsigned char index)
1268{
1269	if (index >= chip->capture_index_offset &&
1270	    index < chip->capture_index_offset + chip->capture_streams)
1271		return SNDRV_PCM_STREAM_CAPTURE;
1272	return SNDRV_PCM_STREAM_PLAYBACK;
1273}
1274
1275/* initialize SD streams */
1276int azx_init_streams(struct azx *chip)
1277{
1278	int i;
1279	int stream_tags[2] = { 0, 0 };
1280
1281	/* initialize each stream (aka device)
1282	 * assign the starting bdl address to each stream (device)
1283	 * and initialize
1284	 */
1285	for (i = 0; i < chip->num_streams; i++) {
1286		struct azx_dev *azx_dev = kzalloc(sizeof(*azx_dev), GFP_KERNEL);
1287		int dir, tag;
1288
1289		if (!azx_dev)
1290			return -ENOMEM;
1291
1292		dir = stream_direction(chip, i);
1293		/* stream tag must be unique throughout
1294		 * the stream direction group,
1295		 * valid values 1...15
1296		 * use separate stream tag if the flag
1297		 * AZX_DCAPS_SEPARATE_STREAM_TAG is used
1298		 */
1299		if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG)
1300			tag = ++stream_tags[dir];
1301		else
1302			tag = i + 1;
1303		snd_hdac_stream_init(azx_bus(chip), azx_stream(azx_dev),
1304				     i, dir, tag);
1305	}
1306
1307	return 0;
1308}
1309EXPORT_SYMBOL_GPL(azx_init_streams);
1310
1311void azx_free_streams(struct azx *chip)
1312{
1313	struct hdac_bus *bus = azx_bus(chip);
1314	struct hdac_stream *s;
1315
1316	while (!list_empty(&bus->stream_list)) {
1317		s = list_first_entry(&bus->stream_list, struct hdac_stream, list);
1318		list_del(&s->list);
1319		kfree(stream_to_azx_dev(s));
1320	}
1321}
1322EXPORT_SYMBOL_GPL(azx_free_streams);