cs8409.h

  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 * HD audio codec driver for Cirrus Logic CS8409 HDA bridge chip
  4 *
  5 * Copyright (C) 2021 Cirrus Logic, Inc. and
  6 *                    Cirrus Logic International Semiconductor Ltd.
  7 */
  8
  9#ifndef __CS8409_PATCH_H
 10#define __CS8409_PATCH_H
 11
 12#include <linux/pci.h>
 13#include <sound/tlv.h>
 14#include <linux/workqueue.h>
 15#include <sound/cs42l42.h>
 16#include <sound/hda_codec.h>
 17#include "hda_local.h"
 18#include "hda_auto_parser.h"
 19#include "hda_jack.h"
 20#include "../generic.h"
 21
 22/* CS8409 Specific Definitions */
 23
 24enum cs8409_pins {
 25	CS8409_PIN_ROOT,
 26	CS8409_PIN_AFG,
 27	CS8409_PIN_ASP1_OUT_A,
 28	CS8409_PIN_ASP1_OUT_B,
 29	CS8409_PIN_ASP1_OUT_C,
 30	CS8409_PIN_ASP1_OUT_D,
 31	CS8409_PIN_ASP1_OUT_E,
 32	CS8409_PIN_ASP1_OUT_F,
 33	CS8409_PIN_ASP1_OUT_G,
 34	CS8409_PIN_ASP1_OUT_H,
 35	CS8409_PIN_ASP2_OUT_A,
 36	CS8409_PIN_ASP2_OUT_B,
 37	CS8409_PIN_ASP2_OUT_C,
 38	CS8409_PIN_ASP2_OUT_D,
 39	CS8409_PIN_ASP2_OUT_E,
 40	CS8409_PIN_ASP2_OUT_F,
 41	CS8409_PIN_ASP2_OUT_G,
 42	CS8409_PIN_ASP2_OUT_H,
 43	CS8409_PIN_ASP1_IN_A,
 44	CS8409_PIN_ASP1_IN_B,
 45	CS8409_PIN_ASP1_IN_C,
 46	CS8409_PIN_ASP1_IN_D,
 47	CS8409_PIN_ASP1_IN_E,
 48	CS8409_PIN_ASP1_IN_F,
 49	CS8409_PIN_ASP1_IN_G,
 50	CS8409_PIN_ASP1_IN_H,
 51	CS8409_PIN_ASP2_IN_A,
 52	CS8409_PIN_ASP2_IN_B,
 53	CS8409_PIN_ASP2_IN_C,
 54	CS8409_PIN_ASP2_IN_D,
 55	CS8409_PIN_ASP2_IN_E,
 56	CS8409_PIN_ASP2_IN_F,
 57	CS8409_PIN_ASP2_IN_G,
 58	CS8409_PIN_ASP2_IN_H,
 59	CS8409_PIN_DMIC1,
 60	CS8409_PIN_DMIC2,
 61	CS8409_PIN_ASP1_TRANSMITTER_A,
 62	CS8409_PIN_ASP1_TRANSMITTER_B,
 63	CS8409_PIN_ASP1_TRANSMITTER_C,
 64	CS8409_PIN_ASP1_TRANSMITTER_D,
 65	CS8409_PIN_ASP1_TRANSMITTER_E,
 66	CS8409_PIN_ASP1_TRANSMITTER_F,
 67	CS8409_PIN_ASP1_TRANSMITTER_G,
 68	CS8409_PIN_ASP1_TRANSMITTER_H,
 69	CS8409_PIN_ASP2_TRANSMITTER_A,
 70	CS8409_PIN_ASP2_TRANSMITTER_B,
 71	CS8409_PIN_ASP2_TRANSMITTER_C,
 72	CS8409_PIN_ASP2_TRANSMITTER_D,
 73	CS8409_PIN_ASP2_TRANSMITTER_E,
 74	CS8409_PIN_ASP2_TRANSMITTER_F,
 75	CS8409_PIN_ASP2_TRANSMITTER_G,
 76	CS8409_PIN_ASP2_TRANSMITTER_H,
 77	CS8409_PIN_ASP1_RECEIVER_A,
 78	CS8409_PIN_ASP1_RECEIVER_B,
 79	CS8409_PIN_ASP1_RECEIVER_C,
 80	CS8409_PIN_ASP1_RECEIVER_D,
 81	CS8409_PIN_ASP1_RECEIVER_E,
 82	CS8409_PIN_ASP1_RECEIVER_F,
 83	CS8409_PIN_ASP1_RECEIVER_G,
 84	CS8409_PIN_ASP1_RECEIVER_H,
 85	CS8409_PIN_ASP2_RECEIVER_A,
 86	CS8409_PIN_ASP2_RECEIVER_B,
 87	CS8409_PIN_ASP2_RECEIVER_C,
 88	CS8409_PIN_ASP2_RECEIVER_D,
 89	CS8409_PIN_ASP2_RECEIVER_E,
 90	CS8409_PIN_ASP2_RECEIVER_F,
 91	CS8409_PIN_ASP2_RECEIVER_G,
 92	CS8409_PIN_ASP2_RECEIVER_H,
 93	CS8409_PIN_DMIC1_IN,
 94	CS8409_PIN_DMIC2_IN,
 95	CS8409_PIN_BEEP_GEN,
 96	CS8409_PIN_VENDOR_WIDGET
 97};
 98
 99enum cs8409_coefficient_index_registers {
100	CS8409_DEV_CFG1,
101	CS8409_DEV_CFG2,
102	CS8409_DEV_CFG3,
103	CS8409_ASP1_CLK_CTRL1,
104	CS8409_ASP1_CLK_CTRL2,
105	CS8409_ASP1_CLK_CTRL3,
106	CS8409_ASP2_CLK_CTRL1,
107	CS8409_ASP2_CLK_CTRL2,
108	CS8409_ASP2_CLK_CTRL3,
109	CS8409_DMIC_CFG,
110	CS8409_BEEP_CFG,
111	ASP1_RX_NULL_INS_RMV,
112	ASP1_Rx_RATE1,
113	ASP1_Rx_RATE2,
114	ASP1_Tx_NULL_INS_RMV,
115	ASP1_Tx_RATE1,
116	ASP1_Tx_RATE2,
117	ASP2_Rx_NULL_INS_RMV,
118	ASP2_Rx_RATE1,
119	ASP2_Rx_RATE2,
120	ASP2_Tx_NULL_INS_RMV,
121	ASP2_Tx_RATE1,
122	ASP2_Tx_RATE2,
123	ASP1_SYNC_CTRL,
124	ASP2_SYNC_CTRL,
125	ASP1_A_TX_CTRL1,
126	ASP1_A_TX_CTRL2,
127	ASP1_B_TX_CTRL1,
128	ASP1_B_TX_CTRL2,
129	ASP1_C_TX_CTRL1,
130	ASP1_C_TX_CTRL2,
131	ASP1_D_TX_CTRL1,
132	ASP1_D_TX_CTRL2,
133	ASP1_E_TX_CTRL1,
134	ASP1_E_TX_CTRL2,
135	ASP1_F_TX_CTRL1,
136	ASP1_F_TX_CTRL2,
137	ASP1_G_TX_CTRL1,
138	ASP1_G_TX_CTRL2,
139	ASP1_H_TX_CTRL1,
140	ASP1_H_TX_CTRL2,
141	ASP2_A_TX_CTRL1,
142	ASP2_A_TX_CTRL2,
143	ASP2_B_TX_CTRL1,
144	ASP2_B_TX_CTRL2,
145	ASP2_C_TX_CTRL1,
146	ASP2_C_TX_CTRL2,
147	ASP2_D_TX_CTRL1,
148	ASP2_D_TX_CTRL2,
149	ASP2_E_TX_CTRL1,
150	ASP2_E_TX_CTRL2,
151	ASP2_F_TX_CTRL1,
152	ASP2_F_TX_CTRL2,
153	ASP2_G_TX_CTRL1,
154	ASP2_G_TX_CTRL2,
155	ASP2_H_TX_CTRL1,
156	ASP2_H_TX_CTRL2,
157	ASP1_A_RX_CTRL1,
158	ASP1_A_RX_CTRL2,
159	ASP1_B_RX_CTRL1,
160	ASP1_B_RX_CTRL2,
161	ASP1_C_RX_CTRL1,
162	ASP1_C_RX_CTRL2,
163	ASP1_D_RX_CTRL1,
164	ASP1_D_RX_CTRL2,
165	ASP1_E_RX_CTRL1,
166	ASP1_E_RX_CTRL2,
167	ASP1_F_RX_CTRL1,
168	ASP1_F_RX_CTRL2,
169	ASP1_G_RX_CTRL1,
170	ASP1_G_RX_CTRL2,
171	ASP1_H_RX_CTRL1,
172	ASP1_H_RX_CTRL2,
173	ASP2_A_RX_CTRL1,
174	ASP2_A_RX_CTRL2,
175	ASP2_B_RX_CTRL1,
176	ASP2_B_RX_CTRL2,
177	ASP2_C_RX_CTRL1,
178	ASP2_C_RX_CTRL2,
179	ASP2_D_RX_CTRL1,
180	ASP2_D_RX_CTRL2,
181	ASP2_E_RX_CTRL1,
182	ASP2_E_RX_CTRL2,
183	ASP2_F_RX_CTRL1,
184	ASP2_F_RX_CTRL2,
185	ASP2_G_RX_CTRL1,
186	ASP2_G_RX_CTRL2,
187	ASP2_H_RX_CTRL1,
188	ASP2_H_RX_CTRL2,
189	CS8409_I2C_ADDR,
190	CS8409_I2C_DATA,
191	CS8409_I2C_CTRL,
192	CS8409_I2C_STS,
193	CS8409_I2C_QWRITE,
194	CS8409_I2C_QREAD,
195	CS8409_SPI_CTRL,
196	CS8409_SPI_TX_DATA,
197	CS8409_SPI_RX_DATA,
198	CS8409_SPI_STS,
199	CS8409_PFE_COEF_W1, /* Parametric filter engine coefficient write 1*/
200	CS8409_PFE_COEF_W2,
201	CS8409_PFE_CTRL1,
202	CS8409_PFE_CTRL2,
203	CS8409_PRE_SCALE_ATTN1,
204	CS8409_PRE_SCALE_ATTN2,
205	CS8409_PFE_COEF_MON1, /* Parametric filter engine coefficient monitor 1*/
206	CS8409_PFE_COEF_MON2,
207	CS8409_ASP1_INTRN_STS,
208	CS8409_ASP2_INTRN_STS,
209	CS8409_ASP1_RX_SCLK_COUNT,
210	CS8409_ASP1_TX_SCLK_COUNT,
211	CS8409_ASP2_RX_SCLK_COUNT,
212	CS8409_ASP2_TX_SCLK_COUNT,
213	CS8409_ASP_UNS_RESP_MASK,
214	CS8409_LOOPBACK_CTRL = 0x80,
215	CS8409_PAD_CFG_SLW_RATE_CTRL = 0x82, /* Pad Config and Slew Rate Control (CIR = 0x0082) */
216};
217
218/* CS42L42 Specific Definitions */
219
220#define CS8409_MAX_CODECS			8
221#define CS42L42_VOLUMES				(4U)
222#define CS42L42_HP_VOL_REAL_MIN			(-63)
223#define CS42L42_HP_VOL_REAL_MAX			(0)
224#define CS42L42_AMIC_VOL_REAL_MIN		(-97)
225#define CS42L42_AMIC_VOL_REAL_MAX		(12)
226#define CS42L42_REG_AMIC_VOL_MASK		(0x00FF)
227#define CS42L42_HSTYPE_MASK			(0x03)
228#define CS42L42_I2C_TIMEOUT_US			(20000)
229#define CS42L42_I2C_SLEEP_US			(2000)
230#define CS42L42_PDN_TIMEOUT_US			(250000)
231#define CS42L42_PDN_SLEEP_US			(2000)
232#define CS42L42_ANA_MUTE_AB			(0x0C)
233#define CS42L42_FULL_SCALE_VOL_MASK		(2)
234#define CS42L42_FULL_SCALE_VOL_0DB		(0)
235#define CS42L42_FULL_SCALE_VOL_MINUS6DB		(1)
236
237/* Dell BULLSEYE / WARLOCK / CYBORG Specific Definitions */
238
239#define CS42L42_I2C_ADDR			(0x48 << 1)
240#define CS8409_CS42L42_RESET			GENMASK(5, 5) /* CS8409_GPIO5 */
241#define CS8409_CS42L42_INT			GENMASK(4, 4) /* CS8409_GPIO4 */
242#define CS8409_CYBORG_SPEAKER_PDN		GENMASK(2, 2) /* CS8409_GPIO2 */
243#define CS8409_WARLOCK_SPEAKER_PDN		GENMASK(1, 1) /* CS8409_GPIO1 */
244#define CS8409_CS42L42_HP_PIN_NID		CS8409_PIN_ASP1_TRANSMITTER_A
245#define CS8409_CS42L42_SPK_PIN_NID		CS8409_PIN_ASP2_TRANSMITTER_A
246#define CS8409_CS42L42_AMIC_PIN_NID		CS8409_PIN_ASP1_RECEIVER_A
247#define CS8409_CS42L42_DMIC_PIN_NID		CS8409_PIN_DMIC1_IN
248#define CS8409_CS42L42_DMIC_ADC_PIN_NID		CS8409_PIN_DMIC1
249
250/* Dolphin */
251
252#define DOLPHIN_C0_I2C_ADDR			(0x48 << 1)
253#define DOLPHIN_C1_I2C_ADDR			(0x49 << 1)
254#define DOLPHIN_HP_PIN_NID			CS8409_PIN_ASP1_TRANSMITTER_A
255#define DOLPHIN_LO_PIN_NID			CS8409_PIN_ASP1_TRANSMITTER_B
256#define DOLPHIN_AMIC_PIN_NID			CS8409_PIN_ASP1_RECEIVER_A
257
258#define DOLPHIN_C0_INT				GENMASK(4, 4)
259#define DOLPHIN_C1_INT				GENMASK(0, 0)
260#define DOLPHIN_C0_RESET			GENMASK(5, 5)
261#define DOLPHIN_C1_RESET			GENMASK(1, 1)
262#define DOLPHIN_WAKE				(DOLPHIN_C0_INT | DOLPHIN_C1_INT)
263
264enum {
265	CS8409_BULLSEYE,
266	CS8409_WARLOCK,
267	CS8409_WARLOCK_MLK,
268	CS8409_WARLOCK_MLK_DUAL_MIC,
269	CS8409_CYBORG,
270	CS8409_FIXUPS,
271	CS8409_DOLPHIN,
272	CS8409_DOLPHIN_FIXUPS,
273	CS8409_ODIN,
274};
275
276enum {
277	CS8409_CODEC0,
278	CS8409_CODEC1
279};
280
281enum {
282	CS42L42_VOL_ADC,
283	CS42L42_VOL_DAC,
284};
285
286#define CS42L42_ADC_VOL_OFFSET			(CS42L42_VOL_ADC)
287#define CS42L42_DAC_CH0_VOL_OFFSET		(CS42L42_VOL_DAC)
288#define CS42L42_DAC_CH1_VOL_OFFSET		(CS42L42_VOL_DAC + 1)
289
290struct cs8409_i2c_param {
291	unsigned int addr;
292	unsigned int value;
293	unsigned int delay;
294};
295
296struct cs8409_cir_param {
297	unsigned int nid;
298	unsigned int cir;
299	unsigned int coeff;
300};
301
302struct sub_codec {
303	struct hda_codec *codec;
304	unsigned int addr;
305	unsigned int reset_gpio;
306	unsigned int irq_mask;
307	const struct cs8409_i2c_param *init_seq;
308	unsigned int init_seq_num;
309
310	unsigned int hp_jack_in:1;
311	unsigned int mic_jack_in:1;
312	unsigned int suspended:1;
313	unsigned int paged:1;
314	unsigned int last_page;
315	unsigned int hsbias_hiz;
316	unsigned int full_scale_vol:1;
317	unsigned int no_type_dect:1;
318
319	s8 vol[CS42L42_VOLUMES];
320};
321
322struct cs8409_spec {
323	struct hda_gen_spec gen;
324	struct hda_codec *codec;
325
326	struct sub_codec *scodecs[CS8409_MAX_CODECS];
327	unsigned int num_scodecs;
328
329	unsigned int gpio_mask;
330	unsigned int gpio_dir;
331	unsigned int gpio_data;
332
333	int speaker_pdn_gpio;
334
335	struct mutex i2c_mux;
336	unsigned int i2c_clck_enabled;
337	unsigned int dev_addr;
338	struct delayed_work i2c_clk_work;
339
340	unsigned int playback_started:1;
341	unsigned int capture_started:1;
342	unsigned int init_done:1;
343	unsigned int build_ctrl_done:1;
344
345	/* verb exec op override */
346	int (*exec_verb)(struct hdac_device *dev, unsigned int cmd, unsigned int flags,
347			 unsigned int *res);
348	/* unsol_event op override */
349	void (*unsol_event)(struct hda_codec *codec, unsigned int res);
350};
351
352extern const struct snd_kcontrol_new cs42l42_dac_volume_mixer;
353extern const struct snd_kcontrol_new cs42l42_adc_volume_mixer;
354
355int cs42l42_volume_info(struct snd_kcontrol *kctrl, struct snd_ctl_elem_info *uinfo);
356int cs42l42_volume_get(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl);
357int cs42l42_volume_put(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl);
358
359extern const struct hda_pcm_stream cs42l42_48k_pcm_analog_playback;
360extern const struct hda_pcm_stream cs42l42_48k_pcm_analog_capture;
361extern const struct hda_quirk cs8409_fixup_tbl[];
362extern const struct hda_model_fixup cs8409_models[];
363extern const struct hda_fixup cs8409_fixups[];
364extern const struct hda_verb cs8409_cs42l42_init_verbs[];
365extern const struct cs8409_cir_param cs8409_cs42l42_hw_cfg[];
366extern const struct cs8409_cir_param cs8409_cs42l42_bullseye_atn[];
367extern struct sub_codec cs8409_cs42l42_codec;
368
369extern const struct hda_verb dolphin_init_verbs[];
370extern const struct cs8409_cir_param dolphin_hw_cfg[];
371extern struct sub_codec dolphin_cs42l42_0;
372extern struct sub_codec dolphin_cs42l42_1;
373
374void cs8409_cs42l42_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action);
375void dolphin_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action);
376
377#endif