cs8409.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * HD audio codec driver for Cirrus Logic CS8409 HDA bridge chip
   4 *
   5 * Copyright (C) 2021 Cirrus Logic, Inc. and
   6 *                    Cirrus Logic International Semiconductor Ltd.
   7 */
   8
   9#include <linux/init.h>
  10#include <linux/slab.h>
  11#include <linux/module.h>
  12#include <sound/core.h>
  13#include <linux/mutex.h>
  14#include <linux/iopoll.h>
  15
  16#include "cs8409.h"
  17
  18/******************************************************************************
  19 *                        CS8409 Specific Functions
  20 ******************************************************************************/
  21
  22static int cs8409_parse_auto_config(struct hda_codec *codec)
  23{
  24	struct cs8409_spec *spec = codec->spec;
  25	int err;
  26	int i;
  27
  28	err = snd_hda_parse_pin_defcfg(codec, &spec->gen.autocfg, NULL, 0);
  29	if (err < 0)
  30		return err;
  31
  32	err = snd_hda_gen_parse_auto_config(codec, &spec->gen.autocfg);
  33	if (err < 0)
  34		return err;
  35
  36	/* keep the ADCs powered up when it's dynamically switchable */
  37	if (spec->gen.dyn_adc_switch) {
  38		unsigned int done = 0;
  39
  40		for (i = 0; i < spec->gen.input_mux.num_items; i++) {
  41			int idx = spec->gen.dyn_adc_idx[i];
  42
  43			if (done & (1 << idx))
  44				continue;
  45			snd_hda_gen_fix_pin_power(codec, spec->gen.adc_nids[idx]);
  46			done |= 1 << idx;
  47		}
  48	}
  49
  50	return 0;
  51}
  52
  53static void cs8409_disable_i2c_clock_worker(struct work_struct *work);
  54
  55static struct cs8409_spec *cs8409_alloc_spec(struct hda_codec *codec)
  56{
  57	struct cs8409_spec *spec;
  58
  59	spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  60	if (!spec)
  61		return NULL;
  62	codec->spec = spec;
  63	spec->codec = codec;
  64	codec->power_save_node = 1;
  65	mutex_init(&spec->i2c_mux);
  66	INIT_DELAYED_WORK(&spec->i2c_clk_work, cs8409_disable_i2c_clock_worker);
  67	snd_hda_gen_spec_init(&spec->gen);
  68
  69	return spec;
  70}
  71
  72static inline int cs8409_vendor_coef_get(struct hda_codec *codec, unsigned int idx)
  73{
  74	snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx);
  75	return snd_hda_codec_read(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_GET_PROC_COEF, 0);
  76}
  77
  78static inline void cs8409_vendor_coef_set(struct hda_codec *codec, unsigned int idx,
  79					  unsigned int coef)
  80{
  81	snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx);
  82	snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_PROC_COEF, coef);
  83}
  84
  85/*
  86 * cs8409_enable_i2c_clock - Disable I2C clocks
  87 * @codec: the codec instance
  88 * Disable I2C clocks.
  89 * This must be called when the i2c mutex is unlocked.
  90 */
  91static void cs8409_disable_i2c_clock(struct hda_codec *codec)
  92{
  93	struct cs8409_spec *spec = codec->spec;
  94
  95	guard(mutex)(&spec->i2c_mux);
  96	if (spec->i2c_clck_enabled) {
  97		cs8409_vendor_coef_set(spec->codec, 0x0,
  98			       cs8409_vendor_coef_get(spec->codec, 0x0) & 0xfffffff7);
  99		spec->i2c_clck_enabled = 0;
 100	}
 101}
 102
 103/*
 104 * cs8409_disable_i2c_clock_worker - Worker that disable the I2C Clock after 25ms without use
 105 */
 106static void cs8409_disable_i2c_clock_worker(struct work_struct *work)
 107{
 108	struct cs8409_spec *spec = container_of(work, struct cs8409_spec, i2c_clk_work.work);
 109
 110	cs8409_disable_i2c_clock(spec->codec);
 111}
 112
 113/*
 114 * cs8409_enable_i2c_clock - Enable I2C clocks
 115 * @codec: the codec instance
 116 * Enable I2C clocks.
 117 * This must be called when the i2c mutex is locked.
 118 */
 119static void cs8409_enable_i2c_clock(struct hda_codec *codec)
 120{
 121	struct cs8409_spec *spec = codec->spec;
 122
 123	/* Cancel the disable timer, but do not wait for any running disable functions to finish.
 124	 * If the disable timer runs out before cancel, the delayed work thread will be blocked,
 125	 * waiting for the mutex to become unlocked. This mutex will be locked for the duration of
 126	 * any i2c transaction, so the disable function will run to completion immediately
 127	 * afterwards in the scenario. The next enable call will re-enable the clock, regardless.
 128	 */
 129	cancel_delayed_work(&spec->i2c_clk_work);
 130
 131	if (!spec->i2c_clck_enabled) {
 132		cs8409_vendor_coef_set(codec, 0x0, cs8409_vendor_coef_get(codec, 0x0) | 0x8);
 133		spec->i2c_clck_enabled = 1;
 134	}
 135	queue_delayed_work(system_power_efficient_wq, &spec->i2c_clk_work, msecs_to_jiffies(25));
 136}
 137
 138/**
 139 * cs8409_i2c_wait_complete - Wait for I2C transaction
 140 * @codec: the codec instance
 141 *
 142 * Wait for I2C transaction to complete.
 143 * Return -ETIMEDOUT if transaction wait times out.
 144 */
 145static int cs8409_i2c_wait_complete(struct hda_codec *codec)
 146{
 147	unsigned int retval;
 148
 149	return read_poll_timeout(cs8409_vendor_coef_get, retval, retval & 0x18,
 150		CS42L42_I2C_SLEEP_US, CS42L42_I2C_TIMEOUT_US, false, codec, CS8409_I2C_STS);
 151}
 152
 153/**
 154 * cs8409_set_i2c_dev_addr - Set i2c address for transaction
 155 * @codec: the codec instance
 156 * @addr: I2C Address
 157 */
 158static void cs8409_set_i2c_dev_addr(struct hda_codec *codec, unsigned int addr)
 159{
 160	struct cs8409_spec *spec = codec->spec;
 161
 162	if (spec->dev_addr != addr) {
 163		cs8409_vendor_coef_set(codec, CS8409_I2C_ADDR, addr);
 164		spec->dev_addr = addr;
 165	}
 166}
 167
 168/**
 169 * cs8409_i2c_set_page - CS8409 I2C set page register.
 170 * @scodec: the codec instance
 171 * @i2c_reg: Page register
 172 *
 173 * Returns negative on error.
 174 */
 175static int cs8409_i2c_set_page(struct sub_codec *scodec, unsigned int i2c_reg)
 176{
 177	struct hda_codec *codec = scodec->codec;
 178
 179	if (scodec->paged && (scodec->last_page != (i2c_reg >> 8))) {
 180		cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg >> 8);
 181		if (cs8409_i2c_wait_complete(codec) < 0)
 182			return -EIO;
 183		scodec->last_page = i2c_reg >> 8;
 184	}
 185
 186	return 0;
 187}
 188
 189/**
 190 * cs8409_i2c_read - CS8409 I2C Read.
 191 * @scodec: the codec instance
 192 * @addr: Register to read
 193 *
 194 * Returns negative on error, otherwise returns read value in bits 0-7.
 195 */
 196static int cs8409_i2c_read(struct sub_codec *scodec, unsigned int addr)
 197{
 198	struct hda_codec *codec = scodec->codec;
 199	struct cs8409_spec *spec = codec->spec;
 200	unsigned int i2c_reg_data;
 201	unsigned int read_data;
 202
 203	if (scodec->suspended)
 204		return -EPERM;
 205
 206	guard(mutex)(&spec->i2c_mux);
 207	cs8409_enable_i2c_clock(codec);
 208	cs8409_set_i2c_dev_addr(codec, scodec->addr);
 209
 210	if (cs8409_i2c_set_page(scodec, addr))
 211		goto error;
 212
 213	i2c_reg_data = (addr << 8) & 0x0ffff;
 214	cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data);
 215	if (cs8409_i2c_wait_complete(codec) < 0)
 216		goto error;
 217
 218	/* Register in bits 15-8 and the data in 7-0 */
 219	read_data = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD);
 220
 221	return read_data & 0x0ff;
 222
 223error:
 224	codec_err(codec, "%s() Failed 0x%02x : 0x%04x\n", __func__, scodec->addr, addr);
 225	return -EIO;
 226}
 227
 228/**
 229 * cs8409_i2c_bulk_read - CS8409 I2C Read Sequence.
 230 * @scodec: the codec instance
 231 * @seq: Register Sequence to read
 232 * @count: Number of registeres to read
 233 *
 234 * Returns negative on error, values are read into value element of cs8409_i2c_param sequence.
 235 */
 236static int cs8409_i2c_bulk_read(struct sub_codec *scodec, struct cs8409_i2c_param *seq, int count)
 237{
 238	struct hda_codec *codec = scodec->codec;
 239	struct cs8409_spec *spec = codec->spec;
 240	unsigned int i2c_reg_data;
 241	int i;
 242
 243	if (scodec->suspended)
 244		return -EPERM;
 245
 246	guard(mutex)(&spec->i2c_mux);
 247	cs8409_set_i2c_dev_addr(codec, scodec->addr);
 248
 249	for (i = 0; i < count; i++) {
 250		cs8409_enable_i2c_clock(codec);
 251		if (cs8409_i2c_set_page(scodec, seq[i].addr))
 252			goto error;
 253
 254		i2c_reg_data = (seq[i].addr << 8) & 0x0ffff;
 255		cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data);
 256
 257		if (cs8409_i2c_wait_complete(codec) < 0)
 258			goto error;
 259
 260		seq[i].value = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD) & 0xff;
 261	}
 262
 263	return 0;
 264
 265error:
 266	codec_err(codec, "I2C Bulk Write Failed 0x%02x\n", scodec->addr);
 267	return -EIO;
 268}
 269
 270/**
 271 * cs8409_i2c_write - CS8409 I2C Write.
 272 * @scodec: the codec instance
 273 * @addr: Register to write to
 274 * @value: Data to write
 275 *
 276 * Returns negative on error, otherwise returns 0.
 277 */
 278static int cs8409_i2c_write(struct sub_codec *scodec, unsigned int addr, unsigned int value)
 279{
 280	struct hda_codec *codec = scodec->codec;
 281	struct cs8409_spec *spec = codec->spec;
 282	unsigned int i2c_reg_data;
 283
 284	if (scodec->suspended)
 285		return -EPERM;
 286
 287	guard(mutex)(&spec->i2c_mux);
 288
 289	cs8409_enable_i2c_clock(codec);
 290	cs8409_set_i2c_dev_addr(codec, scodec->addr);
 291
 292	if (cs8409_i2c_set_page(scodec, addr))
 293		goto error;
 294
 295	i2c_reg_data = ((addr << 8) & 0x0ff00) | (value & 0x0ff);
 296	cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data);
 297
 298	if (cs8409_i2c_wait_complete(codec) < 0)
 299		goto error;
 300
 301	return 0;
 302
 303error:
 304	codec_err(codec, "%s() Failed 0x%02x : 0x%04x\n", __func__, scodec->addr, addr);
 305	return -EIO;
 306}
 307
 308/**
 309 * cs8409_i2c_bulk_write - CS8409 I2C Write Sequence.
 310 * @scodec: the codec instance
 311 * @seq: Register Sequence to write
 312 * @count: Number of registeres to write
 313 *
 314 * Returns negative on error.
 315 */
 316static int cs8409_i2c_bulk_write(struct sub_codec *scodec, const struct cs8409_i2c_param *seq,
 317				 int count)
 318{
 319	struct hda_codec *codec = scodec->codec;
 320	struct cs8409_spec *spec = codec->spec;
 321	unsigned int i2c_reg_data;
 322	int i;
 323
 324	if (scodec->suspended)
 325		return -EPERM;
 326
 327	guard(mutex)(&spec->i2c_mux);
 328	cs8409_set_i2c_dev_addr(codec, scodec->addr);
 329
 330	for (i = 0; i < count; i++) {
 331		cs8409_enable_i2c_clock(codec);
 332		if (cs8409_i2c_set_page(scodec, seq[i].addr))
 333			goto error;
 334
 335		i2c_reg_data = ((seq[i].addr << 8) & 0x0ff00) | (seq[i].value & 0x0ff);
 336		cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data);
 337
 338		if (cs8409_i2c_wait_complete(codec) < 0)
 339			goto error;
 340		/* Certain use cases may require a delay
 341		 * after a write operation before proceeding.
 342		 */
 343		if (seq[i].delay)
 344			fsleep(seq[i].delay);
 345	}
 346
 347	return 0;
 348
 349error:
 350	codec_err(codec, "I2C Bulk Write Failed 0x%02x\n", scodec->addr);
 351	return -EIO;
 352}
 353
 354static int cs8409_init(struct hda_codec *codec)
 355{
 356	int ret = snd_hda_gen_init(codec);
 357
 358	if (!ret)
 359		snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_INIT);
 360
 361	return ret;
 362}
 363
 364static int cs8409_build_controls(struct hda_codec *codec)
 365{
 366	int err;
 367
 368	err = snd_hda_gen_build_controls(codec);
 369	if (err < 0)
 370		return err;
 371	snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_BUILD);
 372
 373	return 0;
 374}
 375
 376/* Enable/Disable Unsolicited Response */
 377static void cs8409_enable_ur(struct hda_codec *codec, int flag)
 378{
 379	struct cs8409_spec *spec = codec->spec;
 380	unsigned int ur_gpios = 0;
 381	int i;
 382
 383	for (i = 0; i < spec->num_scodecs; i++)
 384		ur_gpios |= spec->scodecs[i]->irq_mask;
 385
 386	snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK,
 387			    flag ? ur_gpios : 0);
 388
 389	snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_UNSOLICITED_ENABLE,
 390			    flag ? AC_UNSOL_ENABLED : 0);
 391}
 392
 393static void cs8409_fix_caps(struct hda_codec *codec, unsigned int nid)
 394{
 395	int caps;
 396
 397	/* CS8409 is simple HDA bridge and intended to be used with a remote
 398	 * companion codec. Most of input/output PIN(s) have only basic
 399	 * capabilities. Receive and Transmit NID(s) have only OUTC and INC
 400	 * capabilities and no presence detect capable (PDC) and call to
 401	 * snd_hda_gen_build_controls() will mark them as non detectable
 402	 * phantom jacks. However, a companion codec may be
 403	 * connected to these pins which supports jack detect
 404	 * capabilities. We have to override pin capabilities,
 405	 * otherwise they will not be created as input devices.
 406	 */
 407	caps = snd_hdac_read_parm(&codec->core, nid, AC_PAR_PIN_CAP);
 408	if (caps >= 0)
 409		snd_hdac_override_parm(&codec->core, nid, AC_PAR_PIN_CAP,
 410				       (caps | (AC_PINCAP_IMP_SENSE | AC_PINCAP_PRES_DETECT)));
 411
 412	snd_hda_override_wcaps(codec, nid, (get_wcaps(codec, nid) | AC_WCAP_UNSOL_CAP));
 413}
 414
 415static int cs8409_spk_sw_gpio_get(struct snd_kcontrol *kcontrol,
 416				 struct snd_ctl_elem_value *ucontrol)
 417{
 418	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
 419	struct cs8409_spec *spec = codec->spec;
 420
 421	ucontrol->value.integer.value[0] = !!(spec->gpio_data & spec->speaker_pdn_gpio);
 422	return 0;
 423}
 424
 425static int cs8409_spk_sw_gpio_put(struct snd_kcontrol *kcontrol,
 426				 struct snd_ctl_elem_value *ucontrol)
 427{
 428	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
 429	struct cs8409_spec *spec = codec->spec;
 430	unsigned int gpio_data;
 431
 432	gpio_data = (spec->gpio_data & ~spec->speaker_pdn_gpio) |
 433		(ucontrol->value.integer.value[0] ? spec->speaker_pdn_gpio : 0);
 434	if (gpio_data == spec->gpio_data)
 435		return 0;
 436	spec->gpio_data = gpio_data;
 437	snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data);
 438	return 1;
 439}
 440
 441static const struct snd_kcontrol_new cs8409_spk_sw_ctrl = {
 442	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
 443	.info = snd_ctl_boolean_mono_info,
 444	.get = cs8409_spk_sw_gpio_get,
 445	.put = cs8409_spk_sw_gpio_put,
 446};
 447
 448/******************************************************************************
 449 *                        CS42L42 Specific Functions
 450 ******************************************************************************/
 451
 452int cs42l42_volume_info(struct snd_kcontrol *kctrl, struct snd_ctl_elem_info *uinfo)
 453{
 454	unsigned int ofs = get_amp_offset(kctrl);
 455	u8 chs = get_amp_channels(kctrl);
 456
 457	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 458	uinfo->value.integer.step = 1;
 459	uinfo->count = chs == 3 ? 2 : 1;
 460
 461	switch (ofs) {
 462	case CS42L42_VOL_DAC:
 463		uinfo->value.integer.min = CS42L42_HP_VOL_REAL_MIN;
 464		uinfo->value.integer.max = CS42L42_HP_VOL_REAL_MAX;
 465		break;
 466	case CS42L42_VOL_ADC:
 467		uinfo->value.integer.min = CS42L42_AMIC_VOL_REAL_MIN;
 468		uinfo->value.integer.max = CS42L42_AMIC_VOL_REAL_MAX;
 469		break;
 470	default:
 471		break;
 472	}
 473
 474	return 0;
 475}
 476
 477int cs42l42_volume_get(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl)
 478{
 479	struct hda_codec *codec = snd_kcontrol_chip(kctrl);
 480	struct cs8409_spec *spec = codec->spec;
 481	struct sub_codec *cs42l42 = spec->scodecs[get_amp_index(kctrl)];
 482	int chs = get_amp_channels(kctrl);
 483	unsigned int ofs = get_amp_offset(kctrl);
 484	long *valp = uctrl->value.integer.value;
 485
 486	switch (ofs) {
 487	case CS42L42_VOL_DAC:
 488		if (chs & BIT(0))
 489			*valp++ = cs42l42->vol[ofs];
 490		if (chs & BIT(1))
 491			*valp = cs42l42->vol[ofs+1];
 492		break;
 493	case CS42L42_VOL_ADC:
 494		if (chs & BIT(0))
 495			*valp = cs42l42->vol[ofs];
 496		break;
 497	default:
 498		break;
 499	}
 500
 501	return 0;
 502}
 503
 504static void cs42l42_mute(struct sub_codec *cs42l42, int vol_type,
 505	unsigned int chs, bool mute)
 506{
 507	if (mute) {
 508		if (vol_type == CS42L42_VOL_DAC) {
 509			if (chs & BIT(0))
 510				cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHA_VOL, 0x3f);
 511			if (chs & BIT(1))
 512				cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHB_VOL, 0x3f);
 513		} else if (vol_type == CS42L42_VOL_ADC) {
 514			if (chs & BIT(0))
 515				cs8409_i2c_write(cs42l42, CS42L42_ADC_VOLUME, 0x9f);
 516		}
 517	} else {
 518		if (vol_type == CS42L42_VOL_DAC) {
 519			if (chs & BIT(0))
 520				cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHA_VOL,
 521					-(cs42l42->vol[CS42L42_DAC_CH0_VOL_OFFSET])
 522					& CS42L42_MIXER_CH_VOL_MASK);
 523			if (chs & BIT(1))
 524				cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHB_VOL,
 525					-(cs42l42->vol[CS42L42_DAC_CH1_VOL_OFFSET])
 526					& CS42L42_MIXER_CH_VOL_MASK);
 527		} else if (vol_type == CS42L42_VOL_ADC) {
 528			if (chs & BIT(0))
 529				cs8409_i2c_write(cs42l42, CS42L42_ADC_VOLUME,
 530					cs42l42->vol[CS42L42_ADC_VOL_OFFSET]
 531					& CS42L42_REG_AMIC_VOL_MASK);
 532		}
 533	}
 534}
 535
 536int cs42l42_volume_put(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl)
 537{
 538	struct hda_codec *codec = snd_kcontrol_chip(kctrl);
 539	struct cs8409_spec *spec = codec->spec;
 540	struct sub_codec *cs42l42 = spec->scodecs[get_amp_index(kctrl)];
 541	int chs = get_amp_channels(kctrl);
 542	unsigned int ofs = get_amp_offset(kctrl);
 543	long *valp = uctrl->value.integer.value;
 544
 545	switch (ofs) {
 546	case CS42L42_VOL_DAC:
 547		if (chs & BIT(0))
 548			cs42l42->vol[ofs] = *valp;
 549		if (chs & BIT(1)) {
 550			valp++;
 551			cs42l42->vol[ofs + 1] = *valp;
 552		}
 553		if (spec->playback_started)
 554			cs42l42_mute(cs42l42, CS42L42_VOL_DAC, chs, false);
 555		break;
 556	case CS42L42_VOL_ADC:
 557		if (chs & BIT(0))
 558			cs42l42->vol[ofs] = *valp;
 559		if (spec->capture_started)
 560			cs42l42_mute(cs42l42, CS42L42_VOL_ADC, chs, false);
 561		break;
 562	default:
 563		break;
 564	}
 565
 566	return 0;
 567}
 568
 569static void cs42l42_playback_pcm_hook(struct hda_pcm_stream *hinfo,
 570				   struct hda_codec *codec,
 571				   struct snd_pcm_substream *substream,
 572				   int action)
 573{
 574	struct cs8409_spec *spec = codec->spec;
 575	struct sub_codec *cs42l42;
 576	int i;
 577	bool mute;
 578
 579	switch (action) {
 580	case HDA_GEN_PCM_ACT_PREPARE:
 581		mute = false;
 582		spec->playback_started = 1;
 583		break;
 584	case HDA_GEN_PCM_ACT_CLEANUP:
 585		mute = true;
 586		spec->playback_started = 0;
 587		break;
 588	default:
 589		return;
 590	}
 591
 592	for (i = 0; i < spec->num_scodecs; i++) {
 593		cs42l42 = spec->scodecs[i];
 594		cs42l42_mute(cs42l42, CS42L42_VOL_DAC, 0x3, mute);
 595	}
 596}
 597
 598static void cs42l42_capture_pcm_hook(struct hda_pcm_stream *hinfo,
 599				   struct hda_codec *codec,
 600				   struct snd_pcm_substream *substream,
 601				   int action)
 602{
 603	struct cs8409_spec *spec = codec->spec;
 604	struct sub_codec *cs42l42;
 605	int i;
 606	bool mute;
 607
 608	switch (action) {
 609	case HDA_GEN_PCM_ACT_PREPARE:
 610		mute = false;
 611		spec->capture_started = 1;
 612		break;
 613	case HDA_GEN_PCM_ACT_CLEANUP:
 614		mute = true;
 615		spec->capture_started = 0;
 616		break;
 617	default:
 618		return;
 619	}
 620
 621	for (i = 0; i < spec->num_scodecs; i++) {
 622		cs42l42 = spec->scodecs[i];
 623		cs42l42_mute(cs42l42, CS42L42_VOL_ADC, 0x3, mute);
 624	}
 625}
 626
 627/* Configure CS42L42 slave codec for jack autodetect */
 628static void cs42l42_enable_jack_detect(struct sub_codec *cs42l42)
 629{
 630	cs8409_i2c_write(cs42l42, CS42L42_HSBIAS_SC_AUTOCTL, cs42l42->hsbias_hiz);
 631	/* Clear WAKE# */
 632	cs8409_i2c_write(cs42l42, CS42L42_WAKE_CTL, 0x00C1);
 633	/* Wait ~2.5ms */
 634	usleep_range(2500, 3000);
 635	/* Set mode WAKE# output follows the combination logic directly */
 636	cs8409_i2c_write(cs42l42, CS42L42_WAKE_CTL, 0x00C0);
 637	/* Clear interrupts status */
 638	cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS);
 639	/* Enable interrupt */
 640	cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xF3);
 641}
 642
 643/* Enable and run CS42L42 slave codec jack auto detect */
 644static void cs42l42_run_jack_detect(struct sub_codec *cs42l42)
 645{
 646	/* Clear interrupts */
 647	cs8409_i2c_read(cs42l42, CS42L42_CODEC_STATUS);
 648	cs8409_i2c_read(cs42l42, CS42L42_DET_STATUS1);
 649	cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xFF);
 650	cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS);
 651
 652	cs8409_i2c_write(cs42l42, CS42L42_PWR_CTL2, 0x87);
 653	cs8409_i2c_write(cs42l42, CS42L42_DAC_CTL2, 0x86);
 654	cs8409_i2c_write(cs42l42, CS42L42_MISC_DET_CTL, 0x07);
 655	cs8409_i2c_write(cs42l42, CS42L42_CODEC_INT_MASK, 0xFD);
 656	cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0x80);
 657	/* Wait ~20ms*/
 658	usleep_range(20000, 25000);
 659	cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1, 0x77);
 660	cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0xc0);
 661}
 662
 663static int cs42l42_manual_hs_det(struct sub_codec *cs42l42)
 664{
 665	unsigned int hs_det_status;
 666	unsigned int hs_det_comp1;
 667	unsigned int hs_det_comp2;
 668	unsigned int hs_det_sw;
 669	unsigned int hs_type;
 670
 671	/* Set hs detect to manual, active mode */
 672	cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2,
 673			 (1 << CS42L42_HSDET_CTRL_SHIFT) |
 674			 (0 << CS42L42_HSDET_SET_SHIFT) |
 675			 (0 << CS42L42_HSBIAS_REF_SHIFT) |
 676			 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
 677
 678	/* Configure HS DET comparator reference levels. */
 679	cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1,
 680			 (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) |
 681			 (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT));
 682
 683	/* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */
 684	cs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1);
 685
 686	msleep(100);
 687
 688	hs_det_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS);
 689
 690	hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
 691			CS42L42_HSDET_COMP1_OUT_SHIFT;
 692	hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
 693			CS42L42_HSDET_COMP2_OUT_SHIFT;
 694
 695	/* Close the SW_HSB_HS3 switch for a Type 2 headset. */
 696	cs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2);
 697
 698	msleep(100);
 699
 700	hs_det_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS);
 701
 702	hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
 703			CS42L42_HSDET_COMP1_OUT_SHIFT) << 1;
 704	hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
 705			CS42L42_HSDET_COMP2_OUT_SHIFT) << 1;
 706
 707	/* Use Comparator 1 with 1.25V Threshold. */
 708	switch (hs_det_comp1) {
 709	case CS42L42_HSDET_COMP_TYPE1:
 710		hs_type = CS42L42_PLUG_CTIA;
 711		hs_det_sw = CS42L42_HSDET_SW_TYPE1;
 712		break;
 713	case CS42L42_HSDET_COMP_TYPE2:
 714		hs_type = CS42L42_PLUG_OMTP;
 715		hs_det_sw = CS42L42_HSDET_SW_TYPE2;
 716		break;
 717	default:
 718		/* Fallback to Comparator 2 with 1.75V Threshold. */
 719		switch (hs_det_comp2) {
 720		case CS42L42_HSDET_COMP_TYPE1:
 721			hs_type = CS42L42_PLUG_CTIA;
 722			hs_det_sw = CS42L42_HSDET_SW_TYPE1;
 723			break;
 724		case CS42L42_HSDET_COMP_TYPE2:
 725			hs_type = CS42L42_PLUG_OMTP;
 726			hs_det_sw = CS42L42_HSDET_SW_TYPE2;
 727			break;
 728		case CS42L42_HSDET_COMP_TYPE3:
 729			hs_type = CS42L42_PLUG_HEADPHONE;
 730			hs_det_sw = CS42L42_HSDET_SW_TYPE3;
 731			break;
 732		default:
 733			hs_type = CS42L42_PLUG_INVALID;
 734			hs_det_sw = CS42L42_HSDET_SW_TYPE4;
 735			break;
 736		}
 737	}
 738
 739	/* Set Switches */
 740	cs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, hs_det_sw);
 741
 742	/* Set HSDET mode to Manual—Disabled */
 743	cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2,
 744			 (0 << CS42L42_HSDET_CTRL_SHIFT) |
 745			 (0 << CS42L42_HSDET_SET_SHIFT) |
 746			 (0 << CS42L42_HSBIAS_REF_SHIFT) |
 747			 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
 748
 749	/* Configure HS DET comparator reference levels. */
 750	cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1,
 751			 (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) |
 752			 (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT));
 753
 754	return hs_type;
 755}
 756
 757static int cs42l42_handle_tip_sense(struct sub_codec *cs42l42, unsigned int reg_ts_status)
 758{
 759	int status_changed = 0;
 760
 761	/* TIP_SENSE INSERT/REMOVE */
 762	switch (reg_ts_status) {
 763	case CS42L42_TS_PLUG:
 764		if (cs42l42->no_type_dect) {
 765			status_changed = 1;
 766			cs42l42->hp_jack_in = 1;
 767			cs42l42->mic_jack_in = 0;
 768		} else {
 769			cs42l42_run_jack_detect(cs42l42);
 770		}
 771		break;
 772
 773	case CS42L42_TS_UNPLUG:
 774		status_changed = 1;
 775		cs42l42->hp_jack_in = 0;
 776		cs42l42->mic_jack_in = 0;
 777		break;
 778	default:
 779		/* jack in transition */
 780		break;
 781	}
 782
 783	codec_dbg(cs42l42->codec, "Tip Sense Detection: (%d)\n", reg_ts_status);
 784
 785	return status_changed;
 786}
 787
 788static int cs42l42_jack_unsol_event(struct sub_codec *cs42l42)
 789{
 790	int current_plug_status;
 791	int status_changed = 0;
 792	int reg_cdc_status;
 793	int reg_hs_status;
 794	int reg_ts_status;
 795	int type;
 796
 797	/* Read jack detect status registers */
 798	reg_cdc_status = cs8409_i2c_read(cs42l42, CS42L42_CODEC_STATUS);
 799	reg_hs_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS);
 800	reg_ts_status = cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS);
 801
 802	/* If status values are < 0, read error has occurred. */
 803	if (reg_cdc_status < 0 || reg_hs_status < 0 || reg_ts_status < 0)
 804		return -EIO;
 805
 806	current_plug_status = (reg_ts_status & (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK))
 807				>> CS42L42_TS_PLUG_SHIFT;
 808
 809	/* HSDET_AUTO_DONE */
 810	if (reg_cdc_status & CS42L42_HSDET_AUTO_DONE_MASK) {
 811
 812		/* Disable HSDET_AUTO_DONE */
 813		cs8409_i2c_write(cs42l42, CS42L42_CODEC_INT_MASK, 0xFF);
 814
 815		type = (reg_hs_status & CS42L42_HSDET_TYPE_MASK) >> CS42L42_HSDET_TYPE_SHIFT;
 816
 817		/* Configure the HSDET mode. */
 818		cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0x80);
 819
 820		if (cs42l42->no_type_dect) {
 821			status_changed = cs42l42_handle_tip_sense(cs42l42, current_plug_status);
 822		} else {
 823			if (type == CS42L42_PLUG_INVALID || type == CS42L42_PLUG_HEADPHONE) {
 824				codec_dbg(cs42l42->codec,
 825					  "Auto detect value not valid (%d), running manual det\n",
 826					  type);
 827				type = cs42l42_manual_hs_det(cs42l42);
 828			}
 829
 830			switch (type) {
 831			case CS42L42_PLUG_CTIA:
 832			case CS42L42_PLUG_OMTP:
 833				status_changed = 1;
 834				cs42l42->hp_jack_in = 1;
 835				cs42l42->mic_jack_in = 1;
 836				break;
 837			case CS42L42_PLUG_HEADPHONE:
 838				status_changed = 1;
 839				cs42l42->hp_jack_in = 1;
 840				cs42l42->mic_jack_in = 0;
 841				break;
 842			default:
 843				status_changed = 1;
 844				cs42l42->hp_jack_in = 0;
 845				cs42l42->mic_jack_in = 0;
 846				break;
 847			}
 848			codec_dbg(cs42l42->codec, "Detection done (%d)\n", type);
 849		}
 850
 851		/* Enable the HPOUT ground clamp and configure the HP pull-down */
 852		cs8409_i2c_write(cs42l42, CS42L42_DAC_CTL2, 0x02);
 853		/* Re-Enable Tip Sense Interrupt */
 854		cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xF3);
 855	} else {
 856		status_changed = cs42l42_handle_tip_sense(cs42l42, current_plug_status);
 857	}
 858
 859	return status_changed;
 860}
 861
 862static void cs42l42_resume(struct sub_codec *cs42l42)
 863{
 864	struct hda_codec *codec = cs42l42->codec;
 865	struct cs8409_spec *spec = codec->spec;
 866	struct cs8409_i2c_param irq_regs[] = {
 867		{ CS42L42_CODEC_STATUS, 0x00 },
 868		{ CS42L42_DET_INT_STATUS1, 0x00 },
 869		{ CS42L42_DET_INT_STATUS2, 0x00 },
 870		{ CS42L42_TSRS_PLUG_STATUS, 0x00 },
 871	};
 872	unsigned int fsv;
 873
 874	/* Bring CS42L42 out of Reset */
 875	spec->gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0);
 876	spec->gpio_data |= cs42l42->reset_gpio;
 877	snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data);
 878	usleep_range(10000, 15000);
 879
 880	cs42l42->suspended = 0;
 881
 882	/* Initialize CS42L42 companion codec */
 883	cs8409_i2c_bulk_write(cs42l42, cs42l42->init_seq, cs42l42->init_seq_num);
 884
 885	/* Clear interrupts, by reading interrupt status registers */
 886	cs8409_i2c_bulk_read(cs42l42, irq_regs, ARRAY_SIZE(irq_regs));
 887
 888	fsv = cs8409_i2c_read(cs42l42, CS42L42_HP_CTL);
 889	if (cs42l42->full_scale_vol) {
 890		// Set the full scale volume bit
 891		fsv |= CS42L42_FULL_SCALE_VOL_MASK;
 892		cs8409_i2c_write(cs42l42, CS42L42_HP_CTL, fsv);
 893	}
 894	// Unmute analog channels A and B
 895	fsv = (fsv & ~CS42L42_ANA_MUTE_AB);
 896	cs8409_i2c_write(cs42l42, CS42L42_HP_CTL, fsv);
 897
 898	/* we have to explicitly allow unsol event handling even during the
 899	 * resume phase so that the jack event is processed properly
 900	 */
 901	snd_hda_codec_allow_unsol_events(cs42l42->codec);
 902
 903	cs42l42_enable_jack_detect(cs42l42);
 904}
 905
 906static void cs42l42_suspend(struct sub_codec *cs42l42)
 907{
 908	struct hda_codec *codec = cs42l42->codec;
 909	struct cs8409_spec *spec = codec->spec;
 910	int reg_cdc_status = 0;
 911	const struct cs8409_i2c_param cs42l42_pwr_down_seq[] = {
 912		{ CS42L42_DAC_CTL2, 0x02 },
 913		{ CS42L42_HS_CLAMP_DISABLE, 0x00 },
 914		{ CS42L42_MIXER_CHA_VOL, 0x3F },
 915		{ CS42L42_MIXER_ADC_VOL, 0x3F },
 916		{ CS42L42_MIXER_CHB_VOL, 0x3F },
 917		{ CS42L42_HP_CTL, 0x0D },
 918		{ CS42L42_ASP_RX_DAI0_EN, 0x00 },
 919		{ CS42L42_ASP_CLK_CFG, 0x00 },
 920		{ CS42L42_PWR_CTL1, 0xFE },
 921		{ CS42L42_PWR_CTL2, 0x8C },
 922		{ CS42L42_PWR_CTL1, 0xFF },
 923	};
 924
 925	cs8409_i2c_bulk_write(cs42l42, cs42l42_pwr_down_seq, ARRAY_SIZE(cs42l42_pwr_down_seq));
 926
 927	if (read_poll_timeout(cs8409_i2c_read, reg_cdc_status,
 928			(reg_cdc_status & 0x1), CS42L42_PDN_SLEEP_US, CS42L42_PDN_TIMEOUT_US,
 929			true, cs42l42, CS42L42_CODEC_STATUS) < 0)
 930		codec_warn(codec, "Timeout waiting for PDN_DONE for CS42L42\n");
 931
 932	/* Power down CS42L42 ASP/EQ/MIX/HP */
 933	cs8409_i2c_write(cs42l42, CS42L42_PWR_CTL2, 0x9C);
 934	cs42l42->suspended = 1;
 935	cs42l42->last_page = 0;
 936	cs42l42->hp_jack_in = 0;
 937	cs42l42->mic_jack_in = 0;
 938
 939	/* Put CS42L42 into Reset */
 940	spec->gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0);
 941	spec->gpio_data &= ~cs42l42->reset_gpio;
 942	snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data);
 943}
 944
 945static void cs8409_remove(struct hda_codec *codec)
 946{
 947	struct cs8409_spec *spec = codec->spec;
 948
 949	/* Cancel i2c clock disable timer, and disable clock if left enabled */
 950	cancel_delayed_work_sync(&spec->i2c_clk_work);
 951	cs8409_disable_i2c_clock(codec);
 952
 953	snd_hda_gen_remove(codec);
 954}
 955
 956/******************************************************************************
 957 *                   BULLSEYE / WARLOCK / CYBORG Specific Functions
 958 *                               CS8409/CS42L42
 959 ******************************************************************************/
 960
 961/*
 962 * In the case of CS8409 we do not have unsolicited events from NID's 0x24
 963 * and 0x34 where hs mic and hp are connected. Companion codec CS42L42 will
 964 * generate interrupt via gpio 4 to notify jack events. We have to overwrite
 965 * generic snd_hda_jack_unsol_event(), read CS42L42 jack detect status registers
 966 * and then notify status via generic snd_hda_jack_unsol_event() call.
 967 */
 968static void cs8409_cs42l42_jack_unsol_event(struct hda_codec *codec, unsigned int res)
 969{
 970	struct cs8409_spec *spec = codec->spec;
 971	struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
 972	struct hda_jack_tbl *jk;
 973
 974	/* jack_unsol_event() will be called every time gpio line changing state.
 975	 * In this case gpio4 line goes up as a result of reading interrupt status
 976	 * registers in previous cs8409_jack_unsol_event() call.
 977	 * We don't need to handle this event, ignoring...
 978	 */
 979	if (res & cs42l42->irq_mask)
 980		return;
 981
 982	if (cs42l42_jack_unsol_event(cs42l42)) {
 983		snd_hda_set_pin_ctl(codec, CS8409_CS42L42_SPK_PIN_NID,
 984				    cs42l42->hp_jack_in ? 0 : PIN_OUT);
 985		/* Report jack*/
 986		jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_HP_PIN_NID, 0);
 987		if (jk)
 988			snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
 989							AC_UNSOL_RES_TAG);
 990		/* Report jack*/
 991		jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_AMIC_PIN_NID, 0);
 992		if (jk)
 993			snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
 994							 AC_UNSOL_RES_TAG);
 995	}
 996}
 997
 998static void cs8409_unsol_event(struct hda_codec *codec, unsigned int res)
 999{
1000	struct cs8409_spec *spec = codec->spec;
1001
1002	if (spec->unsol_event)
1003		spec->unsol_event(codec, res);
1004	else
1005		cs8409_cs42l42_jack_unsol_event(codec, res);
1006}
1007
1008/* Manage PDREF, when transition to D3hot */
1009static int cs8409_cs42l42_suspend(struct hda_codec *codec)
1010{
1011	struct cs8409_spec *spec = codec->spec;
1012	int i;
1013
1014	spec->init_done = 0;
1015
1016	cs8409_enable_ur(codec, 0);
1017
1018	for (i = 0; i < spec->num_scodecs; i++)
1019		cs42l42_suspend(spec->scodecs[i]);
1020
1021	/* Cancel i2c clock disable timer, and disable clock if left enabled */
1022	cancel_delayed_work_sync(&spec->i2c_clk_work);
1023	cs8409_disable_i2c_clock(codec);
1024
1025	snd_hda_shutup_pins(codec);
1026
1027	return 0;
1028}
1029
1030/* Vendor specific HW configuration
1031 * PLL, ASP, I2C, SPI, GPIOs, DMIC etc...
1032 */
1033static void cs8409_cs42l42_hw_init(struct hda_codec *codec)
1034{
1035	const struct cs8409_cir_param *seq = cs8409_cs42l42_hw_cfg;
1036	const struct cs8409_cir_param *seq_bullseye = cs8409_cs42l42_bullseye_atn;
1037	struct cs8409_spec *spec = codec->spec;
1038	struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
1039
1040	if (spec->gpio_mask) {
1041		snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_MASK,
1042			spec->gpio_mask);
1043		snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DIRECTION,
1044			spec->gpio_dir);
1045		snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA,
1046			spec->gpio_data);
1047	}
1048
1049	for (; seq->nid; seq++)
1050		cs8409_vendor_coef_set(codec, seq->cir, seq->coeff);
1051
1052	if (codec->fixup_id == CS8409_BULLSEYE) {
1053		for (; seq_bullseye->nid; seq_bullseye++)
1054			cs8409_vendor_coef_set(codec, seq_bullseye->cir, seq_bullseye->coeff);
1055	}
1056
1057	switch (codec->fixup_id) {
1058	case CS8409_CYBORG:
1059	case CS8409_WARLOCK_MLK_DUAL_MIC:
1060		/* DMIC1_MO=00b, DMIC1/2_SR=1 */
1061		cs8409_vendor_coef_set(codec, CS8409_DMIC_CFG, 0x0003);
1062		break;
1063	case CS8409_ODIN:
1064		/* ASP1/2_xxx_EN=1, ASP1/2_MCLK_EN=0, DMIC1_SCL_EN=0 */
1065		cs8409_vendor_coef_set(codec, CS8409_PAD_CFG_SLW_RATE_CTRL, 0xfc00);
1066		break;
1067	default:
1068		break;
1069	}
1070
1071	cs42l42_resume(cs42l42);
1072
1073	/* Enable Unsolicited Response */
1074	cs8409_enable_ur(codec, 1);
1075}
1076
1077static int cs8409_cs42l42_exec_verb(struct hdac_device *dev, unsigned int cmd, unsigned int flags,
1078				    unsigned int *res)
1079{
1080	struct hda_codec *codec = container_of(dev, struct hda_codec, core);
1081	struct cs8409_spec *spec = codec->spec;
1082	struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
1083
1084	unsigned int nid = ((cmd >> 20) & 0x07f);
1085	unsigned int verb = ((cmd >> 8) & 0x0fff);
1086
1087	/* CS8409 pins have no AC_PINSENSE_PRESENCE
1088	 * capabilities. We have to intercept 2 calls for pins 0x24 and 0x34
1089	 * and return correct pin sense values for read_pin_sense() call from
1090	 * hda_jack based on CS42L42 jack detect status.
1091	 */
1092	switch (nid) {
1093	case CS8409_CS42L42_HP_PIN_NID:
1094		if (verb == AC_VERB_GET_PIN_SENSE) {
1095			*res = (cs42l42->hp_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1096			return 0;
1097		}
1098		break;
1099	case CS8409_CS42L42_AMIC_PIN_NID:
1100		if (verb == AC_VERB_GET_PIN_SENSE) {
1101			*res = (cs42l42->mic_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1102			return 0;
1103		}
1104		break;
1105	default:
1106		break;
1107	}
1108
1109	return spec->exec_verb(dev, cmd, flags, res);
1110}
1111
1112void cs8409_cs42l42_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action)
1113{
1114	struct cs8409_spec *spec = codec->spec;
1115
1116	switch (action) {
1117	case HDA_FIXUP_ACT_PRE_PROBE:
1118		snd_hda_add_verbs(codec, cs8409_cs42l42_init_verbs);
1119		/* verb exec op override */
1120		spec->exec_verb = codec->core.exec_verb;
1121		codec->core.exec_verb = cs8409_cs42l42_exec_verb;
1122
1123		spec->scodecs[CS8409_CODEC0] = &cs8409_cs42l42_codec;
1124		spec->num_scodecs = 1;
1125		spec->scodecs[CS8409_CODEC0]->codec = codec;
1126
1127		spec->gen.suppress_auto_mute = 1;
1128		spec->gen.no_primary_hp = 1;
1129		spec->gen.suppress_vmaster = 1;
1130
1131		spec->speaker_pdn_gpio = 0;
1132
1133		/* GPIO 5 out, 3,4 in */
1134		spec->gpio_dir = spec->scodecs[CS8409_CODEC0]->reset_gpio;
1135		spec->gpio_data = 0;
1136		spec->gpio_mask = 0x03f;
1137
1138		/* Basic initial sequence for specific hw configuration */
1139		snd_hda_sequence_write(codec, cs8409_cs42l42_init_verbs);
1140
1141		cs8409_fix_caps(codec, CS8409_CS42L42_HP_PIN_NID);
1142		cs8409_fix_caps(codec, CS8409_CS42L42_AMIC_PIN_NID);
1143
1144		spec->scodecs[CS8409_CODEC0]->hsbias_hiz = 0x0020;
1145
1146		switch (codec->fixup_id) {
1147		case CS8409_CYBORG:
1148			spec->scodecs[CS8409_CODEC0]->full_scale_vol =
1149				CS42L42_FULL_SCALE_VOL_MINUS6DB;
1150			spec->speaker_pdn_gpio = CS8409_CYBORG_SPEAKER_PDN;
1151			break;
1152		case CS8409_ODIN:
1153			spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_0DB;
1154			spec->speaker_pdn_gpio = CS8409_CYBORG_SPEAKER_PDN;
1155			break;
1156		case CS8409_WARLOCK_MLK:
1157		case CS8409_WARLOCK_MLK_DUAL_MIC:
1158			spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_0DB;
1159			spec->speaker_pdn_gpio = CS8409_WARLOCK_SPEAKER_PDN;
1160			break;
1161		default:
1162			spec->scodecs[CS8409_CODEC0]->full_scale_vol =
1163				CS42L42_FULL_SCALE_VOL_MINUS6DB;
1164			spec->speaker_pdn_gpio = CS8409_WARLOCK_SPEAKER_PDN;
1165			break;
1166		}
1167
1168		if (spec->speaker_pdn_gpio > 0) {
1169			spec->gpio_dir |= spec->speaker_pdn_gpio;
1170			spec->gpio_data |= spec->speaker_pdn_gpio;
1171		}
1172
1173		break;
1174	case HDA_FIXUP_ACT_PROBE:
1175		/* Fix Sample Rate to 48kHz */
1176		spec->gen.stream_analog_playback = &cs42l42_48k_pcm_analog_playback;
1177		spec->gen.stream_analog_capture = &cs42l42_48k_pcm_analog_capture;
1178		/* add hooks */
1179		spec->gen.pcm_playback_hook = cs42l42_playback_pcm_hook;
1180		spec->gen.pcm_capture_hook = cs42l42_capture_pcm_hook;
1181		if (codec->fixup_id != CS8409_ODIN)
1182			/* Set initial DMIC volume to -26 dB */
1183			snd_hda_codec_amp_init_stereo(codec, CS8409_CS42L42_DMIC_ADC_PIN_NID,
1184						      HDA_INPUT, 0, 0xff, 0x19);
1185		snd_hda_gen_add_kctl(&spec->gen, "Headphone Playback Volume",
1186				&cs42l42_dac_volume_mixer);
1187		snd_hda_gen_add_kctl(&spec->gen, "Mic Capture Volume",
1188				&cs42l42_adc_volume_mixer);
1189		if (spec->speaker_pdn_gpio > 0)
1190			snd_hda_gen_add_kctl(&spec->gen, "Speaker Playback Switch",
1191					     &cs8409_spk_sw_ctrl);
1192		/* Disable Unsolicited Response during boot */
1193		cs8409_enable_ur(codec, 0);
1194		snd_hda_codec_set_name(codec, "CS8409/CS42L42");
1195		break;
1196	case HDA_FIXUP_ACT_INIT:
1197		cs8409_cs42l42_hw_init(codec);
1198		spec->init_done = 1;
1199		if (spec->init_done && spec->build_ctrl_done
1200			&& !spec->scodecs[CS8409_CODEC0]->hp_jack_in)
1201			cs42l42_run_jack_detect(spec->scodecs[CS8409_CODEC0]);
1202		break;
1203	case HDA_FIXUP_ACT_BUILD:
1204		spec->build_ctrl_done = 1;
1205		/* Run jack auto detect first time on boot
1206		 * after controls have been added, to check if jack has
1207		 * been already plugged in.
1208		 * Run immediately after init.
1209		 */
1210		if (spec->init_done && spec->build_ctrl_done
1211			&& !spec->scodecs[CS8409_CODEC0]->hp_jack_in)
1212			cs42l42_run_jack_detect(spec->scodecs[CS8409_CODEC0]);
1213		break;
1214	default:
1215		break;
1216	}
1217}
1218
1219/******************************************************************************
1220 *                          Dolphin Specific Functions
1221 *                               CS8409/ 2 X CS42L42
1222 ******************************************************************************/
1223
1224/*
1225 * In the case of CS8409 we do not have unsolicited events when
1226 * hs mic and hp are connected. Companion codec CS42L42 will
1227 * generate interrupt via irq_mask to notify jack events. We have to overwrite
1228 * generic snd_hda_jack_unsol_event(), read CS42L42 jack detect status registers
1229 * and then notify status via generic snd_hda_jack_unsol_event() call.
1230 */
1231static void dolphin_jack_unsol_event(struct hda_codec *codec, unsigned int res)
1232{
1233	struct cs8409_spec *spec = codec->spec;
1234	struct sub_codec *cs42l42;
1235	struct hda_jack_tbl *jk;
1236
1237	cs42l42 = spec->scodecs[CS8409_CODEC0];
1238	if (!cs42l42->suspended && (~res & cs42l42->irq_mask) &&
1239	    cs42l42_jack_unsol_event(cs42l42)) {
1240		jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_HP_PIN_NID, 0);
1241		if (jk)
1242			snd_hda_jack_unsol_event(codec,
1243						 (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1244						  AC_UNSOL_RES_TAG);
1245
1246		jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_AMIC_PIN_NID, 0);
1247		if (jk)
1248			snd_hda_jack_unsol_event(codec,
1249						 (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1250						  AC_UNSOL_RES_TAG);
1251	}
1252
1253	cs42l42 = spec->scodecs[CS8409_CODEC1];
1254	if (!cs42l42->suspended && (~res & cs42l42->irq_mask) &&
1255	    cs42l42_jack_unsol_event(cs42l42)) {
1256		jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_LO_PIN_NID, 0);
1257		if (jk)
1258			snd_hda_jack_unsol_event(codec,
1259						 (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1260						  AC_UNSOL_RES_TAG);
1261	}
1262}
1263
1264/* Vendor specific HW configuration
1265 * PLL, ASP, I2C, SPI, GPIOs, DMIC etc...
1266 */
1267static void dolphin_hw_init(struct hda_codec *codec)
1268{
1269	const struct cs8409_cir_param *seq = dolphin_hw_cfg;
1270	struct cs8409_spec *spec = codec->spec;
1271	struct sub_codec *cs42l42;
1272	int i;
1273
1274	if (spec->gpio_mask) {
1275		snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_MASK,
1276				    spec->gpio_mask);
1277		snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DIRECTION,
1278				    spec->gpio_dir);
1279		snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA,
1280				    spec->gpio_data);
1281	}
1282
1283	for (; seq->nid; seq++)
1284		cs8409_vendor_coef_set(codec, seq->cir, seq->coeff);
1285
1286	for (i = 0; i < spec->num_scodecs; i++) {
1287		cs42l42 = spec->scodecs[i];
1288		cs42l42_resume(cs42l42);
1289	}
1290
1291	/* Enable Unsolicited Response */
1292	cs8409_enable_ur(codec, 1);
1293}
1294
1295static int dolphin_exec_verb(struct hdac_device *dev, unsigned int cmd, unsigned int flags,
1296			     unsigned int *res)
1297{
1298	struct hda_codec *codec = container_of(dev, struct hda_codec, core);
1299	struct cs8409_spec *spec = codec->spec;
1300	struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
1301
1302	unsigned int nid = ((cmd >> 20) & 0x07f);
1303	unsigned int verb = ((cmd >> 8) & 0x0fff);
1304
1305	/* CS8409 pins have no AC_PINSENSE_PRESENCE
1306	 * capabilities. We have to intercept calls for CS42L42 pins
1307	 * and return correct pin sense values for read_pin_sense() call from
1308	 * hda_jack based on CS42L42 jack detect status.
1309	 */
1310	switch (nid) {
1311	case DOLPHIN_HP_PIN_NID:
1312	case DOLPHIN_LO_PIN_NID:
1313		if (nid == DOLPHIN_LO_PIN_NID)
1314			cs42l42 = spec->scodecs[CS8409_CODEC1];
1315		if (verb == AC_VERB_GET_PIN_SENSE) {
1316			*res = (cs42l42->hp_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1317			return 0;
1318		}
1319		break;
1320	case DOLPHIN_AMIC_PIN_NID:
1321		if (verb == AC_VERB_GET_PIN_SENSE) {
1322			*res = (cs42l42->mic_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1323			return 0;
1324		}
1325		break;
1326	default:
1327		break;
1328	}
1329
1330	return spec->exec_verb(dev, cmd, flags, res);
1331}
1332
1333void dolphin_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action)
1334{
1335	struct cs8409_spec *spec = codec->spec;
1336	struct snd_kcontrol_new *kctrl;
1337	int i;
1338
1339	switch (action) {
1340	case HDA_FIXUP_ACT_PRE_PROBE:
1341		snd_hda_add_verbs(codec, dolphin_init_verbs);
1342		/* verb exec op override */
1343		spec->exec_verb = codec->core.exec_verb;
1344		codec->core.exec_verb = dolphin_exec_verb;
1345
1346		spec->scodecs[CS8409_CODEC0] = &dolphin_cs42l42_0;
1347		spec->scodecs[CS8409_CODEC0]->codec = codec;
1348		spec->scodecs[CS8409_CODEC1] = &dolphin_cs42l42_1;
1349		spec->scodecs[CS8409_CODEC1]->codec = codec;
1350		spec->num_scodecs = 2;
1351		spec->gen.suppress_vmaster = 1;
1352
1353		spec->unsol_event = dolphin_jack_unsol_event;
1354
1355		/* GPIO 1,5 out, 0,4 in */
1356		spec->gpio_dir = spec->scodecs[CS8409_CODEC0]->reset_gpio |
1357				 spec->scodecs[CS8409_CODEC1]->reset_gpio;
1358		spec->gpio_data = 0;
1359		spec->gpio_mask = 0x03f;
1360
1361		/* Basic initial sequence for specific hw configuration */
1362		snd_hda_sequence_write(codec, dolphin_init_verbs);
1363
1364		snd_hda_jack_add_kctl(codec, DOLPHIN_LO_PIN_NID, "Line Out", true,
1365				      SND_JACK_HEADPHONE, NULL);
1366
1367		snd_hda_jack_add_kctl(codec, DOLPHIN_AMIC_PIN_NID, "Microphone", true,
1368				      SND_JACK_MICROPHONE, NULL);
1369
1370		cs8409_fix_caps(codec, DOLPHIN_HP_PIN_NID);
1371		cs8409_fix_caps(codec, DOLPHIN_LO_PIN_NID);
1372		cs8409_fix_caps(codec, DOLPHIN_AMIC_PIN_NID);
1373
1374		spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_MINUS6DB;
1375		spec->scodecs[CS8409_CODEC1]->full_scale_vol = CS42L42_FULL_SCALE_VOL_MINUS6DB;
1376
1377		break;
1378	case HDA_FIXUP_ACT_PROBE:
1379		/* Fix Sample Rate to 48kHz */
1380		spec->gen.stream_analog_playback = &cs42l42_48k_pcm_analog_playback;
1381		spec->gen.stream_analog_capture = &cs42l42_48k_pcm_analog_capture;
1382		/* add hooks */
1383		spec->gen.pcm_playback_hook = cs42l42_playback_pcm_hook;
1384		spec->gen.pcm_capture_hook = cs42l42_capture_pcm_hook;
1385		snd_hda_gen_add_kctl(&spec->gen, "Headphone Playback Volume",
1386				     &cs42l42_dac_volume_mixer);
1387		snd_hda_gen_add_kctl(&spec->gen, "Mic Capture Volume", &cs42l42_adc_volume_mixer);
1388		kctrl = snd_hda_gen_add_kctl(&spec->gen, "Line Out Playback Volume",
1389					     &cs42l42_dac_volume_mixer);
1390		/* Update Line Out kcontrol template */
1391		if (kctrl)
1392			kctrl->private_value = HDA_COMPOSE_AMP_VAL_OFS(DOLPHIN_HP_PIN_NID, 3, CS8409_CODEC1,
1393					       HDA_OUTPUT, CS42L42_VOL_DAC) | HDA_AMP_VAL_MIN_MUTE;
1394		cs8409_enable_ur(codec, 0);
1395		snd_hda_codec_set_name(codec, "CS8409/CS42L42");
1396		break;
1397	case HDA_FIXUP_ACT_INIT:
1398		dolphin_hw_init(codec);
1399		spec->init_done = 1;
1400		if (spec->init_done && spec->build_ctrl_done) {
1401			for (i = 0; i < spec->num_scodecs; i++) {
1402				if (!spec->scodecs[i]->hp_jack_in)
1403					cs42l42_run_jack_detect(spec->scodecs[i]);
1404			}
1405		}
1406		break;
1407	case HDA_FIXUP_ACT_BUILD:
1408		spec->build_ctrl_done = 1;
1409		/* Run jack auto detect first time on boot
1410		 * after controls have been added, to check if jack has
1411		 * been already plugged in.
1412		 * Run immediately after init.
1413		 */
1414		if (spec->init_done && spec->build_ctrl_done) {
1415			for (i = 0; i < spec->num_scodecs; i++) {
1416				if (!spec->scodecs[i]->hp_jack_in)
1417					cs42l42_run_jack_detect(spec->scodecs[i]);
1418			}
1419		}
1420		break;
1421	default:
1422		break;
1423	}
1424}
1425
1426static int cs8409_probe(struct hda_codec *codec, const struct hda_device_id *id)
1427{
1428	int err;
1429
1430	if (!cs8409_alloc_spec(codec))
1431		return -ENOMEM;
1432
1433	snd_hda_pick_fixup(codec, cs8409_models, cs8409_fixup_tbl, cs8409_fixups);
1434
1435	codec_dbg(codec, "Picked ID=%d, VID=%08x, DEV=%08x\n", codec->fixup_id,
1436			 codec->bus->pci->subsystem_vendor,
1437			 codec->bus->pci->subsystem_device);
1438
1439	snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE);
1440
1441	err = cs8409_parse_auto_config(codec);
1442	if (err < 0) {
1443		cs8409_remove(codec);
1444		return err;
1445	}
1446
1447	snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE);
1448	return 0;
1449}
1450
1451static const struct hda_codec_ops cs8409_codec_ops = {
1452	.probe = cs8409_probe,
1453	.remove = cs8409_remove,
1454	.build_controls = cs8409_build_controls,
1455	.build_pcms = snd_hda_gen_build_pcms,
1456	.init = cs8409_init,
1457	.unsol_event = cs8409_unsol_event,
1458	.suspend = cs8409_cs42l42_suspend,
1459	.stream_pm = snd_hda_gen_stream_pm,
1460};
1461
1462static const struct hda_device_id snd_hda_id_cs8409[] = {
1463	HDA_CODEC_ID(0x10138409, "CS8409"),
1464	{} /* terminator */
1465};
1466MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_cs8409);
1467
1468static struct hda_codec_driver cs8409_driver = {
1469	.id = snd_hda_id_cs8409,
1470	.ops = &cs8409_codec_ops,
1471};
1472module_hda_codec_driver(cs8409_driver);
1473
1474MODULE_LICENSE("GPL");
1475MODULE_DESCRIPTION("Cirrus Logic HDA bridge");