opl3_lib.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
  4 *                   Hannu Savolainen 1993-1996,
  5 *                   Rob Hooft
  6 *                   
  7 *  Routines for control of AdLib FM cards (OPL2/OPL3/OPL4 chips)
  8 *
  9 *  Most if code is ported from OSS/Lite.
 10 */
 11
 12#include <sound/opl3.h>
 13#include <linux/io.h>
 14#include <linux/delay.h>
 15#include <linux/module.h>
 16#include <linux/init.h>
 17#include <linux/slab.h>
 18#include <linux/ioport.h>
 19#include <sound/minors.h>
 20#include "opl3_voice.h"
 21
 22MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Hannu Savolainen 1993-1996, Rob Hooft");
 23MODULE_DESCRIPTION("Routines for control of AdLib FM cards (OPL2/OPL3/OPL4 chips)");
 24MODULE_LICENSE("GPL");
 25
 26static void snd_opl2_command(struct snd_opl3 * opl3, unsigned short cmd, unsigned char val)
 27{
 28	unsigned long port;
 29
 30	/*
 31	 * The original 2-OP synth requires a quite long delay
 32	 * after writing to a register.
 33	 */
 34
 35	port = (cmd & OPL3_RIGHT) ? opl3->r_port : opl3->l_port;
 36
 37	guard(spinlock_irqsave)(&opl3->reg_lock);
 38
 39	outb((unsigned char) cmd, port);
 40	udelay(10);
 41
 42	outb((unsigned char) val, port + 1);
 43	udelay(30);
 44}
 45
 46static void snd_opl3_command(struct snd_opl3 * opl3, unsigned short cmd, unsigned char val)
 47{
 48	unsigned long port;
 49
 50	/*
 51	 * The OPL-3 survives with just two INBs
 52	 * after writing to a register.
 53	 */
 54
 55	port = (cmd & OPL3_RIGHT) ? opl3->r_port : opl3->l_port;
 56
 57	guard(spinlock_irqsave)(&opl3->reg_lock);
 58
 59	outb((unsigned char) cmd, port);
 60	inb(opl3->l_port);
 61	inb(opl3->l_port);
 62
 63	outb((unsigned char) val, port + 1);
 64	inb(opl3->l_port);
 65	inb(opl3->l_port);
 66}
 67
 68static int snd_opl3_detect(struct snd_opl3 * opl3)
 69{
 70	/*
 71	 * This function returns 1 if the FM chip is present at the given I/O port
 72	 * The detection algorithm plays with the timer built in the FM chip and
 73	 * looks for a change in the status register.
 74	 *
 75	 * Note! The timers of the FM chip are not connected to AdLib (and compatible)
 76	 * boards.
 77	 *
 78	 * Note2! The chip is initialized if detected.
 79	 */
 80
 81	unsigned char stat1, stat2, signature;
 82
 83	/* Reset timers 1 and 2 */
 84	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, OPL3_TIMER1_MASK | OPL3_TIMER2_MASK);
 85	/* Reset the IRQ of the FM chip */
 86	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, OPL3_IRQ_RESET);
 87	signature = stat1 = inb(opl3->l_port);	/* Status register */
 88	if ((stat1 & 0xe0) != 0x00) {	/* Should be 0x00 */
 89		dev_dbg(opl3->card->dev, "OPL3: stat1 = 0x%x\n", stat1);
 90		return -ENODEV;
 91	}
 92	/* Set timer1 to 0xff */
 93	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER1, 0xff);
 94	/* Unmask and start timer 1 */
 95	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, OPL3_TIMER2_MASK | OPL3_TIMER1_START);
 96	/* Now we have to delay at least 80us */
 97	udelay(200);
 98	/* Read status after timers have expired */
 99	stat2 = inb(opl3->l_port);
100	/* Stop the timers */
101	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, OPL3_TIMER1_MASK | OPL3_TIMER2_MASK);
102	/* Reset the IRQ of the FM chip */
103	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, OPL3_IRQ_RESET);
104	if ((stat2 & 0xe0) != 0xc0) {	/* There is no YM3812 */
105		dev_dbg(opl3->card->dev, "OPL3: stat2 = 0x%x\n", stat2);
106		return -ENODEV;
107	}
108
109	/* If the toplevel code knows exactly the type of chip, don't try
110	   to detect it. */
111	if (opl3->hardware != OPL3_HW_AUTO)
112		return 0;
113
114	/* There is a FM chip on this address. Detect the type (OPL2 to OPL4) */
115	if (signature == 0x06) {	/* OPL2 */
116		opl3->hardware = OPL3_HW_OPL2;
117	} else {
118		/*
119		 * If we had an OPL4 chip, opl3->hardware would have been set
120		 * by the OPL4 driver; so we can assume OPL3 here.
121		 */
122		if (snd_BUG_ON(!opl3->r_port))
123			return -ENODEV;
124		opl3->hardware = OPL3_HW_OPL3;
125	}
126	return 0;
127}
128
129/*
130 *  AdLib timers
131 */
132
133/*
134 *  Timer 1 - 80us
135 */
136
137static int snd_opl3_timer1_start(struct snd_timer * timer)
138{
139	unsigned char tmp;
140	unsigned int ticks;
141	struct snd_opl3 *opl3;
142
143	opl3 = snd_timer_chip(timer);
144	guard(spinlock_irqsave)(&opl3->timer_lock);
145	ticks = timer->sticks;
146	tmp = (opl3->timer_enable | OPL3_TIMER1_START) & ~OPL3_TIMER1_MASK;
147	opl3->timer_enable = tmp;
148	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER1, 256 - ticks);	/* timer 1 count */
149	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, tmp);	/* enable timer 1 IRQ */
150	return 0;
151}
152
153static int snd_opl3_timer1_stop(struct snd_timer * timer)
154{
155	unsigned char tmp;
156	struct snd_opl3 *opl3;
157
158	opl3 = snd_timer_chip(timer);
159	guard(spinlock_irqsave)(&opl3->timer_lock);
160	tmp = (opl3->timer_enable | OPL3_TIMER1_MASK) & ~OPL3_TIMER1_START;
161	opl3->timer_enable = tmp;
162	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, tmp);	/* disable timer #1 */
163	return 0;
164}
165
166/*
167 *  Timer 2 - 320us
168 */
169
170static int snd_opl3_timer2_start(struct snd_timer * timer)
171{
172	unsigned char tmp;
173	unsigned int ticks;
174	struct snd_opl3 *opl3;
175
176	opl3 = snd_timer_chip(timer);
177	guard(spinlock_irqsave)(&opl3->timer_lock);
178	ticks = timer->sticks;
179	tmp = (opl3->timer_enable | OPL3_TIMER2_START) & ~OPL3_TIMER2_MASK;
180	opl3->timer_enable = tmp;
181	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER2, 256 - ticks);	/* timer 1 count */
182	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, tmp);	/* enable timer 1 IRQ */
183	return 0;
184}
185
186static int snd_opl3_timer2_stop(struct snd_timer * timer)
187{
188	unsigned char tmp;
189	struct snd_opl3 *opl3;
190
191	opl3 = snd_timer_chip(timer);
192	guard(spinlock_irqsave)(&opl3->timer_lock);
193	tmp = (opl3->timer_enable | OPL3_TIMER2_MASK) & ~OPL3_TIMER2_START;
194	opl3->timer_enable = tmp;
195	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, tmp);	/* disable timer #1 */
196	return 0;
197}
198
199/*
200
201 */
202
203static const struct snd_timer_hardware snd_opl3_timer1 =
204{
205	.flags =	SNDRV_TIMER_HW_STOP,
206	.resolution =	80000,
207	.ticks =	256,
208	.start =	snd_opl3_timer1_start,
209	.stop =		snd_opl3_timer1_stop,
210};
211
212static const struct snd_timer_hardware snd_opl3_timer2 =
213{
214	.flags =	SNDRV_TIMER_HW_STOP,
215	.resolution =	320000,
216	.ticks =	256,
217	.start =	snd_opl3_timer2_start,
218	.stop =		snd_opl3_timer2_stop,
219};
220
221static int snd_opl3_timer1_init(struct snd_opl3 * opl3, int timer_no)
222{
223	struct snd_timer *timer = NULL;
224	struct snd_timer_id tid;
225	int err;
226
227	tid.dev_class = SNDRV_TIMER_CLASS_CARD;
228	tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
229	tid.card = opl3->card->number;
230	tid.device = timer_no;
231	tid.subdevice = 0;
232	err = snd_timer_new(opl3->card, "AdLib timer #1", &tid, &timer);
233	if (err >= 0) {
234		strscpy(timer->name, "AdLib timer #1");
235		timer->private_data = opl3;
236		timer->hw = snd_opl3_timer1;
237	}
238	opl3->timer1 = timer;
239	return err;
240}
241
242static int snd_opl3_timer2_init(struct snd_opl3 * opl3, int timer_no)
243{
244	struct snd_timer *timer = NULL;
245	struct snd_timer_id tid;
246	int err;
247
248	tid.dev_class = SNDRV_TIMER_CLASS_CARD;
249	tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
250	tid.card = opl3->card->number;
251	tid.device = timer_no;
252	tid.subdevice = 0;
253	err = snd_timer_new(opl3->card, "AdLib timer #2", &tid, &timer);
254	if (err >= 0) {
255		strscpy(timer->name, "AdLib timer #2");
256		timer->private_data = opl3;
257		timer->hw = snd_opl3_timer2;
258	}
259	opl3->timer2 = timer;
260	return err;
261}
262
263/*
264
265 */
266
267void snd_opl3_interrupt(struct snd_hwdep * hw)
268{
269	unsigned char status;
270	struct snd_opl3 *opl3;
271	struct snd_timer *timer;
272
273	if (hw == NULL)
274		return;
275
276	opl3 = hw->private_data;
277	status = inb(opl3->l_port);
278	if (!(status & 0x80))
279		return;
280
281	if (status & 0x40) {
282		timer = opl3->timer1;
283		snd_timer_interrupt(timer, timer->sticks);
284	}
285	if (status & 0x20) {
286		timer = opl3->timer2;
287		snd_timer_interrupt(timer, timer->sticks);
288	}
289}
290
291EXPORT_SYMBOL(snd_opl3_interrupt);
292
293/*
294
295 */
296
297static int snd_opl3_free(struct snd_opl3 *opl3)
298{
299	if (snd_BUG_ON(!opl3))
300		return -ENXIO;
301	if (opl3->private_free)
302		opl3->private_free(opl3);
303	snd_opl3_clear_patches(opl3);
304	release_and_free_resource(opl3->res_l_port);
305	release_and_free_resource(opl3->res_r_port);
306	kfree(opl3);
307	return 0;
308}
309
310static int snd_opl3_dev_free(struct snd_device *device)
311{
312	struct snd_opl3 *opl3 = device->device_data;
313	return snd_opl3_free(opl3);
314}
315
316int snd_opl3_new(struct snd_card *card,
317		 unsigned short hardware,
318		 struct snd_opl3 **ropl3)
319{
320	static const struct snd_device_ops ops = {
321		.dev_free = snd_opl3_dev_free,
322	};
323	struct snd_opl3 *opl3;
324	int err;
325
326	*ropl3 = NULL;
327	opl3 = kzalloc(sizeof(*opl3), GFP_KERNEL);
328	if (!opl3)
329		return -ENOMEM;
330
331	opl3->card = card;
332	opl3->hardware = hardware;
333	spin_lock_init(&opl3->reg_lock);
334	spin_lock_init(&opl3->timer_lock);
335
336	err = snd_device_new(card, SNDRV_DEV_CODEC, opl3, &ops);
337	if (err < 0) {
338		snd_opl3_free(opl3);
339		return err;
340	}
341
342	*ropl3 = opl3;
343	return 0;
344}
345
346EXPORT_SYMBOL(snd_opl3_new);
347
348int snd_opl3_init(struct snd_opl3 *opl3)
349{
350	if (! opl3->command) {
351		dev_err(opl3->card->dev,
352			"snd_opl3_init: command not defined!\n");
353		return -EINVAL;
354	}
355
356	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TEST, OPL3_ENABLE_WAVE_SELECT);
357	/* Melodic mode */
358	opl3->command(opl3, OPL3_LEFT | OPL3_REG_PERCUSSION, 0x00);
359
360	switch (opl3->hardware & OPL3_HW_MASK) {
361	case OPL3_HW_OPL2:
362		opl3->max_voices = MAX_OPL2_VOICES;
363		break;
364	case OPL3_HW_OPL3:
365	case OPL3_HW_OPL4:
366		opl3->max_voices = MAX_OPL3_VOICES;
367		/* Enter OPL3 mode */
368		opl3->command(opl3, OPL3_RIGHT | OPL3_REG_MODE, OPL3_OPL3_ENABLE);
369	}
370	return 0;
371}
372
373EXPORT_SYMBOL(snd_opl3_init);
374
375int snd_opl3_create(struct snd_card *card,
376		    unsigned long l_port,
377		    unsigned long r_port,
378		    unsigned short hardware,
379		    int integrated,
380		    struct snd_opl3 ** ropl3)
381{
382	struct snd_opl3 *opl3;
383	int err;
384
385	*ropl3 = NULL;
386	err = snd_opl3_new(card, hardware, &opl3);
387	if (err < 0)
388		return err;
389	if (! integrated) {
390		opl3->res_l_port = request_region(l_port, 2, "OPL2/3 (left)");
391		if (!opl3->res_l_port) {
392			dev_err(card->dev, "opl3: can't grab left port 0x%lx\n", l_port);
393			snd_device_free(card, opl3);
394			return -EBUSY;
395		}
396		if (r_port != 0) {
397			opl3->res_r_port = request_region(r_port, 2, "OPL2/3 (right)");
398			if (!opl3->res_r_port) {
399				dev_err(card->dev, "opl3: can't grab right port 0x%lx\n", r_port);
400				snd_device_free(card, opl3);
401				return -EBUSY;
402			}
403		}
404	}
405	opl3->l_port = l_port;
406	opl3->r_port = r_port;
407
408	switch (opl3->hardware) {
409	/* some hardware doesn't support timers */
410	case OPL3_HW_OPL3_SV:
411	case OPL3_HW_OPL3_CS:
412	case OPL3_HW_OPL3_FM801:
413		opl3->command = &snd_opl3_command;
414		break;
415	default:
416		opl3->command = &snd_opl2_command;
417		err = snd_opl3_detect(opl3);
418		if (err < 0) {
419			dev_dbg(card->dev, "OPL2/3 chip not detected at 0x%lx/0x%lx\n",
420				opl3->l_port, opl3->r_port);
421			snd_device_free(card, opl3);
422			return err;
423		}
424		/* detect routine returns correct hardware type */
425		switch (opl3->hardware & OPL3_HW_MASK) {
426		case OPL3_HW_OPL3:
427		case OPL3_HW_OPL4:
428			opl3->command = &snd_opl3_command;
429		}
430	}
431
432	snd_opl3_init(opl3);
433
434	*ropl3 = opl3;
435	return 0;
436}
437
438EXPORT_SYMBOL(snd_opl3_create);
439
440int snd_opl3_timer_new(struct snd_opl3 * opl3, int timer1_dev, int timer2_dev)
441{
442	int err;
443
444	if (timer1_dev >= 0) {
445		err = snd_opl3_timer1_init(opl3, timer1_dev);
446		if (err < 0)
447			return err;
448	}
449	if (timer2_dev >= 0) {
450		err = snd_opl3_timer2_init(opl3, timer2_dev);
451		if (err < 0) {
452			snd_device_free(opl3->card, opl3->timer1);
453			opl3->timer1 = NULL;
454			return err;
455		}
456	}
457	return 0;
458}
459
460EXPORT_SYMBOL(snd_opl3_timer_new);
461
462int snd_opl3_hwdep_new(struct snd_opl3 * opl3,
463		       int device, int seq_device,
464		       struct snd_hwdep ** rhwdep)
465{
466	struct snd_hwdep *hw;
467	struct snd_card *card = opl3->card;
468	int err;
469
470	if (rhwdep)
471		*rhwdep = NULL;
472
473	/* create hardware dependent device (direct FM) */
474
475	err = snd_hwdep_new(card, "OPL2/OPL3", device, &hw);
476	if (err < 0) {
477		snd_device_free(card, opl3);
478		return err;
479	}
480	hw->private_data = opl3;
481	hw->exclusive = 1;
482#ifdef CONFIG_SND_OSSEMUL
483	if (device == 0)
484		hw->oss_type = SNDRV_OSS_DEVICE_TYPE_DMFM;
485#endif
486	strscpy(hw->name, hw->id);
487	switch (opl3->hardware & OPL3_HW_MASK) {
488	case OPL3_HW_OPL2:
489		strscpy(hw->name, "OPL2 FM");
490		hw->iface = SNDRV_HWDEP_IFACE_OPL2;
491		break;
492	case OPL3_HW_OPL3:
493		strscpy(hw->name, "OPL3 FM");
494		hw->iface = SNDRV_HWDEP_IFACE_OPL3;
495		break;
496	case OPL3_HW_OPL4:
497		strscpy(hw->name, "OPL4 FM");
498		hw->iface = SNDRV_HWDEP_IFACE_OPL4;
499		break;
500	}
501
502	/* operators - only ioctl */
503	hw->ops.open = snd_opl3_open;
504	hw->ops.ioctl = snd_opl3_ioctl;
505	hw->ops.write = snd_opl3_write;
506	hw->ops.release = snd_opl3_release;
507
508	opl3->hwdep = hw;
509	opl3->seq_dev_num = seq_device;
510#if IS_ENABLED(CONFIG_SND_SEQUENCER)
511	if (snd_seq_device_new(card, seq_device, SNDRV_SEQ_DEV_ID_OPL3,
512			       sizeof(struct snd_opl3 *), &opl3->seq_dev) >= 0) {
513		strscpy(opl3->seq_dev->name, hw->name);
514		*(struct snd_opl3 **)SNDRV_SEQ_DEVICE_ARGPTR(opl3->seq_dev) = opl3;
515	}
516#endif
517	if (rhwdep)
518		*rhwdep = hw;
519	return 0;
520}
521
522EXPORT_SYMBOL(snd_opl3_hwdep_new);