aaci.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 *  linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
   4 *
   5 *  Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
   6 *
   7 *  Documentation: ARM DDI 0173B
   8 */
   9#include <linux/module.h>
  10#include <linux/delay.h>
  11#include <linux/init.h>
  12#include <linux/ioport.h>
  13#include <linux/device.h>
  14#include <linux/spinlock.h>
  15#include <linux/interrupt.h>
  16#include <linux/err.h>
  17#include <linux/amba/bus.h>
  18#include <linux/io.h>
  19
  20#include <sound/core.h>
  21#include <sound/initval.h>
  22#include <sound/ac97_codec.h>
  23#include <sound/pcm.h>
  24#include <sound/pcm_params.h>
  25
  26#include "aaci.h"
  27
  28#define DRIVER_NAME	"aaci-pl041"
  29
  30#define FRAME_PERIOD_US	21
  31
  32/*
  33 * PM support is not complete.  Turn it off.
  34 */
  35#undef CONFIG_PM
  36
  37static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97)
  38{
  39	u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num);
  40
  41	/*
  42	 * Ensure that the slot 1/2 RX registers are empty.
  43	 */
  44	v = readl(aaci->base + AACI_SLFR);
  45	if (v & SLFR_2RXV)
  46		readl(aaci->base + AACI_SL2RX);
  47	if (v & SLFR_1RXV)
  48		readl(aaci->base + AACI_SL1RX);
  49
  50	if (maincr != readl(aaci->base + AACI_MAINCR)) {
  51		writel(maincr, aaci->base + AACI_MAINCR);
  52		readl(aaci->base + AACI_MAINCR);
  53		udelay(1);
  54	}
  55}
  56
  57/*
  58 * P29:
  59 *  The recommended use of programming the external codec through slot 1
  60 *  and slot 2 data is to use the channels during setup routines and the
  61 *  slot register at any other time.  The data written into slot 1, slot 2
  62 *  and slot 12 registers is transmitted only when their corresponding
  63 *  SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR
  64 *  register.
  65 */
  66static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
  67			    unsigned short val)
  68{
  69	struct aaci *aaci = ac97->private_data;
  70	int timeout;
  71	u32 v;
  72
  73	if (ac97->num >= 4)
  74		return;
  75
  76	guard(mutex)(&aaci->ac97_sem);
  77
  78	aaci_ac97_select_codec(aaci, ac97);
  79
  80	/*
  81	 * P54: You must ensure that AACI_SL2TX is always written
  82	 * to, if required, before data is written to AACI_SL1TX.
  83	 */
  84	writel(val << 4, aaci->base + AACI_SL2TX);
  85	writel(reg << 12, aaci->base + AACI_SL1TX);
  86
  87	/* Initially, wait one frame period */
  88	udelay(FRAME_PERIOD_US);
  89
  90	/* And then wait an additional eight frame periods for it to be sent */
  91	timeout = FRAME_PERIOD_US * 8;
  92	do {
  93		udelay(1);
  94		v = readl(aaci->base + AACI_SLFR);
  95	} while ((v & (SLFR_1TXB|SLFR_2TXB)) && --timeout);
  96
  97	if (v & (SLFR_1TXB|SLFR_2TXB))
  98		dev_err(&aaci->dev->dev,
  99			"timeout waiting for write to complete\n");
 100}
 101
 102/*
 103 * Read an AC'97 register.
 104 */
 105static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
 106{
 107	struct aaci *aaci = ac97->private_data;
 108	int timeout, retries = 10;
 109	u32 v;
 110
 111	if (ac97->num >= 4)
 112		return ~0;
 113
 114	guard(mutex)(&aaci->ac97_sem);
 115
 116	aaci_ac97_select_codec(aaci, ac97);
 117
 118	/*
 119	 * Write the register address to slot 1.
 120	 */
 121	writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX);
 122
 123	/* Initially, wait one frame period */
 124	udelay(FRAME_PERIOD_US);
 125
 126	/* And then wait an additional eight frame periods for it to be sent */
 127	timeout = FRAME_PERIOD_US * 8;
 128	do {
 129		udelay(1);
 130		v = readl(aaci->base + AACI_SLFR);
 131	} while ((v & SLFR_1TXB) && --timeout);
 132
 133	if (v & SLFR_1TXB) {
 134		dev_err(&aaci->dev->dev, "timeout on slot 1 TX busy\n");
 135		return ~0;
 136	}
 137
 138	/* Now wait for the response frame */
 139	udelay(FRAME_PERIOD_US);
 140
 141	/* And then wait an additional eight frame periods for data */
 142	timeout = FRAME_PERIOD_US * 8;
 143	do {
 144		udelay(1);
 145		cond_resched();
 146		v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV);
 147	} while ((v != (SLFR_1RXV|SLFR_2RXV)) && --timeout);
 148
 149	if (v != (SLFR_1RXV|SLFR_2RXV)) {
 150		dev_err(&aaci->dev->dev, "timeout on RX valid\n");
 151		return ~0;
 152	}
 153
 154	do {
 155		v = readl(aaci->base + AACI_SL1RX) >> 12;
 156		if (v == reg) {
 157			v = readl(aaci->base + AACI_SL2RX) >> 4;
 158			break;
 159		} else if (--retries) {
 160			dev_warn(&aaci->dev->dev,
 161				 "ac97 read back fail.  retry\n");
 162			continue;
 163		} else {
 164			dev_warn(&aaci->dev->dev,
 165				"wrong ac97 register read back (%x != %x)\n",
 166				v, reg);
 167			v = ~0;
 168		}
 169	} while (retries);
 170	return v;
 171}
 172
 173static inline void
 174aaci_chan_wait_ready(struct aaci_runtime *aacirun, unsigned long mask)
 175{
 176	u32 val;
 177	int timeout = 5000;
 178
 179	do {
 180		udelay(1);
 181		val = readl(aacirun->base + AACI_SR);
 182	} while (val & mask && timeout--);
 183}
 184
 185
 186
 187/*
 188 * Interrupt support.
 189 */
 190static void aaci_fifo_irq(struct aaci *aaci, int channel, u32 mask)
 191{
 192	if (mask & ISR_ORINTR) {
 193		dev_warn(&aaci->dev->dev, "RX overrun on chan %d\n", channel);
 194		writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR);
 195	}
 196
 197	if (mask & ISR_RXTOINTR) {
 198		dev_warn(&aaci->dev->dev, "RX timeout on chan %d\n", channel);
 199		writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR);
 200	}
 201
 202	if (mask & ISR_RXINTR) {
 203		struct aaci_runtime *aacirun = &aaci->capture;
 204		bool period_elapsed = false;
 205		void *ptr;
 206
 207		if (!aacirun->substream || !aacirun->start) {
 208			dev_warn(&aaci->dev->dev, "RX interrupt???\n");
 209			writel(0, aacirun->base + AACI_IE);
 210			return;
 211		}
 212
 213		scoped_guard(spinlock, &aacirun->lock) {
 214			ptr = aacirun->ptr;
 215			do {
 216				unsigned int len = aacirun->fifo_bytes;
 217				u32 val;
 218
 219				if (aacirun->bytes <= 0) {
 220					aacirun->bytes += aacirun->period;
 221					period_elapsed = true;
 222				}
 223				if (!(aacirun->cr & CR_EN))
 224					break;
 225
 226				val = readl(aacirun->base + AACI_SR);
 227				if (!(val & SR_RXHF))
 228					break;
 229				if (!(val & SR_RXFF))
 230					len >>= 1;
 231
 232				aacirun->bytes -= len;
 233
 234				/* reading 16 bytes at a time */
 235				for( ; len > 0; len -= 16) {
 236					asm(
 237					    "ldmia	%1, {r0, r1, r2, r3}\n\t"
 238					    "stmia	%0!, {r0, r1, r2, r3}"
 239					    : "+r" (ptr)
 240					    : "r" (aacirun->fifo)
 241					    : "r0", "r1", "r2", "r3", "cc");
 242
 243					if (ptr >= aacirun->end)
 244						ptr = aacirun->start;
 245				}
 246			} while(1);
 247
 248			aacirun->ptr = ptr;
 249		}
 250
 251		if (period_elapsed)
 252			snd_pcm_period_elapsed(aacirun->substream);
 253	}
 254
 255	if (mask & ISR_URINTR) {
 256		dev_dbg(&aaci->dev->dev, "TX underrun on chan %d\n", channel);
 257		writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR);
 258	}
 259
 260	if (mask & ISR_TXINTR) {
 261		struct aaci_runtime *aacirun = &aaci->playback;
 262		bool period_elapsed = false;
 263		void *ptr;
 264
 265		if (!aacirun->substream || !aacirun->start) {
 266			dev_warn(&aaci->dev->dev, "TX interrupt???\n");
 267			writel(0, aacirun->base + AACI_IE);
 268			return;
 269		}
 270
 271		scoped_guard(spinlock, &aacirun->lock) {
 272			ptr = aacirun->ptr;
 273			do {
 274				unsigned int len = aacirun->fifo_bytes;
 275				u32 val;
 276
 277				if (aacirun->bytes <= 0) {
 278					aacirun->bytes += aacirun->period;
 279					period_elapsed = true;
 280				}
 281				if (!(aacirun->cr & CR_EN))
 282					break;
 283
 284				val = readl(aacirun->base + AACI_SR);
 285				if (!(val & SR_TXHE))
 286					break;
 287				if (!(val & SR_TXFE))
 288					len >>= 1;
 289
 290				aacirun->bytes -= len;
 291
 292				/* writing 16 bytes at a time */
 293				for ( ; len > 0; len -= 16) {
 294					asm(
 295					    "ldmia	%0!, {r0, r1, r2, r3}\n\t"
 296					    "stmia	%1, {r0, r1, r2, r3}"
 297					    : "+r" (ptr)
 298					    : "r" (aacirun->fifo)
 299					    : "r0", "r1", "r2", "r3", "cc");
 300
 301					if (ptr >= aacirun->end)
 302						ptr = aacirun->start;
 303				}
 304			} while (1);
 305
 306			aacirun->ptr = ptr;
 307		}
 308
 309		if (period_elapsed)
 310			snd_pcm_period_elapsed(aacirun->substream);
 311	}
 312}
 313
 314static irqreturn_t aaci_irq(int irq, void *devid)
 315{
 316	struct aaci *aaci = devid;
 317	u32 mask;
 318	int i;
 319
 320	mask = readl(aaci->base + AACI_ALLINTS);
 321	if (mask) {
 322		u32 m = mask;
 323		for (i = 0; i < 4; i++, m >>= 7) {
 324			if (m & 0x7f) {
 325				aaci_fifo_irq(aaci, i, m);
 326			}
 327		}
 328	}
 329
 330	return mask ? IRQ_HANDLED : IRQ_NONE;
 331}
 332
 333
 334
 335/*
 336 * ALSA support.
 337 */
 338static const struct snd_pcm_hardware aaci_hw_info = {
 339	.info			= SNDRV_PCM_INFO_MMAP |
 340				  SNDRV_PCM_INFO_MMAP_VALID |
 341				  SNDRV_PCM_INFO_INTERLEAVED |
 342				  SNDRV_PCM_INFO_BLOCK_TRANSFER |
 343				  SNDRV_PCM_INFO_RESUME,
 344
 345	/*
 346	 * ALSA doesn't support 18-bit or 20-bit packed into 32-bit
 347	 * words.  It also doesn't support 12-bit at all.
 348	 */
 349	.formats		= SNDRV_PCM_FMTBIT_S16_LE,
 350
 351	/* rates are setup from the AC'97 codec */
 352	.channels_min		= 2,
 353	.channels_max		= 2,
 354	.buffer_bytes_max	= 64 * 1024,
 355	.period_bytes_min	= 256,
 356	.period_bytes_max	= PAGE_SIZE,
 357	.periods_min		= 4,
 358	.periods_max		= PAGE_SIZE / 16,
 359};
 360
 361/*
 362 * We can support two and four channel audio.  Unfortunately
 363 * six channel audio requires a non-standard channel ordering:
 364 *   2 -> FL(3), FR(4)
 365 *   4 -> FL(3), FR(4), SL(7), SR(8)
 366 *   6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required)
 367 *        FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual)
 368 * This requires an ALSA configuration file to correct.
 369 */
 370static int aaci_rule_channels(struct snd_pcm_hw_params *p,
 371	struct snd_pcm_hw_rule *rule)
 372{
 373	static const unsigned int channel_list[] = { 2, 4, 6 };
 374	struct aaci *aaci = rule->private;
 375	unsigned int mask = 1 << 0, slots;
 376
 377	/* pcms[0] is the our 5.1 PCM instance. */
 378	slots = aaci->ac97_bus->pcms[0].r[0].slots;
 379	if (slots & (1 << AC97_SLOT_PCM_SLEFT)) {
 380		mask |= 1 << 1;
 381		if (slots & (1 << AC97_SLOT_LFE))
 382			mask |= 1 << 2;
 383	}
 384
 385	return snd_interval_list(hw_param_interval(p, rule->var),
 386				 ARRAY_SIZE(channel_list), channel_list, mask);
 387}
 388
 389static int aaci_pcm_open(struct snd_pcm_substream *substream)
 390{
 391	struct snd_pcm_runtime *runtime = substream->runtime;
 392	struct aaci *aaci = substream->private_data;
 393	struct aaci_runtime *aacirun;
 394	int ret = 0;
 395
 396	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 397		aacirun = &aaci->playback;
 398	} else {
 399		aacirun = &aaci->capture;
 400	}
 401
 402	aacirun->substream = substream;
 403	runtime->private_data = aacirun;
 404	runtime->hw = aaci_hw_info;
 405	runtime->hw.rates = aacirun->pcm->rates;
 406	snd_pcm_limit_hw_rates(runtime);
 407
 408	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 409		runtime->hw.channels_max = 6;
 410
 411		/* Add rule describing channel dependency. */
 412		ret = snd_pcm_hw_rule_add(substream->runtime, 0,
 413					  SNDRV_PCM_HW_PARAM_CHANNELS,
 414					  aaci_rule_channels, aaci,
 415					  SNDRV_PCM_HW_PARAM_CHANNELS, -1);
 416		if (ret)
 417			return ret;
 418
 419		if (aacirun->pcm->r[1].slots)
 420			snd_ac97_pcm_double_rate_rules(runtime);
 421	}
 422
 423	/*
 424	 * ALSA wants the byte-size of the FIFOs.  As we only support
 425	 * 16-bit samples, this is twice the FIFO depth irrespective
 426	 * of whether it's in compact mode or not.
 427	 */
 428	runtime->hw.fifo_size = aaci->fifo_depth * 2;
 429
 430	guard(mutex)(&aaci->irq_lock);
 431	if (!aaci->users++) {
 432		ret = request_irq(aaci->dev->irq[0], aaci_irq,
 433			   IRQF_SHARED, DRIVER_NAME, aaci);
 434		if (ret != 0)
 435			aaci->users--;
 436	}
 437
 438	return ret;
 439}
 440
 441
 442/*
 443 * Common ALSA stuff
 444 */
 445static int aaci_pcm_close(struct snd_pcm_substream *substream)
 446{
 447	struct aaci *aaci = substream->private_data;
 448	struct aaci_runtime *aacirun = substream->runtime->private_data;
 449
 450	WARN_ON(aacirun->cr & CR_EN);
 451
 452	aacirun->substream = NULL;
 453
 454	guard(mutex)(&aaci->irq_lock);
 455	if (!--aaci->users)
 456		free_irq(aaci->dev->irq[0], aaci);
 457
 458	return 0;
 459}
 460
 461static int aaci_pcm_hw_free(struct snd_pcm_substream *substream)
 462{
 463	struct aaci_runtime *aacirun = substream->runtime->private_data;
 464
 465	/*
 466	 * This must not be called with the device enabled.
 467	 */
 468	WARN_ON(aacirun->cr & CR_EN);
 469
 470	if (aacirun->pcm_open)
 471		snd_ac97_pcm_close(aacirun->pcm);
 472	aacirun->pcm_open = 0;
 473
 474	return 0;
 475}
 476
 477/* Channel to slot mask */
 478static const u32 channels_to_slotmask[] = {
 479	[2] = CR_SL3 | CR_SL4,
 480	[4] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8,
 481	[6] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8 | CR_SL6 | CR_SL9,
 482};
 483
 484static int aaci_pcm_hw_params(struct snd_pcm_substream *substream,
 485			      struct snd_pcm_hw_params *params)
 486{
 487	struct aaci_runtime *aacirun = substream->runtime->private_data;
 488	struct aaci *aaci = substream->private_data;
 489	unsigned int channels = params_channels(params);
 490	unsigned int rate = params_rate(params);
 491	int dbl = rate > 48000;
 492	int err;
 493
 494	aaci_pcm_hw_free(substream);
 495	if (aacirun->pcm_open) {
 496		snd_ac97_pcm_close(aacirun->pcm);
 497		aacirun->pcm_open = 0;
 498	}
 499
 500	/* channels is already limited to 2, 4, or 6 by aaci_rule_channels */
 501	if (dbl && channels != 2)
 502		return -EINVAL;
 503
 504	err = snd_ac97_pcm_open(aacirun->pcm, rate, channels,
 505				aacirun->pcm->r[dbl].slots);
 506
 507	aacirun->pcm_open = err == 0;
 508	aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16;
 509	aacirun->cr |= channels_to_slotmask[channels + dbl * 2];
 510
 511	/*
 512	 * fifo_bytes is the number of bytes we transfer to/from
 513	 * the FIFO, including padding.  So that's x4.  As we're
 514	 * in compact mode, the FIFO is half the size.
 515	 */
 516	aacirun->fifo_bytes = aaci->fifo_depth * 4 / 2;
 517
 518	return err;
 519}
 520
 521static int aaci_pcm_prepare(struct snd_pcm_substream *substream)
 522{
 523	struct snd_pcm_runtime *runtime = substream->runtime;
 524	struct aaci_runtime *aacirun = runtime->private_data;
 525
 526	aacirun->period	= snd_pcm_lib_period_bytes(substream);
 527	aacirun->start	= runtime->dma_area;
 528	aacirun->end	= aacirun->start + snd_pcm_lib_buffer_bytes(substream);
 529	aacirun->ptr	= aacirun->start;
 530	aacirun->bytes	= aacirun->period;
 531
 532	return 0;
 533}
 534
 535static snd_pcm_uframes_t aaci_pcm_pointer(struct snd_pcm_substream *substream)
 536{
 537	struct snd_pcm_runtime *runtime = substream->runtime;
 538	struct aaci_runtime *aacirun = runtime->private_data;
 539	ssize_t bytes = aacirun->ptr - aacirun->start;
 540
 541	return bytes_to_frames(runtime, bytes);
 542}
 543
 544
 545/*
 546 * Playback specific ALSA stuff
 547 */
 548static void aaci_pcm_playback_stop(struct aaci_runtime *aacirun)
 549{
 550	u32 ie;
 551
 552	ie = readl(aacirun->base + AACI_IE);
 553	ie &= ~(IE_URIE|IE_TXIE);
 554	writel(ie, aacirun->base + AACI_IE);
 555	aacirun->cr &= ~CR_EN;
 556	aaci_chan_wait_ready(aacirun, SR_TXB);
 557	writel(aacirun->cr, aacirun->base + AACI_TXCR);
 558}
 559
 560static void aaci_pcm_playback_start(struct aaci_runtime *aacirun)
 561{
 562	u32 ie;
 563
 564	aaci_chan_wait_ready(aacirun, SR_TXB);
 565	aacirun->cr |= CR_EN;
 566
 567	ie = readl(aacirun->base + AACI_IE);
 568	ie |= IE_URIE | IE_TXIE;
 569	writel(ie, aacirun->base + AACI_IE);
 570	writel(aacirun->cr, aacirun->base + AACI_TXCR);
 571}
 572
 573static int aaci_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd)
 574{
 575	struct aaci_runtime *aacirun = substream->runtime->private_data;
 576
 577	guard(spinlock_irqsave)(&aacirun->lock);
 578
 579	switch (cmd) {
 580	case SNDRV_PCM_TRIGGER_START:
 581		aaci_pcm_playback_start(aacirun);
 582		break;
 583
 584	case SNDRV_PCM_TRIGGER_RESUME:
 585		aaci_pcm_playback_start(aacirun);
 586		break;
 587
 588	case SNDRV_PCM_TRIGGER_STOP:
 589		aaci_pcm_playback_stop(aacirun);
 590		break;
 591
 592	case SNDRV_PCM_TRIGGER_SUSPEND:
 593		aaci_pcm_playback_stop(aacirun);
 594		break;
 595
 596	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 597		break;
 598
 599	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 600		break;
 601
 602	default:
 603		return -EINVAL;
 604	}
 605
 606	return 0;
 607}
 608
 609static const struct snd_pcm_ops aaci_playback_ops = {
 610	.open		= aaci_pcm_open,
 611	.close		= aaci_pcm_close,
 612	.hw_params	= aaci_pcm_hw_params,
 613	.hw_free	= aaci_pcm_hw_free,
 614	.prepare	= aaci_pcm_prepare,
 615	.trigger	= aaci_pcm_playback_trigger,
 616	.pointer	= aaci_pcm_pointer,
 617};
 618
 619static void aaci_pcm_capture_stop(struct aaci_runtime *aacirun)
 620{
 621	u32 ie;
 622
 623	aaci_chan_wait_ready(aacirun, SR_RXB);
 624
 625	ie = readl(aacirun->base + AACI_IE);
 626	ie &= ~(IE_ORIE | IE_RXIE);
 627	writel(ie, aacirun->base+AACI_IE);
 628
 629	aacirun->cr &= ~CR_EN;
 630
 631	writel(aacirun->cr, aacirun->base + AACI_RXCR);
 632}
 633
 634static void aaci_pcm_capture_start(struct aaci_runtime *aacirun)
 635{
 636	u32 ie;
 637
 638	aaci_chan_wait_ready(aacirun, SR_RXB);
 639
 640#ifdef DEBUG
 641	/* RX Timeout value: bits 28:17 in RXCR */
 642	aacirun->cr |= 0xf << 17;
 643#endif
 644
 645	aacirun->cr |= CR_EN;
 646	writel(aacirun->cr, aacirun->base + AACI_RXCR);
 647
 648	ie = readl(aacirun->base + AACI_IE);
 649	ie |= IE_ORIE |IE_RXIE; // overrun and rx interrupt -- half full
 650	writel(ie, aacirun->base + AACI_IE);
 651}
 652
 653static int aaci_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd)
 654{
 655	struct aaci_runtime *aacirun = substream->runtime->private_data;
 656
 657	guard(spinlock_irqsave)(&aacirun->lock);
 658
 659	switch (cmd) {
 660	case SNDRV_PCM_TRIGGER_START:
 661		aaci_pcm_capture_start(aacirun);
 662		break;
 663
 664	case SNDRV_PCM_TRIGGER_RESUME:
 665		aaci_pcm_capture_start(aacirun);
 666		break;
 667
 668	case SNDRV_PCM_TRIGGER_STOP:
 669		aaci_pcm_capture_stop(aacirun);
 670		break;
 671
 672	case SNDRV_PCM_TRIGGER_SUSPEND:
 673		aaci_pcm_capture_stop(aacirun);
 674		break;
 675
 676	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 677		break;
 678
 679	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 680		break;
 681
 682	default:
 683		return -EINVAL;
 684	}
 685
 686	return 0;
 687}
 688
 689static int aaci_pcm_capture_prepare(struct snd_pcm_substream *substream)
 690{
 691	struct snd_pcm_runtime *runtime = substream->runtime;
 692	struct aaci *aaci = substream->private_data;
 693
 694	aaci_pcm_prepare(substream);
 695
 696	/* allow changing of sample rate */
 697	aaci_ac97_write(aaci->ac97, AC97_EXTENDED_STATUS, 0x0001); /* VRA */
 698	aaci_ac97_write(aaci->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
 699	aaci_ac97_write(aaci->ac97, AC97_PCM_MIC_ADC_RATE, runtime->rate);
 700
 701	/* Record select: Mic: 0, Aux: 3, Line: 4 */
 702	aaci_ac97_write(aaci->ac97, AC97_REC_SEL, 0x0404);
 703
 704	return 0;
 705}
 706
 707static const struct snd_pcm_ops aaci_capture_ops = {
 708	.open		= aaci_pcm_open,
 709	.close		= aaci_pcm_close,
 710	.hw_params	= aaci_pcm_hw_params,
 711	.hw_free	= aaci_pcm_hw_free,
 712	.prepare	= aaci_pcm_capture_prepare,
 713	.trigger	= aaci_pcm_capture_trigger,
 714	.pointer	= aaci_pcm_pointer,
 715};
 716
 717/*
 718 * Power Management.
 719 */
 720static int aaci_do_suspend(struct snd_card *card)
 721{
 722	snd_power_change_state(card, SNDRV_CTL_POWER_D3cold);
 723	return 0;
 724}
 725
 726static int aaci_do_resume(struct snd_card *card)
 727{
 728	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
 729	return 0;
 730}
 731
 732static int aaci_suspend(struct device *dev)
 733{
 734	struct snd_card *card = dev_get_drvdata(dev);
 735	return card ? aaci_do_suspend(card) : 0;
 736}
 737
 738static int aaci_resume(struct device *dev)
 739{
 740	struct snd_card *card = dev_get_drvdata(dev);
 741	return card ? aaci_do_resume(card) : 0;
 742}
 743
 744static DEFINE_SIMPLE_DEV_PM_OPS(aaci_dev_pm_ops, aaci_suspend, aaci_resume);
 745
 746static const struct ac97_pcm ac97_defs[] = {
 747	[0] = {	/* Front PCM */
 748		.exclusive = 1,
 749		.r = {
 750			[0] = {
 751				.slots	= (1 << AC97_SLOT_PCM_LEFT) |
 752					  (1 << AC97_SLOT_PCM_RIGHT) |
 753					  (1 << AC97_SLOT_PCM_CENTER) |
 754					  (1 << AC97_SLOT_PCM_SLEFT) |
 755					  (1 << AC97_SLOT_PCM_SRIGHT) |
 756					  (1 << AC97_SLOT_LFE),
 757			},
 758			[1] = {
 759				.slots	= (1 << AC97_SLOT_PCM_LEFT) |
 760					  (1 << AC97_SLOT_PCM_RIGHT) |
 761					  (1 << AC97_SLOT_PCM_LEFT_0) |
 762					  (1 << AC97_SLOT_PCM_RIGHT_0),
 763			},
 764		},
 765	},
 766	[1] = {	/* PCM in */
 767		.stream = 1,
 768		.exclusive = 1,
 769		.r = {
 770			[0] = {
 771				.slots	= (1 << AC97_SLOT_PCM_LEFT) |
 772					  (1 << AC97_SLOT_PCM_RIGHT),
 773			},
 774		},
 775	},
 776	[2] = {	/* Mic in */
 777		.stream = 1,
 778		.exclusive = 1,
 779		.r = {
 780			[0] = {
 781				.slots	= (1 << AC97_SLOT_MIC),
 782			},
 783		},
 784	}
 785};
 786
 787static const struct snd_ac97_bus_ops aaci_bus_ops = {
 788	.write	= aaci_ac97_write,
 789	.read	= aaci_ac97_read,
 790};
 791
 792static int aaci_probe_ac97(struct aaci *aaci)
 793{
 794	struct snd_ac97_template ac97_template;
 795	struct snd_ac97_bus *ac97_bus;
 796	struct snd_ac97 *ac97;
 797	int ret;
 798
 799	/*
 800	 * Assert AACIRESET for 2us
 801	 */
 802	writel(0, aaci->base + AACI_RESET);
 803	udelay(2);
 804	writel(RESET_NRST, aaci->base + AACI_RESET);
 805
 806	/*
 807	 * Give the AC'97 codec more than enough time
 808	 * to wake up. (42us = ~2 frames at 48kHz.)
 809	 */
 810	udelay(FRAME_PERIOD_US * 2);
 811
 812	ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus);
 813	if (ret)
 814		goto out;
 815
 816	ac97_bus->clock = 48000;
 817	aaci->ac97_bus = ac97_bus;
 818
 819	memset(&ac97_template, 0, sizeof(struct snd_ac97_template));
 820	ac97_template.private_data = aaci;
 821	ac97_template.num = 0;
 822	ac97_template.scaps = AC97_SCAP_SKIP_MODEM;
 823
 824	ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97);
 825	if (ret)
 826		goto out;
 827	aaci->ac97 = ac97;
 828
 829	/*
 830	 * Disable AC97 PC Beep input on audio codecs.
 831	 */
 832	if (ac97_is_audio(ac97))
 833		snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x801e);
 834
 835	ret = snd_ac97_pcm_assign(ac97_bus, ARRAY_SIZE(ac97_defs), ac97_defs);
 836	if (ret)
 837		goto out;
 838
 839	aaci->playback.pcm = &ac97_bus->pcms[0];
 840	aaci->capture.pcm  = &ac97_bus->pcms[1];
 841
 842 out:
 843	return ret;
 844}
 845
 846static void aaci_free_card(struct snd_card *card)
 847{
 848	struct aaci *aaci = card->private_data;
 849
 850	iounmap(aaci->base);
 851}
 852
 853static struct aaci *aaci_init_card(struct amba_device *dev)
 854{
 855	struct aaci *aaci;
 856	struct snd_card *card;
 857	int err;
 858
 859	err = snd_card_new(&dev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
 860			   THIS_MODULE, sizeof(struct aaci), &card);
 861	if (err < 0)
 862		return NULL;
 863
 864	card->private_free = aaci_free_card;
 865
 866	strscpy(card->driver, DRIVER_NAME, sizeof(card->driver));
 867	strscpy(card->shortname, "ARM AC'97 Interface", sizeof(card->shortname));
 868	snprintf(card->longname, sizeof(card->longname),
 869		 "%s PL%03x rev%u at 0x%08llx, irq %d",
 870		 card->shortname, amba_part(dev), amba_rev(dev),
 871		 (unsigned long long)dev->res.start, dev->irq[0]);
 872
 873	aaci = card->private_data;
 874	mutex_init(&aaci->ac97_sem);
 875	mutex_init(&aaci->irq_lock);
 876	aaci->card = card;
 877	aaci->dev = dev;
 878
 879	/* Set MAINCR to allow slot 1 and 2 data IO */
 880	aaci->maincr = MAINCR_IE | MAINCR_SL1RXEN | MAINCR_SL1TXEN |
 881		       MAINCR_SL2RXEN | MAINCR_SL2TXEN;
 882
 883	return aaci;
 884}
 885
 886static int aaci_init_pcm(struct aaci *aaci)
 887{
 888	struct snd_pcm *pcm;
 889	int ret;
 890
 891	ret = snd_pcm_new(aaci->card, "AACI AC'97", 0, 1, 1, &pcm);
 892	if (ret == 0) {
 893		aaci->pcm = pcm;
 894		pcm->private_data = aaci;
 895		pcm->info_flags = 0;
 896
 897		strscpy(pcm->name, DRIVER_NAME, sizeof(pcm->name));
 898
 899		snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &aaci_playback_ops);
 900		snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &aaci_capture_ops);
 901		snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
 902					       aaci->card->dev,
 903					       0, 64 * 1024);
 904	}
 905
 906	return ret;
 907}
 908
 909static unsigned int aaci_size_fifo(struct aaci *aaci)
 910{
 911	struct aaci_runtime *aacirun = &aaci->playback;
 912	int i;
 913
 914	/*
 915	 * Enable the channel, but don't assign it to any slots, so
 916	 * it won't empty onto the AC'97 link.
 917	 */
 918	writel(CR_FEN | CR_SZ16 | CR_EN, aacirun->base + AACI_TXCR);
 919
 920	for (i = 0; !(readl(aacirun->base + AACI_SR) & SR_TXFF) && i < 4096; i++)
 921		writel(0, aacirun->fifo);
 922
 923	writel(0, aacirun->base + AACI_TXCR);
 924
 925	/*
 926	 * Re-initialise the AACI after the FIFO depth test, to
 927	 * ensure that the FIFOs are empty.  Unfortunately, merely
 928	 * disabling the channel doesn't clear the FIFO.
 929	 */
 930	writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR);
 931	readl(aaci->base + AACI_MAINCR);
 932	udelay(1);
 933	writel(aaci->maincr, aaci->base + AACI_MAINCR);
 934
 935	/*
 936	 * If we hit 4096 entries, we failed.  Go back to the specified
 937	 * fifo depth.
 938	 */
 939	if (i == 4096)
 940		i = 8;
 941
 942	return i;
 943}
 944
 945static int aaci_probe(struct amba_device *dev,
 946		      const struct amba_id *id)
 947{
 948	struct aaci *aaci;
 949	int ret, i;
 950
 951	ret = amba_request_regions(dev, NULL);
 952	if (ret)
 953		return ret;
 954
 955	aaci = aaci_init_card(dev);
 956	if (!aaci) {
 957		ret = -ENOMEM;
 958		goto out;
 959	}
 960
 961	aaci->base = ioremap(dev->res.start, resource_size(&dev->res));
 962	if (!aaci->base) {
 963		ret = -ENOMEM;
 964		goto out;
 965	}
 966
 967	/*
 968	 * Playback uses AACI channel 0
 969	 */
 970	spin_lock_init(&aaci->playback.lock);
 971	aaci->playback.base = aaci->base + AACI_CSCH1;
 972	aaci->playback.fifo = aaci->base + AACI_DR1;
 973
 974	/*
 975	 * Capture uses AACI channel 0
 976	 */
 977	spin_lock_init(&aaci->capture.lock);
 978	aaci->capture.base = aaci->base + AACI_CSCH1;
 979	aaci->capture.fifo = aaci->base + AACI_DR1;
 980
 981	for (i = 0; i < 4; i++) {
 982		void __iomem *base = aaci->base + i * 0x14;
 983
 984		writel(0, base + AACI_IE);
 985		writel(0, base + AACI_TXCR);
 986		writel(0, base + AACI_RXCR);
 987	}
 988
 989	writel(0x1fff, aaci->base + AACI_INTCLR);
 990	writel(aaci->maincr, aaci->base + AACI_MAINCR);
 991	/*
 992	 * Fix: ac97 read back fail errors by reading
 993	 * from any arbitrary aaci register.
 994	 */
 995	readl(aaci->base + AACI_CSCH1);
 996	ret = aaci_probe_ac97(aaci);
 997	if (ret)
 998		goto out;
 999
1000	/*
1001	 * Size the FIFOs (must be multiple of 16).
1002	 * This is the number of entries in the FIFO.
1003	 */
1004	aaci->fifo_depth = aaci_size_fifo(aaci);
1005	if (aaci->fifo_depth & 15) {
1006		printk(KERN_WARNING "AACI: FIFO depth %d not supported\n",
1007		       aaci->fifo_depth);
1008		ret = -ENODEV;
1009		goto out;
1010	}
1011
1012	ret = aaci_init_pcm(aaci);
1013	if (ret)
1014		goto out;
1015
1016	ret = snd_card_register(aaci->card);
1017	if (ret == 0) {
1018		dev_info(&dev->dev, "%s\n", aaci->card->longname);
1019		dev_info(&dev->dev, "FIFO %u entries\n", aaci->fifo_depth);
1020		amba_set_drvdata(dev, aaci->card);
1021		return ret;
1022	}
1023
1024 out:
1025	if (aaci)
1026		snd_card_free(aaci->card);
1027	amba_release_regions(dev);
1028	return ret;
1029}
1030
1031static void aaci_remove(struct amba_device *dev)
1032{
1033	struct snd_card *card = amba_get_drvdata(dev);
1034
1035	if (card) {
1036		struct aaci *aaci = card->private_data;
1037		writel(0, aaci->base + AACI_MAINCR);
1038
1039		snd_card_free(card);
1040		amba_release_regions(dev);
1041	}
1042}
1043
1044static const struct amba_id aaci_ids[] = {
1045	{
1046		.id	= 0x00041041,
1047		.mask	= 0x000fffff,
1048	},
1049	{ 0, 0 },
1050};
1051
1052MODULE_DEVICE_TABLE(amba, aaci_ids);
1053
1054static struct amba_driver aaci_driver = {
1055	.drv		= {
1056		.name	= DRIVER_NAME,
1057		.pm	= &aaci_dev_pm_ops,
1058	},
1059	.probe		= aaci_probe,
1060	.remove		= aaci_remove,
1061	.id_table	= aaci_ids,
1062};
1063
1064module_amba_driver(aaci_driver);
1065
1066MODULE_LICENSE("GPL");
1067MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver");