interface.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * i2sbus driver -- interface register definitions
  4 *
  5 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
  6 */
  7#ifndef __I2SBUS_INTERFACE_H
  8#define __I2SBUS_INTERFACE_H
  9
 10/* i2s bus control registers, at least what we know about them */
 11
 12#define __PAD(m,n) u8 __pad##m[n]
 13#define _PAD(line, n) __PAD(line, n)
 14#define PAD(n) _PAD(__LINE__, (n))
 15struct i2s_interface_regs {
 16	__le32 intr_ctl;	/* 0x00 */
 17	PAD(12);
 18	__le32 serial_format;	/* 0x10 */
 19	PAD(12);
 20	__le32 codec_msg_out;	/* 0x20 */
 21	PAD(12);
 22	__le32 codec_msg_in;	/* 0x30 */
 23	PAD(12);
 24	__le32 frame_count;	/* 0x40 */
 25	PAD(12);
 26	__le32 frame_match;	/* 0x50 */
 27	PAD(12);
 28	__le32 data_word_sizes;	/* 0x60 */
 29	PAD(12);
 30	__le32 peak_level_sel;	/* 0x70 */
 31	PAD(12);
 32	__le32 peak_level_in0;	/* 0x80 */
 33	PAD(12);
 34	__le32 peak_level_in1;	/* 0x90 */
 35	PAD(12);
 36	/* total size: 0x100 bytes */
 37} __packed;
 38
 39/* interrupt register is just a bitfield with
 40 * interrupt enable and pending bits */
 41#define I2S_REG_INTR_CTL		0x00
 42#	define I2S_INT_FRAME_COUNT		(1<<31)
 43#	define I2S_PENDING_FRAME_COUNT		(1<<30)
 44#	define I2S_INT_MESSAGE_FLAG		(1<<29)
 45#	define I2S_PENDING_MESSAGE_FLAG		(1<<28)
 46#	define I2S_INT_NEW_PEAK			(1<<27)
 47#	define I2S_PENDING_NEW_PEAK		(1<<26)
 48#	define I2S_INT_CLOCKS_STOPPED		(1<<25)
 49#	define I2S_PENDING_CLOCKS_STOPPED	(1<<24)
 50#	define I2S_INT_EXTERNAL_SYNC_ERROR	(1<<23)
 51#	define I2S_PENDING_EXTERNAL_SYNC_ERROR	(1<<22)
 52#	define I2S_INT_EXTERNAL_SYNC_OK		(1<<21)
 53#	define I2S_PENDING_EXTERNAL_SYNC_OK	(1<<20)
 54#	define I2S_INT_NEW_SAMPLE_RATE		(1<<19)
 55#	define I2S_PENDING_NEW_SAMPLE_RATE	(1<<18)
 56#	define I2S_INT_STATUS_FLAG		(1<<17)
 57#	define I2S_PENDING_STATUS_FLAG		(1<<16)
 58
 59/* serial format register is more interesting :)
 60 * It contains:
 61 *  - clock source
 62 *  - MClk divisor
 63 *  - SClk divisor
 64 *  - SClk master flag
 65 *  - serial format (sony, i2s 64x, i2s 32x, dav, silabs)
 66 *  - external sample frequency interrupt (don't understand)
 67 *  - external sample frequency
 68 */
 69#define I2S_REG_SERIAL_FORMAT		0x10
 70/* clock source. You get either 18.432, 45.1584 or 49.1520 MHz */
 71#	define I2S_SF_CLOCK_SOURCE_SHIFT	30
 72#	define I2S_SF_CLOCK_SOURCE_MASK		(3<<I2S_SF_CLOCK_SOURCE_SHIFT)
 73#	define I2S_SF_CLOCK_SOURCE_18MHz	(0<<I2S_SF_CLOCK_SOURCE_SHIFT)
 74#	define I2S_SF_CLOCK_SOURCE_45MHz	(1<<I2S_SF_CLOCK_SOURCE_SHIFT)
 75#	define I2S_SF_CLOCK_SOURCE_49MHz	(2<<I2S_SF_CLOCK_SOURCE_SHIFT)
 76/* also, let's define the exact clock speeds here, in Hz */
 77#define I2S_CLOCK_SPEED_18MHz	18432000
 78#define I2S_CLOCK_SPEED_45MHz	45158400
 79#define I2S_CLOCK_SPEED_49MHz	49152000
 80/* MClk is the clock that drives the codec, usually called its 'system clock'.
 81 * It is derived by taking only every 'divisor' tick of the clock.
 82 */
 83#	define I2S_SF_MCLKDIV_SHIFT		24
 84#	define I2S_SF_MCLKDIV_MASK		(0x1F<<I2S_SF_MCLKDIV_SHIFT)
 85#	define I2S_SF_MCLKDIV_1			(0x14<<I2S_SF_MCLKDIV_SHIFT)
 86#	define I2S_SF_MCLKDIV_3			(0x13<<I2S_SF_MCLKDIV_SHIFT)
 87#	define I2S_SF_MCLKDIV_5			(0x12<<I2S_SF_MCLKDIV_SHIFT)
 88#	define I2S_SF_MCLKDIV_14		(0x0E<<I2S_SF_MCLKDIV_SHIFT)
 89#	define I2S_SF_MCLKDIV_OTHER(div)	(((div/2-1)<<I2S_SF_MCLKDIV_SHIFT)&I2S_SF_MCLKDIV_MASK)
 90static inline int i2s_sf_mclkdiv(int div, int *out)
 91{
 92	int d;
 93
 94	switch(div) {
 95	case 1: *out |= I2S_SF_MCLKDIV_1; return 0;
 96	case 3: *out |= I2S_SF_MCLKDIV_3; return 0;
 97	case 5: *out |= I2S_SF_MCLKDIV_5; return 0;
 98	case 14: *out |= I2S_SF_MCLKDIV_14; return 0;
 99	default:
100		if (div%2) return -1;
101		d = div/2-1;
102		if (d == 0x14 || d == 0x13 || d == 0x12 || d == 0x0E)
103			return -1;
104		*out |= I2S_SF_MCLKDIV_OTHER(div);
105		return 0;
106	}
107}
108/* SClk is the clock that drives the i2s wire bus. Note that it is
109 * derived from the MClk above by taking only every 'divisor' tick
110 * of MClk.
111 */
112#	define I2S_SF_SCLKDIV_SHIFT		20
113#	define I2S_SF_SCLKDIV_MASK		(0xF<<I2S_SF_SCLKDIV_SHIFT)
114#	define I2S_SF_SCLKDIV_1			(8<<I2S_SF_SCLKDIV_SHIFT)
115#	define I2S_SF_SCLKDIV_3			(9<<I2S_SF_SCLKDIV_SHIFT)
116#	define I2S_SF_SCLKDIV_OTHER(div)	(((div/2-1)<<I2S_SF_SCLKDIV_SHIFT)&I2S_SF_SCLKDIV_MASK)
117static inline int i2s_sf_sclkdiv(int div, int *out)
118{
119	int d;
120
121	switch(div) {
122	case 1: *out |= I2S_SF_SCLKDIV_1; return 0;
123	case 3: *out |= I2S_SF_SCLKDIV_3; return 0;
124	default:
125		if (div%2) return -1;
126		d = div/2-1;
127		if (d == 8 || d == 9) return -1;
128		*out |= I2S_SF_SCLKDIV_OTHER(div);
129		return 0;
130	}
131}
132#	define I2S_SF_SCLK_MASTER		(1<<19)
133/* serial format is the way the data is put to the i2s wire bus */
134#	define I2S_SF_SERIAL_FORMAT_SHIFT	16
135#	define I2S_SF_SERIAL_FORMAT_MASK	(7<<I2S_SF_SERIAL_FORMAT_SHIFT)
136#	define I2S_SF_SERIAL_FORMAT_SONY	(0<<I2S_SF_SERIAL_FORMAT_SHIFT)
137#	define I2S_SF_SERIAL_FORMAT_I2S_64X	(1<<I2S_SF_SERIAL_FORMAT_SHIFT)
138#	define I2S_SF_SERIAL_FORMAT_I2S_32X	(2<<I2S_SF_SERIAL_FORMAT_SHIFT)
139#	define I2S_SF_SERIAL_FORMAT_I2S_DAV	(4<<I2S_SF_SERIAL_FORMAT_SHIFT)
140#	define I2S_SF_SERIAL_FORMAT_I2S_SILABS	(5<<I2S_SF_SERIAL_FORMAT_SHIFT)
141/* unknown */
142#	define I2S_SF_EXT_SAMPLE_FREQ_INT_SHIFT	12
143#	define I2S_SF_EXT_SAMPLE_FREQ_INT_MASK	(0xF<<I2S_SF_SAMPLE_FREQ_INT_SHIFT)
144/* probably gives external frequency? */
145#	define I2S_SF_EXT_SAMPLE_FREQ_MASK	0xFFF
146
147/* used to send codec messages, but how isn't clear */
148#define I2S_REG_CODEC_MSG_OUT		0x20
149
150/* used to receive codec messages, but how isn't clear */
151#define I2S_REG_CODEC_MSG_IN		0x30
152
153/* frame count reg isn't clear to me yet, but probably useful */
154#define I2S_REG_FRAME_COUNT		0x40
155
156/* program to some value, and get interrupt if frame count reaches it */
157#define I2S_REG_FRAME_MATCH		0x50
158
159/* this register describes how the bus transfers data */
160#define I2S_REG_DATA_WORD_SIZES		0x60
161/* number of interleaved input channels */
162#	define I2S_DWS_NUM_CHANNELS_IN_SHIFT	24
163#	define I2S_DWS_NUM_CHANNELS_IN_MASK	(0x1F<<I2S_DWS_NUM_CHANNELS_IN_SHIFT)
164/* word size of input data */
165#	define I2S_DWS_DATA_IN_SIZE_SHIFT	16
166#	define I2S_DWS_DATA_IN_16BIT		(0<<I2S_DWS_DATA_IN_SIZE_SHIFT)
167#	define I2S_DWS_DATA_IN_24BIT		(3<<I2S_DWS_DATA_IN_SIZE_SHIFT)
168/* number of interleaved output channels */
169#	define I2S_DWS_NUM_CHANNELS_OUT_SHIFT	8
170#	define I2S_DWS_NUM_CHANNELS_OUT_MASK	(0x1F<<I2S_DWS_NUM_CHANNELS_OUT_SHIFT)
171/* word size of output data */
172#	define I2S_DWS_DATA_OUT_SIZE_SHIFT	0
173#	define I2S_DWS_DATA_OUT_16BIT		(0<<I2S_DWS_DATA_OUT_SIZE_SHIFT)
174#	define I2S_DWS_DATA_OUT_24BIT		(3<<I2S_DWS_DATA_OUT_SIZE_SHIFT)
175
176
177/* unknown */
178#define I2S_REG_PEAK_LEVEL_SEL		0x70
179
180/* unknown */
181#define I2S_REG_PEAK_LEVEL_IN0		0x80
182
183/* unknown */
184#define I2S_REG_PEAK_LEVEL_IN1		0x90
185
186#endif /* __I2SBUS_INTERFACE_H */