generic-chip.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Library implementing the most common irq chip callback functions
  4 *
  5 * Copyright (C) 2011, Thomas Gleixner
  6 */
  7#include <linux/io.h>
  8#include <linux/irq.h>
  9#include <linux/slab.h>
 10#include <linux/export.h>
 11#include <linux/irqdomain.h>
 12#include <linux/interrupt.h>
 13#include <linux/kernel_stat.h>
 14#include <linux/syscore_ops.h>
 15
 16#include "internals.h"
 17
 18static LIST_HEAD(gc_list);
 19static DEFINE_RAW_SPINLOCK(gc_lock);
 20
 21/**
 22 * irq_gc_noop - NOOP function
 23 * @d: irq_data
 24 */
 25void irq_gc_noop(struct irq_data *d)
 26{
 27}
 28EXPORT_SYMBOL_GPL(irq_gc_noop);
 29
 30/**
 31 * irq_gc_mask_disable_reg - Mask chip via disable register
 32 * @d: irq_data
 33 *
 34 * Chip has separate enable/disable registers instead of a single mask
 35 * register.
 36 */
 37void irq_gc_mask_disable_reg(struct irq_data *d)
 38{
 39	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 40	struct irq_chip_type *ct = irq_data_get_chip_type(d);
 41	u32 mask = d->mask;
 42
 43	guard(raw_spinlock)(&gc->lock);
 44	irq_reg_writel(gc, mask, ct->regs.disable);
 45	*ct->mask_cache &= ~mask;
 46}
 47EXPORT_SYMBOL_GPL(irq_gc_mask_disable_reg);
 48
 49/**
 50 * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
 51 * @d: irq_data
 52 *
 53 * Chip has a single mask register. Values of this register are cached
 54 * and protected by gc->lock
 55 */
 56void irq_gc_mask_set_bit(struct irq_data *d)
 57{
 58	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 59	struct irq_chip_type *ct = irq_data_get_chip_type(d);
 60	u32 mask = d->mask;
 61
 62	guard(raw_spinlock)(&gc->lock);
 63	*ct->mask_cache |= mask;
 64	irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
 65}
 66EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
 67
 68/**
 69 * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
 70 * @d: irq_data
 71 *
 72 * Chip has a single mask register. Values of this register are cached
 73 * and protected by gc->lock
 74 */
 75void irq_gc_mask_clr_bit(struct irq_data *d)
 76{
 77	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 78	struct irq_chip_type *ct = irq_data_get_chip_type(d);
 79	u32 mask = d->mask;
 80
 81	guard(raw_spinlock)(&gc->lock);
 82	*ct->mask_cache &= ~mask;
 83	irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
 84}
 85EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);
 86
 87/**
 88 * irq_gc_unmask_enable_reg - Unmask chip via enable register
 89 * @d: irq_data
 90 *
 91 * Chip has separate enable/disable registers instead of a single mask
 92 * register.
 93 */
 94void irq_gc_unmask_enable_reg(struct irq_data *d)
 95{
 96	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 97	struct irq_chip_type *ct = irq_data_get_chip_type(d);
 98	u32 mask = d->mask;
 99
100	guard(raw_spinlock)(&gc->lock);
101	irq_reg_writel(gc, mask, ct->regs.enable);
102	*ct->mask_cache |= mask;
103}
104EXPORT_SYMBOL_GPL(irq_gc_unmask_enable_reg);
105
106/**
107 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
108 * @d: irq_data
109 */
110void irq_gc_ack_set_bit(struct irq_data *d)
111{
112	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
113	struct irq_chip_type *ct = irq_data_get_chip_type(d);
114	u32 mask = d->mask;
115
116	guard(raw_spinlock)(&gc->lock);
117	irq_reg_writel(gc, mask, ct->regs.ack);
118}
119EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);
120
121/**
122 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
123 * @d: irq_data
124 */
125void irq_gc_ack_clr_bit(struct irq_data *d)
126{
127	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
128	struct irq_chip_type *ct = irq_data_get_chip_type(d);
129	u32 mask = ~d->mask;
130
131	guard(raw_spinlock)(&gc->lock);
132	irq_reg_writel(gc, mask, ct->regs.ack);
133}
134
135/**
136 * irq_gc_mask_disable_and_ack_set - Mask and ack pending interrupt
137 * @d: irq_data
138 *
139 * This generic implementation of the irq_mask_ack method is for chips
140 * with separate enable/disable registers instead of a single mask
141 * register and where a pending interrupt is acknowledged by setting a
142 * bit.
143 *
144 * Note: This is the only permutation currently used.  Similar generic
145 * functions should be added here if other permutations are required.
146 */
147void irq_gc_mask_disable_and_ack_set(struct irq_data *d)
148{
149	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
150	struct irq_chip_type *ct = irq_data_get_chip_type(d);
151	u32 mask = d->mask;
152
153	guard(raw_spinlock)(&gc->lock);
154	irq_reg_writel(gc, mask, ct->regs.disable);
155	*ct->mask_cache &= ~mask;
156	irq_reg_writel(gc, mask, ct->regs.ack);
157}
158EXPORT_SYMBOL_GPL(irq_gc_mask_disable_and_ack_set);
159
160/**
161 * irq_gc_eoi - EOI interrupt
162 * @d: irq_data
163 */
164void irq_gc_eoi(struct irq_data *d)
165{
166	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
167	struct irq_chip_type *ct = irq_data_get_chip_type(d);
168	u32 mask = d->mask;
169
170	guard(raw_spinlock)(&gc->lock);
171	irq_reg_writel(gc, mask, ct->regs.eoi);
172}
173
174/**
175 * irq_gc_set_wake - Set/clr wake bit for an interrupt
176 * @d:  irq_data
177 * @on: Indicates whether the wake bit should be set or cleared
178 *
179 * For chips where the wake from suspend functionality is not
180 * configured in a separate register and the wakeup active state is
181 * just stored in a bitmask.
182 */
183int irq_gc_set_wake(struct irq_data *d, unsigned int on)
184{
185	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
186	u32 mask = d->mask;
187
188	if (!(mask & gc->wake_enabled))
189		return -EINVAL;
190
191	guard(raw_spinlock)(&gc->lock);
192	if (on)
193		gc->wake_active |= mask;
194	else
195		gc->wake_active &= ~mask;
196	return 0;
197}
198EXPORT_SYMBOL_GPL(irq_gc_set_wake);
199
200static u32 irq_readl_be(void __iomem *addr)
201{
202	return ioread32be(addr);
203}
204
205static void irq_writel_be(u32 val, void __iomem *addr)
206{
207	iowrite32be(val, addr);
208}
209
210void irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
211			   int num_ct, unsigned int irq_base,
212			   void __iomem *reg_base, irq_flow_handler_t handler)
213{
214	struct irq_chip_type *ct = gc->chip_types;
215	int i;
216
217	raw_spin_lock_init(&gc->lock);
218	gc->num_ct = num_ct;
219	gc->irq_base = irq_base;
220	gc->reg_base = reg_base;
221	for (i = 0; i < num_ct; i++)
222		ct[i].chip.name = name;
223	gc->chip_types->handler = handler;
224}
225
226/**
227 * irq_alloc_generic_chip - Allocate a generic chip and initialize it
228 * @name:	Name of the irq chip
229 * @num_ct:	Number of irq_chip_type instances associated with this
230 * @irq_base:	Interrupt base nr for this chip
231 * @reg_base:	Register base address (virtual)
232 * @handler:	Default flow handler associated with this chip
233 *
234 * Returns an initialized irq_chip_generic structure. The chip defaults
235 * to the primary (index 0) irq_chip_type and @handler
236 */
237struct irq_chip_generic *
238irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
239		       void __iomem *reg_base, irq_flow_handler_t handler)
240{
241	struct irq_chip_generic *gc;
242
243	gc = kzalloc(struct_size(gc, chip_types, num_ct), GFP_KERNEL);
244	if (gc) {
245		irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
246				      handler);
247	}
248	return gc;
249}
250EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
251
252static void
253irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
254{
255	struct irq_chip_type *ct = gc->chip_types;
256	u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
257	int i;
258
259	for (i = 0; i < gc->num_ct; i++) {
260		if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
261			mskptr = &ct[i].mask_cache_priv;
262			mskreg = ct[i].regs.mask;
263		}
264		ct[i].mask_cache = mskptr;
265		if (flags & IRQ_GC_INIT_MASK_CACHE)
266			*mskptr = irq_reg_readl(gc, mskreg);
267	}
268}
269
270/**
271 * irq_domain_alloc_generic_chips - Allocate generic chips for an irq domain
272 * @d:		irq domain for which to allocate chips
273 * @info:	Generic chip information
274 *
275 * Return: 0 on success, negative error code on failure
276 */
277int irq_domain_alloc_generic_chips(struct irq_domain *d,
278				   const struct irq_domain_chip_generic_info *info)
279{
280	struct irq_domain_chip_generic *dgc;
281	struct irq_chip_generic *gc;
282	int numchips, i;
283	size_t dgc_sz;
284	size_t gc_sz;
285	size_t sz;
286	void *tmp;
287	int ret;
288
289	if (d->gc)
290		return -EBUSY;
291
292	numchips = DIV_ROUND_UP(d->revmap_size, info->irqs_per_chip);
293	if (!numchips)
294		return -EINVAL;
295
296	/* Allocate a pointer, generic chip and chiptypes for each chip */
297	gc_sz = struct_size(gc, chip_types, info->num_ct);
298	dgc_sz = struct_size(dgc, gc, numchips);
299	sz = dgc_sz + numchips * gc_sz;
300
301	tmp = dgc = kzalloc(sz, GFP_KERNEL);
302	if (!dgc)
303		return -ENOMEM;
304	dgc->irqs_per_chip = info->irqs_per_chip;
305	dgc->num_chips = numchips;
306	dgc->irq_flags_to_set = info->irq_flags_to_set;
307	dgc->irq_flags_to_clear = info->irq_flags_to_clear;
308	dgc->gc_flags = info->gc_flags;
309	dgc->exit = info->exit;
310	d->gc = dgc;
311
312	/* Calc pointer to the first generic chip */
313	tmp += dgc_sz;
314	for (i = 0; i < numchips; i++) {
315		/* Store the pointer to the generic chip */
316		dgc->gc[i] = gc = tmp;
317		irq_init_generic_chip(gc, info->name, info->num_ct,
318				      i * dgc->irqs_per_chip, NULL,
319				      info->handler);
320
321		gc->domain = d;
322		if (dgc->gc_flags & IRQ_GC_BE_IO) {
323			gc->reg_readl = &irq_readl_be;
324			gc->reg_writel = &irq_writel_be;
325		}
326
327		if (info->init) {
328			ret = info->init(gc);
329			if (ret)
330				goto err;
331		}
332
333		scoped_guard (raw_spinlock_irqsave, &gc_lock)
334			list_add_tail(&gc->list, &gc_list);
335		/* Calc pointer to the next generic chip */
336		tmp += gc_sz;
337	}
338	return 0;
339
340err:
341	while (i--) {
342		if (dgc->exit)
343			dgc->exit(dgc->gc[i]);
344		irq_remove_generic_chip(dgc->gc[i], ~0U, 0, 0);
345	}
346	d->gc = NULL;
347	kfree(dgc);
348	return ret;
349}
350EXPORT_SYMBOL_GPL(irq_domain_alloc_generic_chips);
351
352/**
353 * irq_domain_remove_generic_chips - Remove generic chips from an irq domain
354 * @d: irq domain for which generic chips are to be removed
355 */
356void irq_domain_remove_generic_chips(struct irq_domain *d)
357{
358	struct irq_domain_chip_generic *dgc = d->gc;
359	unsigned int i;
360
361	if (!dgc)
362		return;
363
364	for (i = 0; i < dgc->num_chips; i++) {
365		if (dgc->exit)
366			dgc->exit(dgc->gc[i]);
367		irq_remove_generic_chip(dgc->gc[i], ~0U, 0, 0);
368	}
369	d->gc = NULL;
370	kfree(dgc);
371}
372EXPORT_SYMBOL_GPL(irq_domain_remove_generic_chips);
373
374/**
375 * __irq_alloc_domain_generic_chips - Allocate generic chips for an irq domain
376 * @d:			irq domain for which to allocate chips
377 * @irqs_per_chip:	Number of interrupts each chip handles (max 32)
378 * @num_ct:		Number of irq_chip_type instances associated with this
379 * @name:		Name of the irq chip
380 * @handler:		Default flow handler associated with these chips
381 * @clr:		IRQ_* bits to clear in the mapping function
382 * @set:		IRQ_* bits to set in the mapping function
383 * @gcflags:		Generic chip specific setup flags
384 */
385int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
386				     int num_ct, const char *name,
387				     irq_flow_handler_t handler,
388				     unsigned int clr, unsigned int set,
389				     enum irq_gc_flags gcflags)
390{
391	struct irq_domain_chip_generic_info info = {
392		.irqs_per_chip		= irqs_per_chip,
393		.num_ct			= num_ct,
394		.name			= name,
395		.handler		= handler,
396		.irq_flags_to_clear	= clr,
397		.irq_flags_to_set	= set,
398		.gc_flags		= gcflags,
399	};
400
401	return irq_domain_alloc_generic_chips(d, &info);
402}
403EXPORT_SYMBOL_GPL(__irq_alloc_domain_generic_chips);
404
405static struct irq_chip_generic *
406__irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
407{
408	struct irq_domain_chip_generic *dgc = d->gc;
409	int idx;
410
411	if (!dgc)
412		return ERR_PTR(-ENODEV);
413	idx = hw_irq / dgc->irqs_per_chip;
414	if (idx >= dgc->num_chips)
415		return ERR_PTR(-EINVAL);
416	return dgc->gc[idx];
417}
418
419/**
420 * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
421 * @d:			irq domain pointer
422 * @hw_irq:		Hardware interrupt number
423 */
424struct irq_chip_generic *
425irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
426{
427	struct irq_chip_generic *gc = __irq_get_domain_generic_chip(d, hw_irq);
428
429	return !IS_ERR(gc) ? gc : NULL;
430}
431EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
432
433/*
434 * Separate lockdep classes for interrupt chip which can nest irq_desc
435 * lock and request mutex.
436 */
437static struct lock_class_key irq_nested_lock_class;
438static struct lock_class_key irq_nested_request_class;
439
440/*
441 * irq_map_generic_chip - Map a generic chip for an irq domain
442 */
443int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
444			 irq_hw_number_t hw_irq)
445{
446	struct irq_data *data = irq_domain_get_irq_data(d, virq);
447	struct irq_domain_chip_generic *dgc = d->gc;
448	struct irq_chip_generic *gc;
449	struct irq_chip_type *ct;
450	struct irq_chip *chip;
451	int idx;
452
453	gc = __irq_get_domain_generic_chip(d, hw_irq);
454	if (IS_ERR(gc))
455		return PTR_ERR(gc);
456
457	idx = hw_irq % dgc->irqs_per_chip;
458
459	if (test_bit(idx, &gc->unused))
460		return -ENOTSUPP;
461
462	if (test_bit(idx, &gc->installed))
463		return -EBUSY;
464
465	ct = gc->chip_types;
466	chip = &ct->chip;
467
468	/* We only init the cache for the first mapping of a generic chip */
469	if (!gc->installed) {
470		guard(raw_spinlock_irqsave)(&gc->lock);
471		irq_gc_init_mask_cache(gc, dgc->gc_flags);
472	}
473
474	/* Mark the interrupt as installed */
475	set_bit(idx, &gc->installed);
476
477	if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
478		irq_set_lockdep_class(virq, &irq_nested_lock_class,
479				      &irq_nested_request_class);
480
481	if (chip->irq_calc_mask)
482		chip->irq_calc_mask(data);
483	else
484		data->mask = 1 << idx;
485
486	irq_domain_set_info(d, virq, hw_irq, chip, gc, ct->handler, NULL, NULL);
487	irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
488	return 0;
489}
490
491void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
492{
493	struct irq_data *data = irq_domain_get_irq_data(d, virq);
494	struct irq_domain_chip_generic *dgc = d->gc;
495	unsigned int hw_irq = data->hwirq;
496	struct irq_chip_generic *gc;
497	int irq_idx;
498
499	gc = irq_get_domain_generic_chip(d, hw_irq);
500	if (!gc)
501		return;
502
503	irq_idx = hw_irq % dgc->irqs_per_chip;
504
505	clear_bit(irq_idx, &gc->installed);
506	irq_domain_set_info(d, virq, hw_irq, &no_irq_chip, NULL, NULL, NULL,
507			    NULL);
508
509}
510
511const struct irq_domain_ops irq_generic_chip_ops = {
512	.map	= irq_map_generic_chip,
513	.unmap  = irq_unmap_generic_chip,
514	.xlate	= irq_domain_xlate_onetwocell,
515};
516EXPORT_SYMBOL_GPL(irq_generic_chip_ops);
517
518/**
519 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
520 * @gc:		Generic irq chip holding all data
521 * @msk:	Bitmask holding the irqs to initialize relative to gc->irq_base
522 * @flags:	Flags for initialization
523 * @clr:	IRQ_* bits to clear
524 * @set:	IRQ_* bits to set
525 *
526 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
527 * initializes all interrupts to the primary irq_chip_type and its
528 * associated handler.
529 */
530void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
531			    enum irq_gc_flags flags, unsigned int clr,
532			    unsigned int set)
533{
534	struct irq_chip_type *ct = gc->chip_types;
535	struct irq_chip *chip = &ct->chip;
536	unsigned int i;
537
538	scoped_guard (raw_spinlock, &gc_lock)
539		list_add_tail(&gc->list, &gc_list);
540
541	irq_gc_init_mask_cache(gc, flags);
542
543	for (i = gc->irq_base; msk; msk >>= 1, i++) {
544		if (!(msk & 0x01))
545			continue;
546
547		if (flags & IRQ_GC_INIT_NESTED_LOCK)
548			irq_set_lockdep_class(i, &irq_nested_lock_class,
549					      &irq_nested_request_class);
550
551		if (!(flags & IRQ_GC_NO_MASK)) {
552			struct irq_data *d = irq_get_irq_data(i);
553
554			if (chip->irq_calc_mask)
555				chip->irq_calc_mask(d);
556			else
557				d->mask = 1 << (i - gc->irq_base);
558		}
559		irq_set_chip_and_handler(i, chip, ct->handler);
560		irq_set_chip_data(i, gc);
561		irq_modify_status(i, clr, set);
562	}
563	gc->irq_cnt = i - gc->irq_base;
564}
565EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
566
567/**
568 * irq_setup_alt_chip - Switch to alternative chip
569 * @d:		irq_data for this interrupt
570 * @type:	Flow type to be initialized
571 *
572 * Only to be called from chip->irq_set_type() callbacks.
573 */
574int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
575{
576	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
577	struct irq_chip_type *ct = gc->chip_types;
578	unsigned int i;
579
580	for (i = 0; i < gc->num_ct; i++, ct++) {
581		if (ct->type & type) {
582			d->chip = &ct->chip;
583			irq_data_to_desc(d)->handle_irq = ct->handler;
584			return 0;
585		}
586	}
587	return -EINVAL;
588}
589EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
590
591/**
592 * irq_remove_generic_chip - Remove a chip
593 * @gc:		Generic irq chip holding all data
594 * @msk:	Bitmask holding the irqs to initialize relative to gc->irq_base
595 * @clr:	IRQ_* bits to clear
596 * @set:	IRQ_* bits to set
597 *
598 * Remove up to 32 interrupts starting from gc->irq_base.
599 */
600void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
601			     unsigned int clr, unsigned int set)
602{
603	unsigned int i, virq;
604
605	scoped_guard (raw_spinlock, &gc_lock)
606		list_del(&gc->list);
607
608	for (i = 0; msk; msk >>= 1, i++) {
609		if (!(msk & 0x01))
610			continue;
611
612		/*
613		 * Interrupt domain based chips store the base hardware
614		 * interrupt number in gc::irq_base. Otherwise gc::irq_base
615		 * contains the base Linux interrupt number.
616		 */
617		if (gc->domain) {
618			virq = irq_find_mapping(gc->domain, gc->irq_base + i);
619			if (!virq)
620				continue;
621		} else {
622			virq = gc->irq_base + i;
623		}
624
625		/* Remove handler first. That will mask the irq line */
626		irq_set_handler(virq, NULL);
627		irq_set_chip(virq, &no_irq_chip);
628		irq_set_chip_data(virq, NULL);
629		irq_modify_status(virq, clr, set);
630	}
631}
632EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
633
634static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc)
635{
636	unsigned int virq;
637
638	if (!gc->domain)
639		return irq_get_irq_data(gc->irq_base);
640
641	/*
642	 * We don't know which of the irqs has been actually
643	 * installed. Use the first one.
644	 */
645	if (!gc->installed)
646		return NULL;
647
648	virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
649	return virq ? irq_get_irq_data(virq) : NULL;
650}
651
652#ifdef CONFIG_PM
653static int irq_gc_suspend(void *data)
654{
655	struct irq_chip_generic *gc;
656
657	list_for_each_entry(gc, &gc_list, list) {
658		struct irq_chip_type *ct = gc->chip_types;
659
660		if (ct->chip.irq_suspend) {
661			struct irq_data *data = irq_gc_get_irq_data(gc);
662
663			if (data)
664				ct->chip.irq_suspend(data);
665		}
666
667		if (gc->suspend)
668			gc->suspend(gc);
669	}
670	return 0;
671}
672
673static void irq_gc_resume(void *data)
674{
675	struct irq_chip_generic *gc;
676
677	list_for_each_entry(gc, &gc_list, list) {
678		struct irq_chip_type *ct = gc->chip_types;
679
680		if (gc->resume)
681			gc->resume(gc);
682
683		if (ct->chip.irq_resume) {
684			struct irq_data *data = irq_gc_get_irq_data(gc);
685
686			if (data)
687				ct->chip.irq_resume(data);
688		}
689	}
690}
691#else
692#define irq_gc_suspend NULL
693#define irq_gc_resume NULL
694#endif
695
696static void irq_gc_shutdown(void *data)
697{
698	struct irq_chip_generic *gc;
699
700	list_for_each_entry(gc, &gc_list, list) {
701		struct irq_chip_type *ct = gc->chip_types;
702
703		if (ct->chip.irq_pm_shutdown) {
704			struct irq_data *data = irq_gc_get_irq_data(gc);
705
706			if (data)
707				ct->chip.irq_pm_shutdown(data);
708		}
709	}
710}
711
712static const struct syscore_ops irq_gc_syscore_ops = {
713	.suspend = irq_gc_suspend,
714	.resume = irq_gc_resume,
715	.shutdown = irq_gc_shutdown,
716};
717
718static struct syscore irq_gc_syscore = {
719	.ops = &irq_gc_syscore_ops,
720};
721
722static int __init irq_gc_init_ops(void)
723{
724	register_syscore(&irq_gc_syscore);
725	return 0;
726}
727device_initcall(irq_gc_init_ops);