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amdgpu_drm.h
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linux-6.19.14/include/uapi/drm/amdgpu_drm.h
1/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32#ifndef __AMDGPU_DRM_H__ 33#define __AMDGPU_DRM_H__ 34 35#include "drm.h" 36 37#if defined(__cplusplus) 38extern "C" { 39#endif 40 41#define DRM_AMDGPU_GEM_CREATE 0x00 42#define DRM_AMDGPU_GEM_MMAP 0x01 43#define DRM_AMDGPU_CTX 0x02 44#define DRM_AMDGPU_BO_LIST 0x03 45#define DRM_AMDGPU_CS 0x04 46#define DRM_AMDGPU_INFO 0x05 47#define DRM_AMDGPU_GEM_METADATA 0x06 48#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49#define DRM_AMDGPU_GEM_VA 0x08 50#define DRM_AMDGPU_WAIT_CS 0x09 51#define DRM_AMDGPU_GEM_OP 0x10 52#define DRM_AMDGPU_GEM_USERPTR 0x11 53#define DRM_AMDGPU_WAIT_FENCES 0x12 54#define DRM_AMDGPU_VM 0x13 55#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 56#define DRM_AMDGPU_SCHED 0x15 57#define DRM_AMDGPU_USERQ 0x16 58#define DRM_AMDGPU_USERQ_SIGNAL 0x17 59#define DRM_AMDGPU_USERQ_WAIT 0x18 60#define DRM_AMDGPU_GEM_LIST_HANDLES 0x19 61 62#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 63#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 64#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 65#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 66#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 67#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 68#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 69#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 70#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 71#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 72#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 73#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 74#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 75#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 76#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 77#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 78#define DRM_IOCTL_AMDGPU_USERQ DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq) 79#define DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal) 80#define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait) 81#define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles) 82 83/** 84 * DOC: memory domains 85 * 86 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 87 * Memory in this pool could be swapped out to disk if there is pressure. 88 * 89 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 90 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 91 * pages of system memory, allows GPU access system memory in a linearized 92 * fashion. 93 * 94 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 95 * carved out by the BIOS. 96 * 97 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 98 * across shader threads. 99 * 100 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 101 * execution of all the waves on a device. 102 * 103 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 104 * for appending data. 105 * 106 * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for 107 * signalling user mode queues. 108 */ 109#define AMDGPU_GEM_DOMAIN_CPU 0x1 110#define AMDGPU_GEM_DOMAIN_GTT 0x2 111#define AMDGPU_GEM_DOMAIN_VRAM 0x4 112#define AMDGPU_GEM_DOMAIN_GDS 0x8 113#define AMDGPU_GEM_DOMAIN_GWS 0x10 114#define AMDGPU_GEM_DOMAIN_OA 0x20 115#define AMDGPU_GEM_DOMAIN_DOORBELL 0x40 116#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 117 AMDGPU_GEM_DOMAIN_GTT | \ 118 AMDGPU_GEM_DOMAIN_VRAM | \ 119 AMDGPU_GEM_DOMAIN_GDS | \ 120 AMDGPU_GEM_DOMAIN_GWS | \ 121 AMDGPU_GEM_DOMAIN_OA | \ 122 AMDGPU_GEM_DOMAIN_DOORBELL) 123 124/* Flag that CPU access will be required for the case of VRAM domain */ 125#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 126/* Flag that CPU access will not work, this VRAM domain is invisible */ 127#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 128/* Flag that USWC attributes should be used for GTT */ 129#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 130/* Flag that the memory should be in VRAM and cleared */ 131#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 132/* Flag that allocating the BO should use linear VRAM */ 133#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 134/* Flag that BO is always valid in this VM */ 135#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 136/* Flag that BO sharing will be explicitly synchronized */ 137#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 138/* Flag that indicates allocating MQD gart on GFX9, where the mtype 139 * for the second page onward should be set to NC. It should never 140 * be used by user space applications. 141 */ 142#define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 143/* Flag that BO may contain sensitive data that must be wiped before 144 * releasing the memory 145 */ 146#define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 147/* Flag that BO will be encrypted and that the TMZ bit should be 148 * set in the PTEs when mapping this buffer via GPUVM or 149 * accessing it with various hw blocks 150 */ 151#define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 152/* Flag that BO will be used only in preemptible context, which does 153 * not require GTT memory accounting 154 */ 155#define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) 156/* Flag that BO can be discarded under memory pressure without keeping the 157 * content. 158 */ 159#define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12) 160/* Flag that BO is shared coherently between multiple devices or CPU threads. 161 * May depend on GPU instructions to flush caches to system scope explicitly. 162 * 163 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 164 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 165 */ 166#define AMDGPU_GEM_CREATE_COHERENT (1 << 13) 167/* Flag that BO should not be cached by GPU. Coherent without having to flush 168 * GPU caches explicitly 169 * 170 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 171 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 172 */ 173#define AMDGPU_GEM_CREATE_UNCACHED (1 << 14) 174/* Flag that BO should be coherent across devices when using device-level 175 * atomics. May depend on GPU instructions to flush caches to device scope 176 * explicitly, promoting them to system scope automatically. 177 * 178 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 179 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 180 */ 181#define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15) 182/* Set PTE.D and recompress during GTT->VRAM moves according to TILING flags. */ 183#define AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16) 184 185struct drm_amdgpu_gem_create_in { 186 /** the requested memory size */ 187 __u64 bo_size; 188 /** physical start_addr alignment in bytes for some HW requirements */ 189 __u64 alignment; 190 /** the requested memory domains */ 191 __u64 domains; 192 /** allocation flags */ 193 __u64 domain_flags; 194}; 195 196struct drm_amdgpu_gem_create_out { 197 /** returned GEM object handle */ 198 __u32 handle; 199 __u32 _pad; 200}; 201 202union drm_amdgpu_gem_create { 203 struct drm_amdgpu_gem_create_in in; 204 struct drm_amdgpu_gem_create_out out; 205}; 206 207/** Opcode to create new residency list. */ 208#define AMDGPU_BO_LIST_OP_CREATE 0 209/** Opcode to destroy previously created residency list */ 210#define AMDGPU_BO_LIST_OP_DESTROY 1 211/** Opcode to update resource information in the list */ 212#define AMDGPU_BO_LIST_OP_UPDATE 2 213 214struct drm_amdgpu_bo_list_in { 215 /** Type of operation */ 216 __u32 operation; 217 /** Handle of list or 0 if we want to create one */ 218 __u32 list_handle; 219 /** Number of BOs in list */ 220 __u32 bo_number; 221 /** Size of each element describing BO */ 222 __u32 bo_info_size; 223 /** Pointer to array describing BOs */ 224 __u64 bo_info_ptr; 225}; 226 227struct drm_amdgpu_bo_list_entry { 228 /** Handle of BO */ 229 __u32 bo_handle; 230 /** New (if specified) BO priority to be used during migration */ 231 __u32 bo_priority; 232}; 233 234struct drm_amdgpu_bo_list_out { 235 /** Handle of resource list */ 236 __u32 list_handle; 237 __u32 _pad; 238}; 239 240union drm_amdgpu_bo_list { 241 struct drm_amdgpu_bo_list_in in; 242 struct drm_amdgpu_bo_list_out out; 243}; 244 245/* context related */ 246#define AMDGPU_CTX_OP_ALLOC_CTX 1 247#define AMDGPU_CTX_OP_FREE_CTX 2 248#define AMDGPU_CTX_OP_QUERY_STATE 3 249#define AMDGPU_CTX_OP_QUERY_STATE2 4 250#define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 251#define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 252 253/* GPU reset status */ 254#define AMDGPU_CTX_NO_RESET 0 255/* this the context caused it */ 256#define AMDGPU_CTX_GUILTY_RESET 1 257/* some other context caused it */ 258#define AMDGPU_CTX_INNOCENT_RESET 2 259/* unknown cause */ 260#define AMDGPU_CTX_UNKNOWN_RESET 3 261 262/* indicate gpu reset occurred after ctx created */ 263#define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 264/* indicate vram lost occurred after ctx created */ 265#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 266/* indicate some job from this context once cause gpu hang */ 267#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 268/* indicate some errors are detected by RAS */ 269#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 270#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 271/* indicate that the reset hasn't completed yet */ 272#define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5) 273 274/* Context priority level */ 275#define AMDGPU_CTX_PRIORITY_UNSET -2048 276#define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 277#define AMDGPU_CTX_PRIORITY_LOW -512 278#define AMDGPU_CTX_PRIORITY_NORMAL 0 279/* 280 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 281 * CAP_SYS_NICE or DRM_MASTER 282*/ 283#define AMDGPU_CTX_PRIORITY_HIGH 512 284#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 285 286/* select a stable profiling pstate for perfmon tools */ 287#define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf 288#define AMDGPU_CTX_STABLE_PSTATE_NONE 0 289#define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 290#define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 291#define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 292#define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 293 294struct drm_amdgpu_ctx_in { 295 /** AMDGPU_CTX_OP_* */ 296 __u32 op; 297 /** Flags */ 298 __u32 flags; 299 __u32 ctx_id; 300 /** AMDGPU_CTX_PRIORITY_* */ 301 __s32 priority; 302}; 303 304union drm_amdgpu_ctx_out { 305 struct { 306 __u32 ctx_id; 307 __u32 _pad; 308 } alloc; 309 310 struct { 311 /** For future use, no flags defined so far */ 312 __u64 flags; 313 /** Number of resets caused by this context so far. */ 314 __u32 hangs; 315 /** Reset status since the last call of the ioctl. */ 316 __u32 reset_status; 317 } state; 318 319 struct { 320 __u32 flags; 321 __u32 _pad; 322 } pstate; 323}; 324 325union drm_amdgpu_ctx { 326 struct drm_amdgpu_ctx_in in; 327 union drm_amdgpu_ctx_out out; 328}; 329 330/* user queue IOCTL operations */ 331#define AMDGPU_USERQ_OP_CREATE 1 332#define AMDGPU_USERQ_OP_FREE 2 333 334/* queue priority levels */ 335/* low < normal low < normal high < high */ 336#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK 0x3 337#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT 0 338#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW 0 339#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW 1 340#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH 2 341#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH 3 /* admin only */ 342/* for queues that need access to protected content */ 343#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE (1 << 2) 344 345/* 346 * This structure is a container to pass input configuration 347 * info for all supported userqueue related operations. 348 * For operation AMDGPU_USERQ_OP_CREATE: user is expected 349 * to set all fields, excep the parameter 'queue_id'. 350 * For operation AMDGPU_USERQ_OP_FREE: the only input parameter expected 351 * to be set is 'queue_id', eveything else is ignored. 352 */ 353struct drm_amdgpu_userq_in { 354 /** AMDGPU_USERQ_OP_* */ 355 __u32 op; 356 /** Queue id passed for operation USERQ_OP_FREE */ 357 __u32 queue_id; 358 /** the target GPU engine to execute workload (AMDGPU_HW_IP_*) */ 359 __u32 ip_type; 360 /** 361 * @doorbell_handle: the handle of doorbell GEM object 362 * associated with this userqueue client. 363 */ 364 __u32 doorbell_handle; 365 /** 366 * @doorbell_offset: 32-bit offset of the doorbell in the doorbell bo. 367 * Kernel will generate absolute doorbell offset using doorbell_handle 368 * and doorbell_offset in the doorbell bo. 369 */ 370 __u32 doorbell_offset; 371 /** 372 * @flags: flags used for queue parameters 373 */ 374 __u32 flags; 375 /** 376 * @queue_va: Virtual address of the GPU memory which holds the queue 377 * object. The queue holds the workload packets. 378 */ 379 __u64 queue_va; 380 /** 381 * @queue_size: Size of the queue in bytes, this needs to be 256-byte 382 * aligned. 383 */ 384 __u64 queue_size; 385 /** 386 * @rptr_va : Virtual address of the GPU memory which holds the ring RPTR. 387 * This object must be at least 8 byte in size and aligned to 8-byte offset. 388 */ 389 __u64 rptr_va; 390 /** 391 * @wptr_va : Virtual address of the GPU memory which holds the ring WPTR. 392 * This object must be at least 8 byte in size and aligned to 8-byte offset. 393 * 394 * Queue, RPTR and WPTR can come from the same object, as long as the size 395 * and alignment related requirements are met. 396 */ 397 __u64 wptr_va; 398 /** 399 * @mqd: MQD (memory queue descriptor) is a set of parameters which allow 400 * the GPU to uniquely define and identify a usermode queue. 401 * 402 * MQD data can be of different size for different GPU IP/engine and 403 * their respective versions/revisions, so this points to a __u64 * 404 * which holds IP specific MQD of this usermode queue. 405 */ 406 __u64 mqd; 407 /** 408 * @size: size of MQD data in bytes, it must match the MQD structure 409 * size of the respective engine/revision defined in UAPI for ex, for 410 * gfx11 workloads, size = sizeof(drm_amdgpu_userq_mqd_gfx11). 411 */ 412 __u64 mqd_size; 413}; 414 415/* The structure to carry output of userqueue ops */ 416struct drm_amdgpu_userq_out { 417 /** 418 * For operation AMDGPU_USERQ_OP_CREATE: This field contains a unique 419 * queue ID to represent the newly created userqueue in the system, otherwise 420 * it should be ignored. 421 */ 422 __u32 queue_id; 423 __u32 _pad; 424}; 425 426union drm_amdgpu_userq { 427 struct drm_amdgpu_userq_in in; 428 struct drm_amdgpu_userq_out out; 429}; 430 431/* GFX V11 IP specific MQD parameters */ 432struct drm_amdgpu_userq_mqd_gfx11 { 433 /** 434 * @shadow_va: Virtual address of the GPU memory to hold the shadow buffer. 435 * Use AMDGPU_INFO_IOCTL to find the exact size of the object. 436 */ 437 __u64 shadow_va; 438 /** 439 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer. 440 * Use AMDGPU_INFO_IOCTL to find the exact size of the object. 441 */ 442 __u64 csa_va; 443}; 444 445/* GFX V11 SDMA IP specific MQD parameters */ 446struct drm_amdgpu_userq_mqd_sdma_gfx11 { 447 /** 448 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer. 449 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL 450 * to get the size. 451 */ 452 __u64 csa_va; 453}; 454 455/* GFX V11 Compute IP specific MQD parameters */ 456struct drm_amdgpu_userq_mqd_compute_gfx11 { 457 /** 458 * @eop_va: Virtual address of the GPU memory to hold the EOP buffer. 459 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL 460 * to get the size. 461 */ 462 __u64 eop_va; 463}; 464 465/* userq signal/wait ioctl */ 466struct drm_amdgpu_userq_signal { 467 /** 468 * @queue_id: Queue handle used by the userq fence creation function 469 * to retrieve the WPTR. 470 */ 471 __u32 queue_id; 472 __u32 pad; 473 /** 474 * @syncobj_handles: The list of syncobj handles submitted by the user queue 475 * job to be signaled. 476 */ 477 __u64 syncobj_handles; 478 /** 479 * @num_syncobj_handles: A count that represents the number of syncobj handles in 480 * @syncobj_handles. 481 */ 482 __u64 num_syncobj_handles; 483 /** 484 * @bo_read_handles: The list of BO handles that the submitted user queue job 485 * is using for read only. This will update BO fences in the kernel. 486 */ 487 __u64 bo_read_handles; 488 /** 489 * @bo_write_handles: The list of BO handles that the submitted user queue job 490 * is using for write only. This will update BO fences in the kernel. 491 */ 492 __u64 bo_write_handles; 493 /** 494 * @num_bo_read_handles: A count that represents the number of read BO handles in 495 * @bo_read_handles. 496 */ 497 __u32 num_bo_read_handles; 498 /** 499 * @num_bo_write_handles: A count that represents the number of write BO handles in 500 * @bo_write_handles. 501 */ 502 __u32 num_bo_write_handles; 503}; 504 505struct drm_amdgpu_userq_fence_info { 506 /** 507 * @va: A gpu address allocated for each queue which stores the 508 * read pointer (RPTR) value. 509 */ 510 __u64 va; 511 /** 512 * @value: A 64 bit value represents the write pointer (WPTR) of the 513 * queue commands which compared with the RPTR value to signal the 514 * fences. 515 */ 516 __u64 value; 517}; 518 519struct drm_amdgpu_userq_wait { 520 /** 521 * @waitq_id: Queue handle used by the userq wait IOCTL to retrieve the 522 * wait queue and maintain the fence driver references in it. 523 */ 524 __u32 waitq_id; 525 __u32 pad; 526 /** 527 * @syncobj_handles: The list of syncobj handles submitted by the user queue 528 * job to get the va/value pairs. 529 */ 530 __u64 syncobj_handles; 531 /** 532 * @syncobj_timeline_handles: The list of timeline syncobj handles submitted by 533 * the user queue job to get the va/value pairs at given @syncobj_timeline_points. 534 */ 535 __u64 syncobj_timeline_handles; 536 /** 537 * @syncobj_timeline_points: The list of timeline syncobj points submitted by the 538 * user queue job for the corresponding @syncobj_timeline_handles. 539 */ 540 __u64 syncobj_timeline_points; 541 /** 542 * @bo_read_handles: The list of read BO handles submitted by the user queue 543 * job to get the va/value pairs. 544 */ 545 __u64 bo_read_handles; 546 /** 547 * @bo_write_handles: The list of write BO handles submitted by the user queue 548 * job to get the va/value pairs. 549 */ 550 __u64 bo_write_handles; 551 /** 552 * @num_syncobj_timeline_handles: A count that represents the number of timeline 553 * syncobj handles in @syncobj_timeline_handles. 554 */ 555 __u16 num_syncobj_timeline_handles; 556 /** 557 * @num_fences: This field can be used both as input and output. As input it defines 558 * the maximum number of fences that can be returned and as output it will specify 559 * how many fences were actually returned from the ioctl. 560 */ 561 __u16 num_fences; 562 /** 563 * @num_syncobj_handles: A count that represents the number of syncobj handles in 564 * @syncobj_handles. 565 */ 566 __u32 num_syncobj_handles; 567 /** 568 * @num_bo_read_handles: A count that represents the number of read BO handles in 569 * @bo_read_handles. 570 */ 571 __u32 num_bo_read_handles; 572 /** 573 * @num_bo_write_handles: A count that represents the number of write BO handles in 574 * @bo_write_handles. 575 */ 576 __u32 num_bo_write_handles; 577 /** 578 * @out_fences: The field is a return value from the ioctl containing the list of 579 * address/value pairs to wait for. 580 */ 581 __u64 out_fences; 582}; 583 584/* vm ioctl */ 585#define AMDGPU_VM_OP_RESERVE_VMID 1 586#define AMDGPU_VM_OP_UNRESERVE_VMID 2 587 588struct drm_amdgpu_vm_in { 589 /** AMDGPU_VM_OP_* */ 590 __u32 op; 591 __u32 flags; 592}; 593 594struct drm_amdgpu_vm_out { 595 /** For future use, no flags defined so far */ 596 __u64 flags; 597}; 598 599union drm_amdgpu_vm { 600 struct drm_amdgpu_vm_in in; 601 struct drm_amdgpu_vm_out out; 602}; 603 604/* sched ioctl */ 605#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 606#define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 607 608struct drm_amdgpu_sched_in { 609 /* AMDGPU_SCHED_OP_* */ 610 __u32 op; 611 __u32 fd; 612 /** AMDGPU_CTX_PRIORITY_* */ 613 __s32 priority; 614 __u32 ctx_id; 615}; 616 617union drm_amdgpu_sched { 618 struct drm_amdgpu_sched_in in; 619}; 620 621/* 622 * This is not a reliable API and you should expect it to fail for any 623 * number of reasons and have fallback path that do not use userptr to 624 * perform any operation. 625 */ 626#define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 627#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 628#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 629#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 630 631struct drm_amdgpu_gem_userptr { 632 __u64 addr; 633 __u64 size; 634 /* AMDGPU_GEM_USERPTR_* */ 635 __u32 flags; 636 /* Resulting GEM handle */ 637 __u32 handle; 638}; 639 640/* SI-CI-VI: */ 641/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 642#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 643#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 644#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 645#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 646#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 647#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 648#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 649#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 650#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 651#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 652#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 653#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 654#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 655#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 656#define AMDGPU_TILING_NUM_BANKS_SHIFT 21 657#define AMDGPU_TILING_NUM_BANKS_MASK 0x3 658 659/* GFX9 - GFX11: */ 660#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 661#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 662#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 663#define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 664#define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 665#define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 666#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 667#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 668#define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 669#define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 670#define AMDGPU_TILING_SCANOUT_SHIFT 63 671#define AMDGPU_TILING_SCANOUT_MASK 0x1 672 673/* GFX12 and later: */ 674#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0 675#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7 676/* These are DCC recompression settings for memory management: */ 677#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3 678#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */ 679#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5 680#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */ 681#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8 682#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */ 683/* When clearing the buffer or moving it from VRAM to GTT, don't compress and set DCC metadata 684 * to uncompressed. Set when parts of an allocation bypass DCC and read raw data. */ 685#define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_SHIFT 14 686#define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_MASK 0x1 687/* bit gap */ 688#define AMDGPU_TILING_GFX12_SCANOUT_SHIFT 63 689#define AMDGPU_TILING_GFX12_SCANOUT_MASK 0x1 690 691/* Set/Get helpers for tiling flags. */ 692#define AMDGPU_TILING_SET(field, value) \ 693 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 694#define AMDGPU_TILING_GET(value, field) \ 695 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 696 697#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 698#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 699 700/** The same structure is shared for input/output */ 701struct drm_amdgpu_gem_metadata { 702 /** GEM Object handle */ 703 __u32 handle; 704 /** Do we want get or set metadata */ 705 __u32 op; 706 struct { 707 /** For future use, no flags defined so far */ 708 __u64 flags; 709 /** family specific tiling info */ 710 __u64 tiling_info; 711 __u32 data_size_bytes; 712 __u32 data[64]; 713 } data; 714}; 715 716struct drm_amdgpu_gem_mmap_in { 717 /** the GEM object handle */ 718 __u32 handle; 719 __u32 _pad; 720}; 721 722struct drm_amdgpu_gem_mmap_out { 723 /** mmap offset from the vma offset manager */ 724 __u64 addr_ptr; 725}; 726 727union drm_amdgpu_gem_mmap { 728 struct drm_amdgpu_gem_mmap_in in; 729 struct drm_amdgpu_gem_mmap_out out; 730}; 731 732struct drm_amdgpu_gem_wait_idle_in { 733 /** GEM object handle */ 734 __u32 handle; 735 /** For future use, no flags defined so far */ 736 __u32 flags; 737 /** Absolute timeout to wait */ 738 __u64 timeout; 739}; 740 741struct drm_amdgpu_gem_wait_idle_out { 742 /** BO status: 0 - BO is idle, 1 - BO is busy */ 743 __u32 status; 744 /** Returned current memory domain */ 745 __u32 domain; 746}; 747 748union drm_amdgpu_gem_wait_idle { 749 struct drm_amdgpu_gem_wait_idle_in in; 750 struct drm_amdgpu_gem_wait_idle_out out; 751}; 752 753struct drm_amdgpu_wait_cs_in { 754 /* Command submission handle 755 * handle equals 0 means none to wait for 756 * handle equals ~0ull means wait for the latest sequence number 757 */ 758 __u64 handle; 759 /** Absolute timeout to wait */ 760 __u64 timeout; 761 __u32 ip_type; 762 __u32 ip_instance; 763 __u32 ring; 764 __u32 ctx_id; 765}; 766 767struct drm_amdgpu_wait_cs_out { 768 /** CS status: 0 - CS completed, 1 - CS still busy */ 769 __u64 status; 770}; 771 772union drm_amdgpu_wait_cs { 773 struct drm_amdgpu_wait_cs_in in; 774 struct drm_amdgpu_wait_cs_out out; 775}; 776 777struct drm_amdgpu_fence { 778 __u32 ctx_id; 779 __u32 ip_type; 780 __u32 ip_instance; 781 __u32 ring; 782 __u64 seq_no; 783}; 784 785struct drm_amdgpu_wait_fences_in { 786 /** This points to uint64_t * which points to fences */ 787 __u64 fences; 788 __u32 fence_count; 789 __u32 wait_all; 790 __u64 timeout_ns; 791}; 792 793struct drm_amdgpu_wait_fences_out { 794 __u32 status; 795 __u32 first_signaled; 796}; 797 798union drm_amdgpu_wait_fences { 799 struct drm_amdgpu_wait_fences_in in; 800 struct drm_amdgpu_wait_fences_out out; 801}; 802 803#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 804#define AMDGPU_GEM_OP_SET_PLACEMENT 1 805#define AMDGPU_GEM_OP_GET_MAPPING_INFO 2 806 807struct drm_amdgpu_gem_vm_entry { 808 /* Start of mapping (in bytes) */ 809 __u64 addr; 810 811 /* Size of mapping (in bytes) */ 812 __u64 size; 813 814 /* Mapping offset */ 815 __u64 offset; 816 817 /* flags needed to recreate mapping */ 818 __u64 flags; 819}; 820 821/* Sets or returns a value associated with a buffer. */ 822struct drm_amdgpu_gem_op { 823 /** GEM object handle */ 824 __u32 handle; 825 /** AMDGPU_GEM_OP_* */ 826 __u32 op; 827 /** Input or return value. For MAPPING_INFO op: pointer to array of struct drm_amdgpu_gem_vm_entry */ 828 __u64 value; 829 /** For MAPPING_INFO op: number of mappings (in/out) */ 830 __u32 num_entries; 831 832 __u32 padding; 833}; 834 835#define AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT (1 << 0) 836 837struct drm_amdgpu_gem_list_handles { 838 /* User pointer to array of drm_amdgpu_gem_bo_info_entry */ 839 __u64 entries; 840 841 /* Size of entries buffer / Number of handles in process (if larger than size of buffer, must retry) */ 842 __u32 num_entries; 843 844 __u32 padding; 845}; 846 847struct drm_amdgpu_gem_list_handles_entry { 848 /* gem handle of buffer object */ 849 __u32 gem_handle; 850 851 /* Currently just one flag: IS_IMPORT */ 852 __u32 flags; 853 854 /* Size of bo */ 855 __u64 size; 856 857 /* Preferred domains for GEM_CREATE */ 858 __u64 preferred_domains; 859 860 /* GEM_CREATE flags for re-creation of buffer */ 861 __u64 alloc_flags; 862 863 /* physical start_addr alignment in bytes for some HW requirements */ 864 __u64 alignment; 865}; 866 867#define AMDGPU_VA_OP_MAP 1 868#define AMDGPU_VA_OP_UNMAP 2 869#define AMDGPU_VA_OP_CLEAR 3 870#define AMDGPU_VA_OP_REPLACE 4 871 872/* Delay the page table update till the next CS */ 873#define AMDGPU_VM_DELAY_UPDATE (1 << 0) 874 875/* Mapping flags */ 876/* readable mapping */ 877#define AMDGPU_VM_PAGE_READABLE (1 << 1) 878/* writable mapping */ 879#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 880/* executable mapping, new for VI */ 881#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 882/* partially resident texture */ 883#define AMDGPU_VM_PAGE_PRT (1 << 4) 884/* MTYPE flags use bit 5 to 8 */ 885#define AMDGPU_VM_MTYPE_MASK (0xf << 5) 886/* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 887#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 888/* Use Non Coherent MTYPE instead of default MTYPE */ 889#define AMDGPU_VM_MTYPE_NC (1 << 5) 890/* Use Write Combine MTYPE instead of default MTYPE */ 891#define AMDGPU_VM_MTYPE_WC (2 << 5) 892/* Use Cache Coherent MTYPE instead of default MTYPE */ 893#define AMDGPU_VM_MTYPE_CC (3 << 5) 894/* Use UnCached MTYPE instead of default MTYPE */ 895#define AMDGPU_VM_MTYPE_UC (4 << 5) 896/* Use Read Write MTYPE instead of default MTYPE */ 897#define AMDGPU_VM_MTYPE_RW (5 << 5) 898/* don't allocate MALL */ 899#define AMDGPU_VM_PAGE_NOALLOC (1 << 9) 900 901struct drm_amdgpu_gem_va { 902 /** GEM object handle */ 903 __u32 handle; 904 __u32 _pad; 905 /** AMDGPU_VA_OP_* */ 906 __u32 operation; 907 /** AMDGPU_VM_PAGE_* */ 908 __u32 flags; 909 /** va address to assign . Must be correctly aligned.*/ 910 __u64 va_address; 911 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 912 __u64 offset_in_bo; 913 /** Specify mapping size. Must be correctly aligned. */ 914 __u64 map_size; 915 /** 916 * vm_timeline_point is a sequence number used to add new timeline point. 917 */ 918 __u64 vm_timeline_point; 919 /** 920 * The vm page table update fence is installed in given vm_timeline_syncobj_out 921 * at vm_timeline_point. 922 */ 923 __u32 vm_timeline_syncobj_out; 924 /** the number of syncobj handles in @input_fence_syncobj_handles */ 925 __u32 num_syncobj_handles; 926 /** Array of sync object handle to wait for given input fences */ 927 __u64 input_fence_syncobj_handles; 928}; 929 930#define AMDGPU_HW_IP_GFX 0 931#define AMDGPU_HW_IP_COMPUTE 1 932#define AMDGPU_HW_IP_DMA 2 933#define AMDGPU_HW_IP_UVD 3 934#define AMDGPU_HW_IP_VCE 4 935#define AMDGPU_HW_IP_UVD_ENC 5 936#define AMDGPU_HW_IP_VCN_DEC 6 937/* 938 * From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support 939 * both encoding and decoding jobs. 940 */ 941#define AMDGPU_HW_IP_VCN_ENC 7 942#define AMDGPU_HW_IP_VCN_JPEG 8 943#define AMDGPU_HW_IP_VPE 9 944#define AMDGPU_HW_IP_NUM 10 945 946#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 947 948#define AMDGPU_CHUNK_ID_IB 0x01 949#define AMDGPU_CHUNK_ID_FENCE 0x02 950#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 951#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 952#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 953#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 954#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 955#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 956#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 957#define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a 958 959struct drm_amdgpu_cs_chunk { 960 __u32 chunk_id; 961 __u32 length_dw; 962 __u64 chunk_data; 963}; 964 965struct drm_amdgpu_cs_in { 966 /** Rendering context id */ 967 __u32 ctx_id; 968 /** Handle of resource list associated with CS */ 969 __u32 bo_list_handle; 970 __u32 num_chunks; 971 __u32 flags; 972 /** this points to __u64 * which point to cs chunks */ 973 __u64 chunks; 974}; 975 976struct drm_amdgpu_cs_out { 977 __u64 handle; 978}; 979 980union drm_amdgpu_cs { 981 struct drm_amdgpu_cs_in in; 982 struct drm_amdgpu_cs_out out; 983}; 984 985/* Specify flags to be used for IB */ 986 987/* This IB should be submitted to CE */ 988#define AMDGPU_IB_FLAG_CE (1<<0) 989 990/* Preamble flag, which means the IB could be dropped if no context switch */ 991#define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 992 993/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 994#define AMDGPU_IB_FLAG_PREEMPT (1<<2) 995 996/* The IB fence should do the L2 writeback but not invalidate any shader 997 * caches (L2/vL1/sL1/I$). */ 998#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 999 1000/* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 1001 * This will reset wave ID counters for the IB. 1002 */ 1003#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 1004 1005/* Flag the IB as secure (TMZ) 1006 */ 1007#define AMDGPU_IB_FLAGS_SECURE (1 << 5) 1008 1009/* Tell KMD to flush and invalidate caches 1010 */ 1011#define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 1012 1013struct drm_amdgpu_cs_chunk_ib { 1014 __u32 _pad; 1015 /** AMDGPU_IB_FLAG_* */ 1016 __u32 flags; 1017 /** Virtual address to begin IB execution */ 1018 __u64 va_start; 1019 /** Size of submission */ 1020 __u32 ib_bytes; 1021 /** HW IP to submit to */ 1022 __u32 ip_type; 1023 /** HW IP index of the same type to submit to */ 1024 __u32 ip_instance; 1025 /** Ring index to submit to */ 1026 __u32 ring; 1027}; 1028 1029struct drm_amdgpu_cs_chunk_dep { 1030 __u32 ip_type; 1031 __u32 ip_instance; 1032 __u32 ring; 1033 __u32 ctx_id; 1034 __u64 handle; 1035}; 1036 1037struct drm_amdgpu_cs_chunk_fence { 1038 __u32 handle; 1039 __u32 offset; 1040}; 1041 1042struct drm_amdgpu_cs_chunk_sem { 1043 __u32 handle; 1044}; 1045 1046struct drm_amdgpu_cs_chunk_syncobj { 1047 __u32 handle; 1048 __u32 flags; 1049 __u64 point; 1050}; 1051 1052#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 1053#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 1054#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 1055 1056union drm_amdgpu_fence_to_handle { 1057 struct { 1058 struct drm_amdgpu_fence fence; 1059 __u32 what; 1060 __u32 pad; 1061 } in; 1062 struct { 1063 __u32 handle; 1064 } out; 1065}; 1066 1067struct drm_amdgpu_cs_chunk_data { 1068 union { 1069 struct drm_amdgpu_cs_chunk_ib ib_data; 1070 struct drm_amdgpu_cs_chunk_fence fence_data; 1071 }; 1072}; 1073 1074#define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1 1075 1076struct drm_amdgpu_cs_chunk_cp_gfx_shadow { 1077 __u64 shadow_va; 1078 __u64 csa_va; 1079 __u64 gds_va; 1080 __u64 flags; 1081}; 1082 1083/* 1084 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 1085 * 1086 */ 1087#define AMDGPU_IDS_FLAGS_FUSION 0x01 1088#define AMDGPU_IDS_FLAGS_PREEMPTION 0x02 1089#define AMDGPU_IDS_FLAGS_TMZ 0x04 1090#define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x08 1091#define AMDGPU_IDS_FLAGS_GANG_SUBMIT 0x10 1092 1093/* 1094 * Query h/w info: Flag identifying VF/PF/PT mode 1095 * 1096 */ 1097#define AMDGPU_IDS_FLAGS_MODE_MASK 0x300 1098#define AMDGPU_IDS_FLAGS_MODE_SHIFT 0x8 1099#define AMDGPU_IDS_FLAGS_MODE_PF 0x0 1100#define AMDGPU_IDS_FLAGS_MODE_VF 0x1 1101#define AMDGPU_IDS_FLAGS_MODE_PT 0x2 1102 1103/* indicate if acceleration can be working */ 1104#define AMDGPU_INFO_ACCEL_WORKING 0x00 1105/* get the crtc_id from the mode object id? */ 1106#define AMDGPU_INFO_CRTC_FROM_ID 0x01 1107/* query hw IP info */ 1108#define AMDGPU_INFO_HW_IP_INFO 0x02 1109/* query hw IP instance count for the specified type */ 1110#define AMDGPU_INFO_HW_IP_COUNT 0x03 1111/* timestamp for GL_ARB_timer_query */ 1112#define AMDGPU_INFO_TIMESTAMP 0x05 1113/* Query the firmware version */ 1114#define AMDGPU_INFO_FW_VERSION 0x0e 1115 /* Subquery id: Query VCE firmware version */ 1116 #define AMDGPU_INFO_FW_VCE 0x1 1117 /* Subquery id: Query UVD firmware version */ 1118 #define AMDGPU_INFO_FW_UVD 0x2 1119 /* Subquery id: Query GMC firmware version */ 1120 #define AMDGPU_INFO_FW_GMC 0x03 1121 /* Subquery id: Query GFX ME firmware version */ 1122 #define AMDGPU_INFO_FW_GFX_ME 0x04 1123 /* Subquery id: Query GFX PFP firmware version */ 1124 #define AMDGPU_INFO_FW_GFX_PFP 0x05 1125 /* Subquery id: Query GFX CE firmware version */ 1126 #define AMDGPU_INFO_FW_GFX_CE 0x06 1127 /* Subquery id: Query GFX RLC firmware version */ 1128 #define AMDGPU_INFO_FW_GFX_RLC 0x07 1129 /* Subquery id: Query GFX MEC firmware version */ 1130 #define AMDGPU_INFO_FW_GFX_MEC 0x08 1131 /* Subquery id: Query SMC firmware version */ 1132 #define AMDGPU_INFO_FW_SMC 0x0a 1133 /* Subquery id: Query SDMA firmware version */ 1134 #define AMDGPU_INFO_FW_SDMA 0x0b 1135 /* Subquery id: Query PSP SOS firmware version */ 1136 #define AMDGPU_INFO_FW_SOS 0x0c 1137 /* Subquery id: Query PSP ASD firmware version */ 1138 #define AMDGPU_INFO_FW_ASD 0x0d 1139 /* Subquery id: Query VCN firmware version */ 1140 #define AMDGPU_INFO_FW_VCN 0x0e 1141 /* Subquery id: Query GFX RLC SRLC firmware version */ 1142 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 1143 /* Subquery id: Query GFX RLC SRLG firmware version */ 1144 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 1145 /* Subquery id: Query GFX RLC SRLS firmware version */ 1146 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 1147 /* Subquery id: Query DMCU firmware version */ 1148 #define AMDGPU_INFO_FW_DMCU 0x12 1149 #define AMDGPU_INFO_FW_TA 0x13 1150 /* Subquery id: Query DMCUB firmware version */ 1151 #define AMDGPU_INFO_FW_DMCUB 0x14 1152 /* Subquery id: Query TOC firmware version */ 1153 #define AMDGPU_INFO_FW_TOC 0x15 1154 /* Subquery id: Query CAP firmware version */ 1155 #define AMDGPU_INFO_FW_CAP 0x16 1156 /* Subquery id: Query GFX RLCP firmware version */ 1157 #define AMDGPU_INFO_FW_GFX_RLCP 0x17 1158 /* Subquery id: Query GFX RLCV firmware version */ 1159 #define AMDGPU_INFO_FW_GFX_RLCV 0x18 1160 /* Subquery id: Query MES_KIQ firmware version */ 1161 #define AMDGPU_INFO_FW_MES_KIQ 0x19 1162 /* Subquery id: Query MES firmware version */ 1163 #define AMDGPU_INFO_FW_MES 0x1a 1164 /* Subquery id: Query IMU firmware version */ 1165 #define AMDGPU_INFO_FW_IMU 0x1b 1166 /* Subquery id: Query VPE firmware version */ 1167 #define AMDGPU_INFO_FW_VPE 0x1c 1168 1169/* number of bytes moved for TTM migration */ 1170#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 1171/* the used VRAM size */ 1172#define AMDGPU_INFO_VRAM_USAGE 0x10 1173/* the used GTT size */ 1174#define AMDGPU_INFO_GTT_USAGE 0x11 1175/* Information about GDS, etc. resource configuration */ 1176#define AMDGPU_INFO_GDS_CONFIG 0x13 1177/* Query information about VRAM and GTT domains */ 1178#define AMDGPU_INFO_VRAM_GTT 0x14 1179/* Query information about register in MMR address space*/ 1180#define AMDGPU_INFO_READ_MMR_REG 0x15 1181/* Query information about device: rev id, family, etc. */ 1182#define AMDGPU_INFO_DEV_INFO 0x16 1183/* visible vram usage */ 1184#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 1185/* number of TTM buffer evictions */ 1186#define AMDGPU_INFO_NUM_EVICTIONS 0x18 1187/* Query memory about VRAM and GTT domains */ 1188#define AMDGPU_INFO_MEMORY 0x19 1189/* Query vce clock table */ 1190#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 1191/* Query vbios related information */ 1192#define AMDGPU_INFO_VBIOS 0x1B 1193 /* Subquery id: Query vbios size */ 1194 #define AMDGPU_INFO_VBIOS_SIZE 0x1 1195 /* Subquery id: Query vbios image */ 1196 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 1197 /* Subquery id: Query vbios info */ 1198 #define AMDGPU_INFO_VBIOS_INFO 0x3 1199/* Query UVD handles */ 1200#define AMDGPU_INFO_NUM_HANDLES 0x1C 1201/* Query sensor related information */ 1202#define AMDGPU_INFO_SENSOR 0x1D 1203 /* Subquery id: Query GPU shader clock */ 1204 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 1205 /* Subquery id: Query GPU memory clock */ 1206 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 1207 /* Subquery id: Query GPU temperature */ 1208 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 1209 /* Subquery id: Query GPU load */ 1210 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 1211 /* Subquery id: Query average GPU power */ 1212 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 1213 /* Subquery id: Query northbridge voltage */ 1214 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 1215 /* Subquery id: Query graphics voltage */ 1216 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 1217 /* Subquery id: Query GPU stable pstate shader clock */ 1218 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 1219 /* Subquery id: Query GPU stable pstate memory clock */ 1220 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 1221 /* Subquery id: Query GPU peak pstate shader clock */ 1222 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa 1223 /* Subquery id: Query GPU peak pstate memory clock */ 1224 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb 1225 /* Subquery id: Query input GPU power */ 1226 #define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc 1227/* Number of VRAM page faults on CPU access. */ 1228#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 1229#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 1230/* query ras mask of enabled features*/ 1231#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 1232/* RAS MASK: UMC (VRAM) */ 1233#define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 1234/* RAS MASK: SDMA */ 1235#define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 1236/* RAS MASK: GFX */ 1237#define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 1238/* RAS MASK: MMHUB */ 1239#define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 1240/* RAS MASK: ATHUB */ 1241#define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 1242/* RAS MASK: PCIE */ 1243#define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 1244/* RAS MASK: HDP */ 1245#define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 1246/* RAS MASK: XGMI */ 1247#define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 1248/* RAS MASK: DF */ 1249#define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 1250/* RAS MASK: SMN */ 1251#define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 1252/* RAS MASK: SEM */ 1253#define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 1254/* RAS MASK: MP0 */ 1255#define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 1256/* RAS MASK: MP1 */ 1257#define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 1258/* RAS MASK: FUSE */ 1259#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 1260/* query video encode/decode caps */ 1261#define AMDGPU_INFO_VIDEO_CAPS 0x21 1262 /* Subquery id: Decode */ 1263 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 1264 /* Subquery id: Encode */ 1265 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 1266/* Query the max number of IBs per gang per submission */ 1267#define AMDGPU_INFO_MAX_IBS 0x22 1268/* query last page fault info */ 1269#define AMDGPU_INFO_GPUVM_FAULT 0x23 1270/* query FW object size and alignment */ 1271#define AMDGPU_INFO_UQ_FW_AREAS 0x24 1272 1273#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 1274#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 1275#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 1276#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 1277 1278struct drm_amdgpu_query_fw { 1279 /** AMDGPU_INFO_FW_* */ 1280 __u32 fw_type; 1281 /** 1282 * Index of the IP if there are more IPs of 1283 * the same type. 1284 */ 1285 __u32 ip_instance; 1286 /** 1287 * Index of the engine. Whether this is used depends 1288 * on the firmware type. (e.g. MEC, SDMA) 1289 */ 1290 __u32 index; 1291 __u32 _pad; 1292}; 1293 1294/* Input structure for the INFO ioctl */ 1295struct drm_amdgpu_info { 1296 /* Where the return value will be stored */ 1297 __u64 return_pointer; 1298 /* The size of the return value. Just like "size" in "snprintf", 1299 * it limits how many bytes the kernel can write. */ 1300 __u32 return_size; 1301 /* The query request id. */ 1302 __u32 query; 1303 1304 union { 1305 struct { 1306 __u32 id; 1307 __u32 _pad; 1308 } mode_crtc; 1309 1310 struct { 1311 /** AMDGPU_HW_IP_* */ 1312 __u32 type; 1313 /** 1314 * Index of the IP if there are more IPs of the same 1315 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 1316 */ 1317 __u32 ip_instance; 1318 } query_hw_ip; 1319 1320 struct { 1321 __u32 dword_offset; 1322 /** number of registers to read */ 1323 __u32 count; 1324 __u32 instance; 1325 /** For future use, no flags defined so far */ 1326 __u32 flags; 1327 } read_mmr_reg; 1328 1329 struct drm_amdgpu_query_fw query_fw; 1330 1331 struct { 1332 __u32 type; 1333 __u32 offset; 1334 } vbios_info; 1335 1336 struct { 1337 __u32 type; 1338 } sensor_info; 1339 1340 struct { 1341 __u32 type; 1342 } video_cap; 1343 }; 1344}; 1345 1346struct drm_amdgpu_info_gds { 1347 /** GDS GFX partition size */ 1348 __u32 gds_gfx_partition_size; 1349 /** GDS compute partition size */ 1350 __u32 compute_partition_size; 1351 /** total GDS memory size */ 1352 __u32 gds_total_size; 1353 /** GWS size per GFX partition */ 1354 __u32 gws_per_gfx_partition; 1355 /** GSW size per compute partition */ 1356 __u32 gws_per_compute_partition; 1357 /** OA size per GFX partition */ 1358 __u32 oa_per_gfx_partition; 1359 /** OA size per compute partition */ 1360 __u32 oa_per_compute_partition; 1361 __u32 _pad; 1362}; 1363 1364struct drm_amdgpu_info_vram_gtt { 1365 __u64 vram_size; 1366 __u64 vram_cpu_accessible_size; 1367 __u64 gtt_size; 1368}; 1369 1370struct drm_amdgpu_heap_info { 1371 /** max. physical memory */ 1372 __u64 total_heap_size; 1373 1374 /** Theoretical max. available memory in the given heap */ 1375 __u64 usable_heap_size; 1376 1377 /** 1378 * Number of bytes allocated in the heap. This includes all processes 1379 * and private allocations in the kernel. It changes when new buffers 1380 * are allocated, freed, and moved. It cannot be larger than 1381 * heap_size. 1382 */ 1383 __u64 heap_usage; 1384 1385 /** 1386 * Theoretical possible max. size of buffer which 1387 * could be allocated in the given heap 1388 */ 1389 __u64 max_allocation; 1390}; 1391 1392struct drm_amdgpu_memory_info { 1393 struct drm_amdgpu_heap_info vram; 1394 struct drm_amdgpu_heap_info cpu_accessible_vram; 1395 struct drm_amdgpu_heap_info gtt; 1396}; 1397 1398struct drm_amdgpu_info_firmware { 1399 __u32 ver; 1400 __u32 feature; 1401}; 1402 1403struct drm_amdgpu_info_vbios { 1404 __u8 name[64]; 1405 __u8 vbios_pn[64]; 1406 __u32 version; 1407 __u32 pad; 1408 __u8 vbios_ver_str[32]; 1409 __u8 date[32]; 1410}; 1411 1412#define AMDGPU_VRAM_TYPE_UNKNOWN 0 1413#define AMDGPU_VRAM_TYPE_GDDR1 1 1414#define AMDGPU_VRAM_TYPE_DDR2 2 1415#define AMDGPU_VRAM_TYPE_GDDR3 3 1416#define AMDGPU_VRAM_TYPE_GDDR4 4 1417#define AMDGPU_VRAM_TYPE_GDDR5 5 1418#define AMDGPU_VRAM_TYPE_HBM 6 1419#define AMDGPU_VRAM_TYPE_DDR3 7 1420#define AMDGPU_VRAM_TYPE_DDR4 8 1421#define AMDGPU_VRAM_TYPE_GDDR6 9 1422#define AMDGPU_VRAM_TYPE_DDR5 10 1423#define AMDGPU_VRAM_TYPE_LPDDR4 11 1424#define AMDGPU_VRAM_TYPE_LPDDR5 12 1425#define AMDGPU_VRAM_TYPE_HBM3E 13 1426 1427struct drm_amdgpu_info_device { 1428 /** PCI Device ID */ 1429 __u32 device_id; 1430 /** Internal chip revision: A0, A1, etc.) */ 1431 __u32 chip_rev; 1432 __u32 external_rev; 1433 /** Revision id in PCI Config space */ 1434 __u32 pci_rev; 1435 __u32 family; 1436 __u32 num_shader_engines; 1437 __u32 num_shader_arrays_per_engine; 1438 /* in KHz */ 1439 __u32 gpu_counter_freq; 1440 __u64 max_engine_clock; 1441 __u64 max_memory_clock; 1442 /* cu information */ 1443 __u32 cu_active_number; 1444 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 1445 __u32 cu_ao_mask; 1446 __u32 cu_bitmap[4][4]; 1447 /** Render backend pipe mask. One render backend is CB+DB. */ 1448 __u32 enabled_rb_pipes_mask; 1449 __u32 num_rb_pipes; 1450 __u32 num_hw_gfx_contexts; 1451 /* PCIe version (the smaller of the GPU and the CPU/motherboard) */ 1452 __u32 pcie_gen; 1453 __u64 ids_flags; 1454 /** Starting virtual address for UMDs. */ 1455 __u64 virtual_address_offset; 1456 /** The maximum virtual address */ 1457 __u64 virtual_address_max; 1458 /** Required alignment of virtual addresses. */ 1459 __u32 virtual_address_alignment; 1460 /** Page table entry - fragment size */ 1461 __u32 pte_fragment_size; 1462 __u32 gart_page_size; 1463 /** constant engine ram size*/ 1464 __u32 ce_ram_size; 1465 /** video memory type info*/ 1466 __u32 vram_type; 1467 /** video memory bit width*/ 1468 __u32 vram_bit_width; 1469 /* vce harvesting instance */ 1470 __u32 vce_harvest_config; 1471 /* gfx double offchip LDS buffers */ 1472 __u32 gc_double_offchip_lds_buf; 1473 /* NGG Primitive Buffer */ 1474 __u64 prim_buf_gpu_addr; 1475 /* NGG Position Buffer */ 1476 __u64 pos_buf_gpu_addr; 1477 /* NGG Control Sideband */ 1478 __u64 cntl_sb_buf_gpu_addr; 1479 /* NGG Parameter Cache */ 1480 __u64 param_buf_gpu_addr; 1481 __u32 prim_buf_size; 1482 __u32 pos_buf_size; 1483 __u32 cntl_sb_buf_size; 1484 __u32 param_buf_size; 1485 /* wavefront size*/ 1486 __u32 wave_front_size; 1487 /* shader visible vgprs*/ 1488 __u32 num_shader_visible_vgprs; 1489 /* CU per shader array*/ 1490 __u32 num_cu_per_sh; 1491 /* number of tcc blocks*/ 1492 __u32 num_tcc_blocks; 1493 /* gs vgt table depth*/ 1494 __u32 gs_vgt_table_depth; 1495 /* gs primitive buffer depth*/ 1496 __u32 gs_prim_buffer_depth; 1497 /* max gs wavefront per vgt*/ 1498 __u32 max_gs_waves_per_vgt; 1499 /* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */ 1500 __u32 pcie_num_lanes; 1501 /* always on cu bitmap */ 1502 __u32 cu_ao_bitmap[4][4]; 1503 /** Starting high virtual address for UMDs. */ 1504 __u64 high_va_offset; 1505 /** The maximum high virtual address */ 1506 __u64 high_va_max; 1507 /* gfx10 pa_sc_tile_steering_override */ 1508 __u32 pa_sc_tile_steering_override; 1509 /* disabled TCCs */ 1510 __u64 tcc_disabled_mask; 1511 __u64 min_engine_clock; 1512 __u64 min_memory_clock; 1513 /* The following fields are only set on gfx11+, older chips set 0. */ 1514 __u32 tcp_cache_size; /* AKA GL0, VMEM cache */ 1515 __u32 num_sqc_per_wgp; 1516 __u32 sqc_data_cache_size; /* AKA SMEM cache */ 1517 __u32 sqc_inst_cache_size; 1518 __u32 gl1c_cache_size; 1519 __u32 gl2c_cache_size; 1520 __u64 mall_size; /* AKA infinity cache */ 1521 /* high 32 bits of the rb pipes mask */ 1522 __u32 enabled_rb_pipes_mask_hi; 1523 /* shadow area size for gfx11 */ 1524 __u32 shadow_size; 1525 /* shadow area base virtual alignment for gfx11 */ 1526 __u32 shadow_alignment; 1527 /* context save area size for gfx11 */ 1528 __u32 csa_size; 1529 /* context save area base virtual alignment for gfx11 */ 1530 __u32 csa_alignment; 1531 /* Userq IP mask (1 << AMDGPU_HW_IP_*) */ 1532 __u32 userq_ip_mask; 1533 __u32 pad; 1534}; 1535 1536struct drm_amdgpu_info_hw_ip { 1537 /** Version of h/w IP */ 1538 __u32 hw_ip_version_major; 1539 __u32 hw_ip_version_minor; 1540 /** Capabilities */ 1541 __u64 capabilities_flags; 1542 /** command buffer address start alignment*/ 1543 __u32 ib_start_alignment; 1544 /** command buffer size alignment*/ 1545 __u32 ib_size_alignment; 1546 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 1547 __u32 available_rings; 1548 /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */ 1549 __u32 ip_discovery_version; 1550 /* Userq available slots */ 1551 __u32 userq_num_slots; 1552}; 1553 1554struct drm_amdgpu_info_num_handles { 1555 /** Max handles as supported by firmware for UVD */ 1556 __u32 uvd_max_handles; 1557 /** Handles currently in use for UVD */ 1558 __u32 uvd_used_handles; 1559}; 1560 1561#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1562 1563struct drm_amdgpu_info_vce_clock_table_entry { 1564 /** System clock */ 1565 __u32 sclk; 1566 /** Memory clock */ 1567 __u32 mclk; 1568 /** VCE clock */ 1569 __u32 eclk; 1570 __u32 pad; 1571}; 1572 1573struct drm_amdgpu_info_vce_clock_table { 1574 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1575 __u32 num_valid_entries; 1576 __u32 pad; 1577}; 1578 1579/* query video encode/decode caps */ 1580#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 1581#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 1582#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 1583#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 1584#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 1585#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 1586#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 1587#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 1588#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 1589 1590struct drm_amdgpu_info_video_codec_info { 1591 __u32 valid; 1592 __u32 max_width; 1593 __u32 max_height; 1594 __u32 max_pixels_per_frame; 1595 __u32 max_level; 1596 __u32 pad; 1597}; 1598 1599struct drm_amdgpu_info_video_caps { 1600 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 1601}; 1602 1603#define AMDGPU_VMHUB_TYPE_MASK 0xff 1604#define AMDGPU_VMHUB_TYPE_SHIFT 0 1605#define AMDGPU_VMHUB_TYPE_GFX 0 1606#define AMDGPU_VMHUB_TYPE_MM0 1 1607#define AMDGPU_VMHUB_TYPE_MM1 2 1608#define AMDGPU_VMHUB_IDX_MASK 0xff00 1609#define AMDGPU_VMHUB_IDX_SHIFT 8 1610 1611struct drm_amdgpu_info_gpuvm_fault { 1612 __u64 addr; 1613 __u32 status; 1614 __u32 vmhub; 1615}; 1616 1617struct drm_amdgpu_info_uq_metadata_gfx { 1618 /* shadow area size for gfx11 */ 1619 __u32 shadow_size; 1620 /* shadow area base virtual alignment for gfx11 */ 1621 __u32 shadow_alignment; 1622 /* context save area size for gfx11 */ 1623 __u32 csa_size; 1624 /* context save area base virtual alignment for gfx11 */ 1625 __u32 csa_alignment; 1626}; 1627 1628struct drm_amdgpu_info_uq_metadata { 1629 union { 1630 struct drm_amdgpu_info_uq_metadata_gfx gfx; 1631 }; 1632}; 1633 1634/* 1635 * Supported GPU families 1636 */ 1637#define AMDGPU_FAMILY_UNKNOWN 0 1638#define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 1639#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 1640#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 1641#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 1642#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1643#define AMDGPU_FAMILY_AI 141 /* Vega10 */ 1644#define AMDGPU_FAMILY_RV 142 /* Raven */ 1645#define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1646#define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ 1647#define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */ 1648#define AMDGPU_FAMILY_YC 146 /* Yellow Carp */ 1649#define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */ 1650#define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */ 1651#define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */ 1652#define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */ 1653#define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */ 1654 1655#if defined(__cplusplus) 1656} 1657#endif 1658 1659#endif
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