header.h

  1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
  2/*
  3 * This file is provided under a dual BSD/GPLv2 license.  When using or
  4 * redistributing this file, you may do so under either license.
  5 *
  6 * Copyright(c) 2022 Intel Corporation
  7 */
  8
  9#ifndef __INCLUDE_SOUND_SOF_IPC4_HEADER_H__
 10#define __INCLUDE_SOUND_SOF_IPC4_HEADER_H__
 11
 12#include <linux/types.h>
 13#include <uapi/sound/sof/abi.h>
 14
 15/* maximum message size for mailbox Tx/Rx */
 16#define SOF_IPC4_MSG_MAX_SIZE			4096
 17
 18/** \addtogroup sof_uapi uAPI
 19 *  SOF uAPI specification.
 20 *  @{
 21 */
 22
 23/**
 24 * struct sof_ipc4_msg - Placeholder of an IPC4 message
 25 * @header_u64:		IPC4 header as single u64 number
 26 * @primary:		Primary, mandatory part of the header
 27 * @extension:		Extended part of the header, if not used it should be
 28 *			set to 0
 29 * @data_size:		Size of data in bytes pointed by @data_ptr
 30 * @data_ptr:		Pointer to the optional payload of a message
 31 */
 32struct sof_ipc4_msg {
 33	union {
 34		u64 header_u64;
 35		struct {
 36			u32 primary;
 37			u32 extension;
 38		};
 39	};
 40
 41	size_t data_size;
 42	void *data_ptr;
 43};
 44
 45/**
 46 * struct sof_ipc4_tuple - Generic type/ID and parameter tuple
 47 * @type:		type/ID
 48 * @size:		size of the @value array in bytes
 49 * @value:		value for the given type
 50 */
 51struct sof_ipc4_tuple {
 52	uint32_t type;
 53	uint32_t size;
 54	uint32_t value[];
 55} __packed;
 56
 57/*
 58 * IPC4 messages have two 32 bit identifier made up as follows :-
 59 *
 60 * header - msg type, msg id, msg direction ...
 61 * extension - extra params such as msg data size in mailbox
 62 *
 63 * These are sent at the start of the IPC message in the mailbox. Messages
 64 * should not be sent in the doorbell (special exceptions for firmware).
 65 */
 66
 67/*
 68 * IPC4 primary header bit allocation for messages
 69 * bit 0-23:	message type specific
 70 * bit 24-28:	type:	enum sof_ipc4_global_msg if target is SOF_IPC4_FW_GEN_MSG
 71 *			enum sof_ipc4_module_type if target is SOF_IPC4_MODULE_MSG
 72 * bit 29:	response - sof_ipc4_msg_dir
 73 * bit 30:	target - enum sof_ipc4_msg_target
 74 * bit 31:	reserved, unused
 75 */
 76
 77/* Value of target field - must fit into 1 bit */
 78enum sof_ipc4_msg_target {
 79	/* Global FW message */
 80	SOF_IPC4_FW_GEN_MSG,
 81
 82	/* Module message */
 83	SOF_IPC4_MODULE_MSG
 84};
 85
 86/* Value of type field - must fit into 5 bits */
 87enum sof_ipc4_global_msg {
 88	SOF_IPC4_GLB_BOOT_CONFIG,
 89	SOF_IPC4_GLB_ROM_CONTROL,
 90	SOF_IPC4_GLB_IPCGATEWAY_CMD,
 91
 92	/* 3 .. 12: RESERVED - do not use */
 93
 94	SOF_IPC4_GLB_PERF_MEASUREMENTS_CMD = 13,
 95	SOF_IPC4_GLB_CHAIN_DMA,
 96
 97	SOF_IPC4_GLB_LOAD_MULTIPLE_MODULES,
 98	SOF_IPC4_GLB_UNLOAD_MULTIPLE_MODULES,
 99
100	/* pipeline settings */
101	SOF_IPC4_GLB_CREATE_PIPELINE,
102	SOF_IPC4_GLB_DELETE_PIPELINE,
103	SOF_IPC4_GLB_SET_PIPELINE_STATE,
104	SOF_IPC4_GLB_GET_PIPELINE_STATE,
105	SOF_IPC4_GLB_GET_PIPELINE_CONTEXT_SIZE,
106	SOF_IPC4_GLB_SAVE_PIPELINE,
107	SOF_IPC4_GLB_RESTORE_PIPELINE,
108
109	/*
110	 * library loading
111	 *
112	 * Loads library (using Code Load or HD/A Host Output DMA)
113	 */
114	SOF_IPC4_GLB_LOAD_LIBRARY,
115	/*
116	 * Prepare the host DMA channel for library loading, must be followed by
117	 * a SOF_IPC4_GLB_LOAD_LIBRARY message as the library loading step
118	 */
119	SOF_IPC4_GLB_LOAD_LIBRARY_PREPARE,
120
121	SOF_IPC4_GLB_INTERNAL_MESSAGE,
122
123	/* Notification (FW to SW driver) */
124	SOF_IPC4_GLB_NOTIFICATION,
125
126	/* 28 .. 31: RESERVED - do not use */
127
128	SOF_IPC4_GLB_TYPE_LAST,
129};
130
131/* Value of response field - must fit into 1 bit */
132enum sof_ipc4_msg_dir {
133	SOF_IPC4_MSG_REQUEST,
134	SOF_IPC4_MSG_REPLY,
135};
136
137enum sof_ipc4_pipeline_state {
138	SOF_IPC4_PIPE_INVALID_STATE,
139	SOF_IPC4_PIPE_UNINITIALIZED,
140	SOF_IPC4_PIPE_RESET,
141	SOF_IPC4_PIPE_PAUSED,
142	SOF_IPC4_PIPE_RUNNING,
143	SOF_IPC4_PIPE_EOS
144};
145
146/* Generic message fields (bit 24-30) */
147
148/* encoded to header's msg_tgt field */
149#define SOF_IPC4_MSG_TARGET_SHIFT		30
150#define SOF_IPC4_MSG_TARGET_MASK		BIT(30)
151#define SOF_IPC4_MSG_TARGET(x)			((x) << SOF_IPC4_MSG_TARGET_SHIFT)
152#define SOF_IPC4_MSG_IS_MODULE_MSG(x)		((x) & SOF_IPC4_MSG_TARGET_MASK ? 1 : 0)
153
154/* encoded to header's rsp field */
155#define SOF_IPC4_MSG_DIR_SHIFT			29
156#define SOF_IPC4_MSG_DIR_MASK			BIT(29)
157#define SOF_IPC4_MSG_DIR(x)			((x) << SOF_IPC4_MSG_DIR_SHIFT)
158
159/* encoded to header's type field */
160#define SOF_IPC4_MSG_TYPE_SHIFT			24
161#define SOF_IPC4_MSG_TYPE_MASK			GENMASK(28, 24)
162#define SOF_IPC4_MSG_TYPE_SET(x)		(((x) << SOF_IPC4_MSG_TYPE_SHIFT) & \
163						 SOF_IPC4_MSG_TYPE_MASK)
164#define SOF_IPC4_MSG_TYPE_GET(x)		(((x) & SOF_IPC4_MSG_TYPE_MASK) >> \
165						 SOF_IPC4_MSG_TYPE_SHIFT)
166
167/* Global message type specific field definitions */
168
169/* pipeline creation ipc msg */
170#define SOF_IPC4_GLB_PIPE_INSTANCE_SHIFT	16
171#define SOF_IPC4_GLB_PIPE_INSTANCE_MASK		GENMASK(23, 16)
172#define SOF_IPC4_GLB_PIPE_INSTANCE_ID(x)	((x) << SOF_IPC4_GLB_PIPE_INSTANCE_SHIFT)
173
174#define SOF_IPC4_GLB_PIPE_PRIORITY_SHIFT	11
175#define SOF_IPC4_GLB_PIPE_PRIORITY_MASK		GENMASK(15, 11)
176#define SOF_IPC4_GLB_PIPE_PRIORITY(x)		((x) << SOF_IPC4_GLB_PIPE_PRIORITY_SHIFT)
177
178#define SOF_IPC4_GLB_PIPE_MEM_SIZE_SHIFT	0
179#define SOF_IPC4_GLB_PIPE_MEM_SIZE_MASK		GENMASK(10, 0)
180#define SOF_IPC4_GLB_PIPE_MEM_SIZE(x)		((x) << SOF_IPC4_GLB_PIPE_MEM_SIZE_SHIFT)
181
182#define SOF_IPC4_GLB_PIPE_EXT_LP_SHIFT		0
183#define SOF_IPC4_GLB_PIPE_EXT_LP_MASK		BIT(0)
184#define SOF_IPC4_GLB_PIPE_EXT_LP(x)		((x) << SOF_IPC4_GLB_PIPE_EXT_LP_SHIFT)
185
186#define SOF_IPC4_GLB_PIPE_EXT_CORE_ID_SHIFT	20
187#define SOF_IPC4_GLB_PIPE_EXT_CORE_ID_MASK	GENMASK(23, 20)
188#define SOF_IPC4_GLB_PIPE_EXT_CORE_ID(x)	((x) << SOF_IPC4_GLB_PIPE_EXT_CORE_ID_SHIFT)
189
190/* pipeline set state ipc msg */
191#define SOF_IPC4_GLB_PIPE_STATE_ID_SHIFT		16
192#define SOF_IPC4_GLB_PIPE_STATE_ID_MASK		GENMASK(23, 16)
193#define SOF_IPC4_GLB_PIPE_STATE_ID(x)		((x) << SOF_IPC4_GLB_PIPE_STATE_ID_SHIFT)
194
195#define SOF_IPC4_GLB_PIPE_STATE_SHIFT		0
196#define SOF_IPC4_GLB_PIPE_STATE_MASK		GENMASK(15, 0)
197#define SOF_IPC4_GLB_PIPE_STATE(x)		((x) << SOF_IPC4_GLB_PIPE_STATE_SHIFT)
198
199/* pipeline set state IPC msg extension */
200#define SOF_IPC4_GLB_PIPE_STATE_EXT_MULTI	BIT(0)
201
202/* load library ipc msg */
203#define SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID_SHIFT	16
204#define SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID(x)	((x) << SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID_SHIFT)
205
206/* chain dma ipc message */
207#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_SHIFT	0
208#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_MASK	GENMASK(4, 0)
209#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID(x)	(((x) << SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_SHIFT) & \
210						 SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_MASK)
211
212#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_SHIFT	8
213#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_MASK	GENMASK(12, 8)
214#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID(x)	(((x) << SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_SHIFT) & \
215						 SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_MASK)
216
217#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_SHIFT	16
218#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_MASK	BIT(16)
219#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE(x)	(((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_SHIFT)
220
221#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE_SHIFT	17
222#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE_MASK	BIT(17)
223#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE(x)	(((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_ENABLE_SHIFT)
224
225#define SOF_IPC4_GLB_CHAIN_DMA_SCS_SHIFT	18
226#define SOF_IPC4_GLB_CHAIN_DMA_SCS_MASK		BIT(18)
227#define SOF_IPC4_GLB_CHAIN_DMA_SCS(x)		(((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_SCS_SHIFT)
228
229#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_SHIFT 0
230#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_MASK  GENMASK(24, 0)
231#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE(x)	   (((x) << \
232						     SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_SHIFT) & \
233						    SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_MASK)
234
235enum sof_ipc4_channel_config {
236	/* one channel only. */
237	SOF_IPC4_CHANNEL_CONFIG_MONO,
238	/* L & R. */
239	SOF_IPC4_CHANNEL_CONFIG_STEREO,
240	/* L, R & LFE; PCM only. */
241	SOF_IPC4_CHANNEL_CONFIG_2_POINT_1,
242	/* L, C & R; MP3 & AAC only. */
243	SOF_IPC4_CHANNEL_CONFIG_3_POINT_0,
244	/* L, C, R & LFE; PCM only. */
245	SOF_IPC4_CHANNEL_CONFIG_3_POINT_1,
246	/* L, R, Ls & Rs; PCM only. */
247	SOF_IPC4_CHANNEL_CONFIG_QUATRO,
248	/* L, C, R & Cs; MP3 & AAC only. */
249	SOF_IPC4_CHANNEL_CONFIG_4_POINT_0,
250	/* L, C, R, Ls & Rs. */
251	SOF_IPC4_CHANNEL_CONFIG_5_POINT_0,
252	/* L, C, R, Ls, Rs & LFE. */
253	SOF_IPC4_CHANNEL_CONFIG_5_POINT_1,
254	/* one channel replicated in two. */
255	SOF_IPC4_CHANNEL_CONFIG_DUAL_MONO,
256	/* Stereo (L,R) in 4 slots, 1st stream: [ L, R, -, - ] */
257	SOF_IPC4_CHANNEL_CONFIG_I2S_DUAL_STEREO_0,
258	/* Stereo (L,R) in 4 slots, 2nd stream: [ -, -, L, R ] */
259	SOF_IPC4_CHANNEL_CONFIG_I2S_DUAL_STEREO_1,
260	/* L, C, R, Ls, Rs & LFE., LS, RS */
261	SOF_IPC4_CHANNEL_CONFIG_7_POINT_1,
262};
263
264enum sof_ipc4_interleaved_style {
265	SOF_IPC4_CHANNELS_INTERLEAVED,
266	SOF_IPC4_CHANNELS_NONINTERLEAVED,
267};
268
269enum sof_ipc4_sample_type {
270	SOF_IPC4_MSB_INTEGER, /* integer with Most Significant Byte first */
271	SOF_IPC4_LSB_INTEGER, /* integer with Least Significant Byte first */
272};
273
274struct sof_ipc4_audio_format {
275	uint32_t sampling_frequency;
276	uint32_t bit_depth;
277	uint32_t ch_map;
278	uint32_t ch_cfg; /* sof_ipc4_channel_config */
279	uint32_t interleaving_style;
280	uint32_t fmt_cfg; /* channels_count valid_bit_depth s_type */
281} __packed __aligned(4);
282
283#define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_SHIFT	0
284#define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_MASK	GENMASK(7, 0)
285#define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(x)	\
286	((x) & SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_MASK)
287#define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_SHIFT	8
288#define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_MASK	GENMASK(15, 8)
289#define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(x)	\
290	(((x) & SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_MASK) >> \
291	 SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_SHIFT)
292#define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_SHIFT	16
293#define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_MASK	GENMASK(23, 16)
294#define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE(x)	\
295	(((x) & SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_MASK) >>  \
296	 SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_SHIFT)
297
298/* Module message type specific field definitions */
299
300enum sof_ipc4_module_type {
301	SOF_IPC4_MOD_INIT_INSTANCE,
302	SOF_IPC4_MOD_CONFIG_GET,
303	SOF_IPC4_MOD_CONFIG_SET,
304	SOF_IPC4_MOD_LARGE_CONFIG_GET,
305	SOF_IPC4_MOD_LARGE_CONFIG_SET,
306	SOF_IPC4_MOD_BIND,
307	SOF_IPC4_MOD_UNBIND,
308	SOF_IPC4_MOD_SET_DX,
309	SOF_IPC4_MOD_SET_D0IX,
310	SOF_IPC4_MOD_ENTER_MODULE_RESTORE,
311	SOF_IPC4_MOD_EXIT_MODULE_RESTORE,
312	SOF_IPC4_MOD_DELETE_INSTANCE,
313
314	SOF_IPC4_MOD_TYPE_LAST,
315};
316
317struct sof_ipc4_base_module_cfg {
318	uint32_t cpc; /* the max count of Cycles Per Chunk processing */
319	uint32_t ibs; /* input Buffer Size (in bytes)  */
320	uint32_t obs; /* output Buffer Size (in bytes) */
321	uint32_t is_pages; /* number of physical pages used */
322	struct sof_ipc4_audio_format audio_fmt;
323} __packed __aligned(4);
324
325/* common module ipc msg */
326#define SOF_IPC4_MOD_INSTANCE_SHIFT		16
327#define SOF_IPC4_MOD_INSTANCE_MASK		GENMASK(23, 16)
328#define SOF_IPC4_MOD_INSTANCE(x)		((x) << SOF_IPC4_MOD_INSTANCE_SHIFT)
329#define SOF_IPC4_MOD_INSTANCE_GET(x)		(((x) & SOF_IPC4_MOD_INSTANCE_MASK) \
330						 >> SOF_IPC4_MOD_INSTANCE_SHIFT)
331
332#define SOF_IPC4_MOD_ID_SHIFT			0
333#define SOF_IPC4_MOD_ID_MASK			GENMASK(15, 0)
334#define SOF_IPC4_MOD_ID(x)			((x) << SOF_IPC4_MOD_ID_SHIFT)
335#define SOF_IPC4_MOD_ID_GET(x)			(((x) & SOF_IPC4_MOD_ID_MASK) \
336						 >> SOF_IPC4_MOD_ID_SHIFT)
337
338/* init module ipc msg */
339#define SOF_IPC4_MOD_EXT_PARAM_SIZE_SHIFT	0
340#define SOF_IPC4_MOD_EXT_PARAM_SIZE_MASK	GENMASK(15, 0)
341#define SOF_IPC4_MOD_EXT_PARAM_SIZE(x)		((x) << SOF_IPC4_MOD_EXT_PARAM_SIZE_SHIFT)
342
343#define SOF_IPC4_MOD_EXT_PPL_ID_SHIFT		16
344#define SOF_IPC4_MOD_EXT_PPL_ID_MASK		GENMASK(23, 16)
345#define SOF_IPC4_MOD_EXT_PPL_ID(x)		((x) << SOF_IPC4_MOD_EXT_PPL_ID_SHIFT)
346
347#define SOF_IPC4_MOD_EXT_CORE_ID_SHIFT		24
348#define SOF_IPC4_MOD_EXT_CORE_ID_MASK		GENMASK(27, 24)
349#define SOF_IPC4_MOD_EXT_CORE_ID(x)		((x) << SOF_IPC4_MOD_EXT_CORE_ID_SHIFT)
350
351#define SOF_IPC4_MOD_EXT_DOMAIN_SHIFT		28
352#define SOF_IPC4_MOD_EXT_DOMAIN_MASK		BIT(28)
353#define SOF_IPC4_MOD_EXT_DOMAIN(x)		((x) << SOF_IPC4_MOD_EXT_DOMAIN_SHIFT)
354
355/*  bind/unbind module ipc msg */
356#define SOF_IPC4_MOD_EXT_DST_MOD_ID_SHIFT	0
357#define SOF_IPC4_MOD_EXT_DST_MOD_ID_MASK	GENMASK(15, 0)
358#define SOF_IPC4_MOD_EXT_DST_MOD_ID(x)		((x) << SOF_IPC4_MOD_EXT_DST_MOD_ID_SHIFT)
359
360#define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_SHIFT	16
361#define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_MASK	GENMASK(23, 16)
362#define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE(x)	((x) << SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_SHIFT)
363
364#define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_SHIFT	24
365#define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_MASK	GENMASK(26, 24)
366#define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID(x)	((x) << SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_SHIFT)
367
368#define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_SHIFT	27
369#define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_MASK	GENMASK(29, 27)
370#define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID(x)	((x) << SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_SHIFT)
371
372#define MOD_ENABLE_LOG	6
373#define MOD_SYSTEM_TIME	20
374
375/* set module large config */
376#define SOF_IPC4_MOD_EXT_MSG_SIZE_SHIFT		0
377#define SOF_IPC4_MOD_EXT_MSG_SIZE_MASK		GENMASK(19, 0)
378#define SOF_IPC4_MOD_EXT_MSG_SIZE(x)		((x) << SOF_IPC4_MOD_EXT_MSG_SIZE_SHIFT)
379
380#define SOF_IPC4_MOD_EXT_MSG_PARAM_ID_SHIFT	20
381#define SOF_IPC4_MOD_EXT_MSG_PARAM_ID_MASK	GENMASK(27, 20)
382#define SOF_IPC4_MOD_EXT_MSG_PARAM_ID(x)	((x) << SOF_IPC4_MOD_EXT_MSG_PARAM_ID_SHIFT)
383
384#define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_SHIFT	28
385#define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_MASK	BIT(28)
386#define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK(x)	((x) << SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_SHIFT)
387
388#define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_SHIFT	29
389#define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_MASK	BIT(29)
390#define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK(x)	((x) << SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_SHIFT)
391
392/* Init instance messagees */
393#define SOF_IPC4_MOD_INIT_BASEFW_MOD_ID		0
394#define SOF_IPC4_MOD_INIT_BASEFW_INSTANCE_ID	0
395
396enum sof_ipc4_base_fw_params {
397	SOF_IPC4_FW_PARAM_ENABLE_LOGS = 6,
398	SOF_IPC4_FW_PARAM_FW_CONFIG,
399	SOF_IPC4_FW_PARAM_HW_CONFIG_GET,
400	SOF_IPC4_FW_PARAM_MODULES_INFO_GET,
401	SOF_IPC4_FW_PARAM_LIBRARIES_INFO_GET = 16,
402	SOF_IPC4_FW_PARAM_SYSTEM_TIME = 20,
403	SOF_IPC4_FW_PARAM_MIC_PRIVACY_STATE_CHANGE = 35,
404};
405
406enum sof_ipc4_fw_config_params {
407	SOF_IPC4_FW_CFG_FW_VERSION,
408	SOF_IPC4_FW_CFG_MEMORY_RECLAIMED,
409	SOF_IPC4_FW_CFG_SLOW_CLOCK_FREQ_HZ,
410	SOF_IPC4_FW_CFG_FAST_CLOCK_FREQ_HZ,
411	SOF_IPC4_FW_CFG_DMA_BUFFER_CONFIG,
412	SOF_IPC4_FW_CFG_ALH_SUPPORT_LEVEL,
413	SOF_IPC4_FW_CFG_DL_MAILBOX_BYTES,
414	SOF_IPC4_FW_CFG_UL_MAILBOX_BYTES,
415	SOF_IPC4_FW_CFG_TRACE_LOG_BYTES,
416	SOF_IPC4_FW_CFG_MAX_PPL_COUNT,
417	SOF_IPC4_FW_CFG_MAX_ASTATE_COUNT,
418	SOF_IPC4_FW_CFG_MAX_MODULE_PIN_COUNT,
419	SOF_IPC4_FW_CFG_MODULES_COUNT,
420	SOF_IPC4_FW_CFG_MAX_MOD_INST_COUNT,
421	SOF_IPC4_FW_CFG_MAX_LL_TASKS_PER_PRI_COUNT,
422	SOF_IPC4_FW_CFG_LL_PRI_COUNT,
423	SOF_IPC4_FW_CFG_MAX_DP_TASKS_COUNT,
424	SOF_IPC4_FW_CFG_MAX_LIBS_COUNT,
425	SOF_IPC4_FW_CFG_SCHEDULER_CONFIG,
426	SOF_IPC4_FW_CFG_XTAL_FREQ_HZ,
427	SOF_IPC4_FW_CFG_CLOCKS_CONFIG,
428	SOF_IPC4_FW_CFG_RESERVED,
429	SOF_IPC4_FW_CFG_POWER_GATING_POLICY,
430	SOF_IPC4_FW_CFG_ASSERT_MODE,
431	SOF_IPC4_FW_RESERVED1,
432	SOF_IPC4_FW_RESERVED2,
433	SOF_IPC4_FW_RESERVED3,
434	SOF_IPC4_FW_RESERVED4,
435	SOF_IPC4_FW_RESERVED5,
436	SOF_IPC4_FW_CONTEXT_SAVE
437};
438
439struct sof_ipc4_fw_version {
440	uint16_t major;
441	uint16_t minor;
442	uint16_t hotfix;
443	uint16_t build;
444} __packed;
445
446/* Payload data for SOF_IPC4_MOD_SET_DX */
447struct sof_ipc4_dx_state_info {
448	/* core(s) to apply the change */
449	uint32_t core_mask;
450	/* core state: 0: put core_id to D3; 1: put core_id to D0 */
451	uint32_t dx_mask;
452} __packed __aligned(4);
453
454enum sof_ipc4_hw_config_params {
455	SOF_IPC4_HW_CFG_INTEL_MIC_PRIVACY_CAPS = 11,
456};
457
458#define SOF_IPC_INTEL_MIC_PRIVACY_VERSION_PTL	1
459
460struct sof_ipc4_intel_mic_privacy_cap {
461	uint32_t version;
462	uint32_t capabilities_length;
463	uint32_t capabilities[];
464} __packed;
465
466/* Reply messages */
467
468/*
469 * IPC4 primary header bit allocation for replies
470 * bit 0-23:	status
471 * bit 24-28:	type:	enum sof_ipc4_global_msg if target is SOF_IPC4_FW_GEN_MSG
472 *			enum sof_ipc4_module_type if target is SOF_IPC4_MODULE_MSG
473 * bit 29:	response - sof_ipc4_msg_dir
474 * bit 30:	target - enum sof_ipc4_msg_target
475 * bit 31:	reserved, unused
476 */
477
478#define SOF_IPC4_REPLY_STATUS			GENMASK(23, 0)
479
480/* Notification messages */
481
482/*
483 * IPC4 primary header bit allocation for notifications
484 * bit 0-15:	notification type specific
485 * bit 16-23:	enum sof_ipc4_notification_type
486 * bit 24-28:	SOF_IPC4_GLB_NOTIFICATION
487 * bit 29:	response - sof_ipc4_msg_dir
488 * bit 30:	target - enum sof_ipc4_msg_target
489 * bit 31:	reserved, unused
490 */
491
492#define SOF_IPC4_MSG_IS_NOTIFICATION(x)		(SOF_IPC4_MSG_TYPE_GET(x) == \
493						 SOF_IPC4_GLB_NOTIFICATION)
494
495#define SOF_IPC4_NOTIFICATION_TYPE_SHIFT	16
496#define SOF_IPC4_NOTIFICATION_TYPE_MASK		GENMASK(23, 16)
497#define SOF_IPC4_NOTIFICATION_TYPE_GET(x)	(((x) & SOF_IPC4_NOTIFICATION_TYPE_MASK) >> \
498						 SOF_IPC4_NOTIFICATION_TYPE_SHIFT)
499
500#define SOF_IPC4_LOG_CORE_SHIFT			12
501#define SOF_IPC4_LOG_CORE_MASK			GENMASK(15, 12)
502#define SOF_IPC4_LOG_CORE_GET(x)		(((x) & SOF_IPC4_LOG_CORE_MASK) >> \
503						 SOF_IPC4_LOG_CORE_SHIFT)
504
505#define SOF_IPC4_FW_READY_LIB_RESTORED		BIT(15)
506
507/* Value of notification type field - must fit into 8 bits */
508enum sof_ipc4_notification_type {
509	/* Phrase detected (notification from WoV module) */
510	SOF_IPC4_NOTIFY_PHRASE_DETECTED = 4,
511	/* Event from a resource (pipeline or module instance) */
512	SOF_IPC4_NOTIFY_RESOURCE_EVENT,
513	/* Debug log buffer status changed */
514	SOF_IPC4_NOTIFY_LOG_BUFFER_STATUS,
515	/* Timestamp captured at the link */
516	SOF_IPC4_NOTIFY_TIMESTAMP_CAPTURED,
517	/* FW complete initialization */
518	SOF_IPC4_NOTIFY_FW_READY,
519	/* Audio classifier result (ACA) */
520	SOF_IPC4_NOTIFY_FW_AUD_CLASS_RESULT,
521	/* Exception caught by DSP FW */
522	SOF_IPC4_NOTIFY_EXCEPTION_CAUGHT,
523	/* 11 is skipped by the existing cavs firmware */
524	/* Custom module notification */
525	SOF_IPC4_NOTIFY_MODULE_NOTIFICATION = 12,
526	/* 13 is reserved - do not use */
527	/* Probe notify data available */
528	SOF_IPC4_NOTIFY_PROBE_DATA_AVAILABLE = 14,
529	/* AM module notifications */
530	SOF_IPC4_NOTIFY_ASYNC_MSG_SRVC_MESSAGE,
531
532	SOF_IPC4_NOTIFY_TYPE_LAST,
533};
534
535struct sof_ipc4_notify_resource_data {
536	uint32_t resource_type;
537	uint32_t resource_id;
538	uint32_t event_type;
539	uint32_t reserved;
540	uint32_t data[6];
541} __packed __aligned(4);
542
543#define SOF_IPC4_DEBUG_DESCRIPTOR_SIZE		12 /* 3 x u32 */
544
545/*
546 * The debug memory window is divided into 16 slots, and the
547 * first slot is used as a recorder for the other 15 slots.
548 */
549#define SOF_IPC4_MAX_DEBUG_SLOTS		15
550#define SOF_IPC4_DEBUG_SLOT_SIZE		0x1000
551
552/* debug log slot types */
553#define SOF_IPC4_DEBUG_SLOT_UNUSED		0x00000000
554#define SOF_IPC4_DEBUG_SLOT_CRITICAL_LOG	0x54524300 /* byte 0: core ID */
555#define SOF_IPC4_DEBUG_SLOT_DEBUG_LOG		0x474f4c00 /* byte 0: core ID */
556#define SOF_IPC4_DEBUG_SLOT_GDB_STUB		0x42444700
557#define SOF_IPC4_DEBUG_SLOT_TELEMETRY		0x4c455400
558#define SOF_IPC4_DEBUG_SLOT_BROKEN		0x44414544
559
560/**
561 * struct sof_ipc4_notify_module_data - payload for module notification
562 * @instance_id: instance ID of the originator module of the notification
563 * @module_id: module ID of the originator of the notification
564 * @event_id: module specific event id
565 * @event_data_size: Size of the @event_data (if any) in bytes
566 * @event_data: Optional notification data, module and notification dependent
567 */
568struct sof_ipc4_notify_module_data {
569	uint16_t instance_id;
570	uint16_t module_id;
571	uint32_t event_id;
572	uint32_t event_data_size;
573	uint8_t event_data[];
574} __packed __aligned(4);
575
576/*
577 * ALSA kcontrol change notification
578 *
579 * The event_id of struct sof_ipc4_notify_module_data is divided into two u16:
580 *  upper u16: magic number for ALSA kcontrol types: 0xA15A
581 *  lower u16: param_id of the control, which is the type of the control
582 * The event_data contains the struct sof_ipc4_control_msg_payload of the control
583 * which sent the notification.
584 */
585#define SOF_IPC4_NOTIFY_MODULE_EVENTID_ALSA_MAGIC_MASK		GENMASK(31, 16)
586#define SOF_IPC4_NOTIFY_MODULE_EVENTID_ALSA_MAGIC_VAL		0xA15A0000
587#define SOF_IPC4_NOTIFY_MODULE_EVENTID_ALSA_PARAMID_MASK	GENMASK(15, 0)
588
589/** @}*/
590
591#endif