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hdaudio.h
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linux-6.19.14/include/sound/hdaudio.h
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * HD-audio core stuff 4 */ 5 6#ifndef __SOUND_HDAUDIO_H 7#define __SOUND_HDAUDIO_H 8 9#include <linux/device.h> 10#include <linux/interrupt.h> 11#include <linux/io.h> 12#include <linux/io-64-nonatomic-lo-hi.h> 13#include <linux/iopoll.h> 14#include <linux/pci.h> 15#include <linux/pm_runtime.h> 16#include <linux/timecounter.h> 17#include <sound/core.h> 18#include <sound/pcm.h> 19#include <sound/memalloc.h> 20#include <sound/hda_verbs.h> 21#include <drm/intel/i915_component.h> 22 23/* codec node id */ 24typedef u16 hda_nid_t; 25 26struct hdac_bus; 27struct hdac_stream; 28struct hdac_device; 29struct hdac_driver; 30struct hdac_widget_tree; 31struct hda_device_id; 32 33/* 34 * exported bus type 35 */ 36extern const struct bus_type snd_hda_bus_type; 37 38/* 39 * generic arrays 40 */ 41struct snd_array { 42 unsigned int used; 43 unsigned int alloced; 44 unsigned int elem_size; 45 unsigned int alloc_align; 46 void *list; 47}; 48 49/* 50 * HD-audio codec base device 51 */ 52struct hdac_device { 53 struct device dev; 54 int type; 55 struct hdac_bus *bus; 56 unsigned int addr; /* codec address */ 57 struct list_head list; /* list point for bus codec_list */ 58 59 hda_nid_t afg; /* AFG node id */ 60 hda_nid_t mfg; /* MFG node id */ 61 62 /* ids */ 63 unsigned int vendor_id; 64 unsigned int subsystem_id; 65 unsigned int revision_id; 66 unsigned int afg_function_id; 67 unsigned int mfg_function_id; 68 unsigned int afg_unsol:1; 69 unsigned int mfg_unsol:1; 70 71 unsigned int power_caps; /* FG power caps */ 72 73 const char *vendor_name; /* codec vendor name */ 74 const char *chip_name; /* codec chip name */ 75 76 /* verb exec op override */ 77 int (*exec_verb)(struct hdac_device *dev, unsigned int cmd, 78 unsigned int flags, unsigned int *res); 79 80 /* widgets */ 81 unsigned int num_nodes; 82 hda_nid_t start_nid, end_nid; 83 84 /* misc flags */ 85 atomic_t in_pm; /* suspend/resume being performed */ 86 87 /* sysfs */ 88 struct mutex widget_lock; 89 struct hdac_widget_tree *widgets; 90 91 /* regmap */ 92 struct regmap *regmap; 93 struct mutex regmap_lock; 94 struct snd_array vendor_verbs; 95 bool lazy_cache:1; /* don't wake up for writes */ 96 bool caps_overwriting:1; /* caps overwrite being in process */ 97 bool cache_coef:1; /* cache COEF read/write too */ 98 unsigned int registered:1; /* codec was registered */ 99}; 100 101/* device/driver type used for matching */ 102enum { 103 HDA_DEV_CORE, 104 HDA_DEV_LEGACY, 105 HDA_DEV_ASOC, 106}; 107 108enum { 109 SND_SKL_PCI_BIND_AUTO, /* automatic selection based on pci class */ 110 SND_SKL_PCI_BIND_LEGACY,/* bind only with legacy driver */ 111 SND_SKL_PCI_BIND_ASOC /* bind only with ASoC driver */ 112}; 113 114/* direction */ 115enum { 116 HDA_INPUT, HDA_OUTPUT 117}; 118 119#define dev_to_hdac_dev(_dev) container_of(_dev, struct hdac_device, dev) 120 121int snd_hdac_device_init(struct hdac_device *dev, struct hdac_bus *bus, 122 const char *name, unsigned int addr); 123void snd_hdac_device_exit(struct hdac_device *dev); 124int snd_hdac_device_register(struct hdac_device *codec); 125void snd_hdac_device_unregister(struct hdac_device *codec); 126int snd_hdac_device_set_chip_name(struct hdac_device *codec, const char *name); 127int snd_hdac_codec_modalias(const struct hdac_device *hdac, char *buf, size_t size); 128 129int snd_hdac_refresh_widgets(struct hdac_device *codec); 130 131int snd_hdac_read(struct hdac_device *codec, hda_nid_t nid, 132 unsigned int verb, unsigned int parm, unsigned int *res); 133int _snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, int parm, 134 unsigned int *res); 135int snd_hdac_read_parm_uncached(struct hdac_device *codec, hda_nid_t nid, 136 int parm); 137int snd_hdac_override_parm(struct hdac_device *codec, hda_nid_t nid, 138 unsigned int parm, unsigned int val); 139int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid, 140 hda_nid_t *conn_list, int max_conns); 141int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid, 142 hda_nid_t *start_id); 143unsigned int snd_hdac_stream_format_bits(snd_pcm_format_t format, snd_pcm_subformat_t subformat, 144 unsigned int maxbits); 145unsigned int snd_hdac_stream_format(unsigned int channels, unsigned int bits, unsigned int rate); 146unsigned int snd_hdac_spdif_stream_format(unsigned int channels, unsigned int bits, 147 unsigned int rate, unsigned short spdif_ctls); 148int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid, 149 u32 *ratesp, u64 *formatsp, u32 *subformatsp, 150 unsigned int *bpsp); 151bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid, 152 unsigned int format); 153 154int snd_hdac_codec_read(struct hdac_device *hdac, hda_nid_t nid, 155 int flags, unsigned int verb, unsigned int parm); 156int snd_hdac_codec_write(struct hdac_device *hdac, hda_nid_t nid, 157 int flags, unsigned int verb, unsigned int parm); 158bool snd_hdac_check_power_state(struct hdac_device *hdac, 159 hda_nid_t nid, unsigned int target_state); 160unsigned int snd_hdac_sync_power_state(struct hdac_device *hdac, 161 hda_nid_t nid, unsigned int target_state); 162/** 163 * snd_hdac_read_parm - read a codec parameter 164 * @codec: the codec object 165 * @nid: NID to read a parameter 166 * @parm: parameter to read 167 * 168 * Returns -1 for error. If you need to distinguish the error more 169 * strictly, use _snd_hdac_read_parm() directly. 170 */ 171static inline int snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, 172 int parm) 173{ 174 unsigned int val; 175 176 return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val; 177} 178 179#ifdef CONFIG_PM 180int snd_hdac_power_up(struct hdac_device *codec); 181int snd_hdac_power_down(struct hdac_device *codec); 182int snd_hdac_power_up_pm(struct hdac_device *codec); 183int snd_hdac_power_down_pm(struct hdac_device *codec); 184int snd_hdac_keep_power_up(struct hdac_device *codec); 185 186/* call this at entering into suspend/resume callbacks in codec driver */ 187static inline void snd_hdac_enter_pm(struct hdac_device *codec) 188{ 189 atomic_inc(&codec->in_pm); 190} 191 192/* call this at leaving from suspend/resume callbacks in codec driver */ 193static inline void snd_hdac_leave_pm(struct hdac_device *codec) 194{ 195 atomic_dec(&codec->in_pm); 196} 197 198static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) 199{ 200 return atomic_read(&codec->in_pm); 201} 202 203static inline bool snd_hdac_is_power_on(struct hdac_device *codec) 204{ 205 return !pm_runtime_suspended(&codec->dev); 206} 207#else 208static inline int snd_hdac_power_up(struct hdac_device *codec) { return 0; } 209static inline int snd_hdac_power_down(struct hdac_device *codec) { return 0; } 210static inline int snd_hdac_power_up_pm(struct hdac_device *codec) { return 0; } 211static inline int snd_hdac_power_down_pm(struct hdac_device *codec) { return 0; } 212static inline int snd_hdac_keep_power_up(struct hdac_device *codec) { return 0; } 213static inline void snd_hdac_enter_pm(struct hdac_device *codec) {} 214static inline void snd_hdac_leave_pm(struct hdac_device *codec) {} 215static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) { return false; } 216static inline bool snd_hdac_is_power_on(struct hdac_device *codec) { return true; } 217#endif 218 219/* 220 * HD-audio codec base driver 221 */ 222struct hdac_driver { 223 struct device_driver driver; 224 int type; 225 const struct hda_device_id *id_table; 226 int (*match)(struct hdac_device *dev, const struct hdac_driver *drv); 227 void (*unsol_event)(struct hdac_device *dev, unsigned int event); 228 229 /* fields used by ext bus APIs */ 230 int (*probe)(struct hdac_device *dev); 231 int (*remove)(struct hdac_device *dev); 232 void (*shutdown)(struct hdac_device *dev); 233}; 234 235#define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver) 236 237const struct hda_device_id * 238hdac_get_device_id(struct hdac_device *hdev, const struct hdac_driver *drv); 239 240/* 241 * Bus verb operators 242 */ 243struct hdac_bus_ops { 244 /* send a single command */ 245 int (*command)(struct hdac_bus *bus, unsigned int cmd); 246 /* get a response from the last command */ 247 int (*get_response)(struct hdac_bus *bus, unsigned int addr, 248 unsigned int *res); 249 /* notify of codec link power-up/down */ 250 void (*link_power)(struct hdac_device *hdev, bool enable); 251}; 252 253/* 254 * ops used for ASoC HDA codec drivers 255 */ 256struct hdac_ext_bus_ops { 257 int (*hdev_attach)(struct hdac_device *hdev); 258 int (*hdev_detach)(struct hdac_device *hdev); 259}; 260 261#define HDA_UNSOL_QUEUE_SIZE 64 262#define HDA_MAX_CODECS 8 /* limit by controller side */ 263 264/* 265 * CORB/RIRB 266 * 267 * Each CORB entry is 4byte, RIRB is 8byte 268 */ 269struct hdac_rb { 270 __le32 *buf; /* virtual address of CORB/RIRB buffer */ 271 dma_addr_t addr; /* physical address of CORB/RIRB buffer */ 272 unsigned short rp, wp; /* RIRB read/write pointers */ 273 int cmds[HDA_MAX_CODECS]; /* number of pending requests */ 274 u32 res[HDA_MAX_CODECS]; /* last read value */ 275}; 276 277/* 278 * HD-audio bus base driver 279 * 280 * @ppcap: pp capabilities pointer 281 * @spbcap: SPIB capabilities pointer 282 * @mlcap: MultiLink capabilities pointer 283 * @gtscap: gts capabilities pointer 284 * @drsmcap: dma resume capabilities pointer 285 * @num_streams: streams supported 286 * @idx: HDA link index 287 * @hlink_list: link list of HDA links 288 * @lock: lock for link and display power mgmt 289 * @cmd_dma_state: state of cmd DMAs: CORB and RIRB 290 */ 291struct hdac_bus { 292 struct device *dev; 293 const struct hdac_bus_ops *ops; 294 const struct hdac_ext_bus_ops *ext_ops; 295 296 /* h/w resources */ 297 unsigned long addr; 298 void __iomem *remap_addr; 299 int irq; 300 301 void __iomem *ppcap; 302 void __iomem *spbcap; 303 void __iomem *mlcap; 304 void __iomem *gtscap; 305 void __iomem *drsmcap; 306 307 /* codec linked list */ 308 struct list_head codec_list; 309 unsigned int num_codecs; 310 311 /* link caddr -> codec */ 312 struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1]; 313 314 /* unsolicited event queue */ 315 u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */ 316 unsigned int unsol_rp, unsol_wp; 317 struct work_struct unsol_work; 318 319 /* bit flags of detected codecs */ 320 unsigned long codec_mask; 321 322 /* bit flags of powered codecs */ 323 unsigned long codec_powered; 324 325 /* CORB/RIRB */ 326 struct hdac_rb corb; 327 struct hdac_rb rirb; 328 unsigned int last_cmd[HDA_MAX_CODECS]; /* last sent command */ 329 wait_queue_head_t rirb_wq; 330 331 /* CORB/RIRB and position buffers */ 332 struct snd_dma_buffer rb; 333 struct snd_dma_buffer posbuf; 334 int dma_type; /* SNDRV_DMA_TYPE_XXX for CORB/RIRB */ 335 336 /* hdac_stream linked list */ 337 struct list_head stream_list; 338 339 /* operation state */ 340 bool chip_init:1; /* h/w initialized */ 341 342 /* behavior flags */ 343 bool aligned_mmio:1; /* aligned MMIO access */ 344 bool sync_write:1; /* sync after verb write */ 345 bool use_posbuf:1; /* use position buffer */ 346 bool snoop:1; /* enable snooping */ 347 bool align_bdle_4k:1; /* BDLE align 4K boundary */ 348 bool reverse_assign:1; /* assign devices in reverse order */ 349 bool corbrp_self_clear:1; /* CORBRP clears itself after reset */ 350 bool polling_mode:1; 351 bool needs_damn_long_delay:1; 352 bool not_use_interrupts:1; /* prohibiting the RIRB IRQ */ 353 bool access_sdnctl_in_dword:1; /* accessing the sdnctl register by dword */ 354 bool use_pio_for_commands:1; /* Use PIO instead of CORB for commands */ 355 356 int poll_count; 357 358 int bdl_pos_adj; /* BDL position adjustment */ 359 360 /* delay time in us for dma stop */ 361 unsigned int dma_stop_delay; 362 363 /* locks */ 364 spinlock_t reg_lock; 365 struct mutex cmd_mutex; 366 struct mutex lock; 367 368 /* DRM component interface */ 369 struct drm_audio_component *audio_component; 370 long display_power_status; 371 unsigned long display_power_active; 372 373 /* parameters required for enhanced capabilities */ 374 int num_streams; 375 int idx; 376 377 /* link management */ 378 struct list_head hlink_list; 379 bool cmd_dma_state; 380 381 /* factor used to derive STRIPE control value */ 382 unsigned int sdo_limit; 383 384 /* address offset between host and hadc */ 385 dma_addr_t addr_offset; 386}; 387 388int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev, 389 const struct hdac_bus_ops *ops); 390void snd_hdac_bus_exit(struct hdac_bus *bus); 391int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr, 392 unsigned int cmd, unsigned int *res); 393 394void snd_hdac_codec_link_up(struct hdac_device *codec); 395void snd_hdac_codec_link_down(struct hdac_device *codec); 396 397int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val); 398int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr, 399 unsigned int *res); 400int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus); 401 402bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset); 403void snd_hdac_bus_stop_chip(struct hdac_bus *bus); 404void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus); 405void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus); 406void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus); 407void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus); 408int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset); 409void snd_hdac_bus_link_power(struct hdac_device *hdev, bool enable); 410 411void snd_hdac_bus_update_rirb(struct hdac_bus *bus); 412int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status, 413 void (*ack)(struct hdac_bus *, 414 struct hdac_stream *)); 415 416int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus); 417void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus); 418 419#ifdef CONFIG_SND_HDA_ALIGNED_MMIO 420unsigned int snd_hdac_aligned_read(void __iomem *addr, unsigned int mask); 421void snd_hdac_aligned_write(unsigned int val, void __iomem *addr, 422 unsigned int mask); 423#define snd_hdac_aligned_mmio(bus) (bus)->aligned_mmio 424#else 425#define snd_hdac_aligned_mmio(bus) false 426#define snd_hdac_aligned_read(addr, mask) 0 427#define snd_hdac_aligned_write(val, addr, mask) do {} while (0) 428#endif 429 430static inline void snd_hdac_reg_writeb(struct hdac_bus *bus, void __iomem *addr, 431 u8 val) 432{ 433 if (snd_hdac_aligned_mmio(bus)) 434 snd_hdac_aligned_write(val, addr, 0xff); 435 else 436 writeb(val, addr); 437} 438 439static inline void snd_hdac_reg_writew(struct hdac_bus *bus, void __iomem *addr, 440 u16 val) 441{ 442 if (snd_hdac_aligned_mmio(bus)) 443 snd_hdac_aligned_write(val, addr, 0xffff); 444 else 445 writew(val, addr); 446} 447 448static inline u8 snd_hdac_reg_readb(struct hdac_bus *bus, void __iomem *addr) 449{ 450 return snd_hdac_aligned_mmio(bus) ? 451 snd_hdac_aligned_read(addr, 0xff) : readb(addr); 452} 453 454static inline u16 snd_hdac_reg_readw(struct hdac_bus *bus, void __iomem *addr) 455{ 456 return snd_hdac_aligned_mmio(bus) ? 457 snd_hdac_aligned_read(addr, 0xffff) : readw(addr); 458} 459 460#define snd_hdac_reg_writel(bus, addr, val) writel(val, addr) 461#define snd_hdac_reg_readl(bus, addr) readl(addr) 462#define snd_hdac_reg_writeq(bus, addr, val) writeq(val, addr) 463#define snd_hdac_reg_readq(bus, addr) readq(addr) 464 465/* 466 * macros for easy use 467 */ 468#define _snd_hdac_chip_writeb(chip, reg, value) \ 469 snd_hdac_reg_writeb(chip, (chip)->remap_addr + (reg), value) 470#define _snd_hdac_chip_readb(chip, reg) \ 471 snd_hdac_reg_readb(chip, (chip)->remap_addr + (reg)) 472#define _snd_hdac_chip_writew(chip, reg, value) \ 473 snd_hdac_reg_writew(chip, (chip)->remap_addr + (reg), value) 474#define _snd_hdac_chip_readw(chip, reg) \ 475 snd_hdac_reg_readw(chip, (chip)->remap_addr + (reg)) 476#define _snd_hdac_chip_writel(chip, reg, value) \ 477 snd_hdac_reg_writel(chip, (chip)->remap_addr + (reg), value) 478#define _snd_hdac_chip_readl(chip, reg) \ 479 snd_hdac_reg_readl(chip, (chip)->remap_addr + (reg)) 480 481/* read/write a register, pass without AZX_REG_ prefix */ 482#define snd_hdac_chip_writel(chip, reg, value) \ 483 _snd_hdac_chip_writel(chip, AZX_REG_ ## reg, value) 484#define snd_hdac_chip_writew(chip, reg, value) \ 485 _snd_hdac_chip_writew(chip, AZX_REG_ ## reg, value) 486#define snd_hdac_chip_writeb(chip, reg, value) \ 487 _snd_hdac_chip_writeb(chip, AZX_REG_ ## reg, value) 488#define snd_hdac_chip_readl(chip, reg) \ 489 _snd_hdac_chip_readl(chip, AZX_REG_ ## reg) 490#define snd_hdac_chip_readw(chip, reg) \ 491 _snd_hdac_chip_readw(chip, AZX_REG_ ## reg) 492#define snd_hdac_chip_readb(chip, reg) \ 493 _snd_hdac_chip_readb(chip, AZX_REG_ ## reg) 494 495/* update a register, pass without AZX_REG_ prefix */ 496#define snd_hdac_chip_updatel(chip, reg, mask, val) \ 497 snd_hdac_chip_writel(chip, reg, \ 498 (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val)) 499#define snd_hdac_chip_updatew(chip, reg, mask, val) \ 500 snd_hdac_chip_writew(chip, reg, \ 501 (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val)) 502#define snd_hdac_chip_updateb(chip, reg, mask, val) \ 503 snd_hdac_chip_writeb(chip, reg, \ 504 (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val)) 505 506/* update register macro */ 507#define snd_hdac_updatel(addr, reg, mask, val) \ 508 writel(((readl(addr + reg) & ~(mask)) | (val)), addr + reg) 509 510#define snd_hdac_updatew(addr, reg, mask, val) \ 511 writew(((readw(addr + reg) & ~(mask)) | (val)), addr + reg) 512 513/* 514 * HD-audio stream 515 */ 516struct hdac_stream { 517 struct hdac_bus *bus; 518 struct snd_dma_buffer bdl; /* BDL buffer */ 519 __le32 *posbuf; /* position buffer pointer */ 520 int direction; /* playback / capture (SNDRV_PCM_STREAM_*) */ 521 522 unsigned int bufsize; /* size of the play buffer in bytes */ 523 unsigned int period_bytes; /* size of the period in bytes */ 524 unsigned int frags; /* number for period in the play buffer */ 525 unsigned int fifo_size; /* FIFO size */ 526 527 void __iomem *sd_addr; /* stream descriptor pointer */ 528 529 void __iomem *spib_addr; /* software position in buffers stream pointer */ 530 void __iomem *fifo_addr; /* software position Max fifos stream pointer */ 531 532 void __iomem *dpibr_addr; /* DMA position in buffer resume pointer */ 533 u32 dpib; /* DMA position in buffer */ 534 u32 lpib; /* Linear position in buffer */ 535 536 u32 sd_int_sta_mask; /* stream int status mask */ 537 538 /* pcm support */ 539 struct snd_pcm_substream *substream; /* assigned substream, 540 * set in PCM open 541 */ 542 struct snd_compr_stream *cstream; 543 unsigned int format_val; /* format value to be set in the 544 * controller and the codec 545 */ 546 unsigned char stream_tag; /* assigned stream */ 547 unsigned char index; /* stream index */ 548 int assigned_key; /* last device# key assigned to */ 549 550 bool opened:1; 551 bool running:1; 552 bool prepared:1; 553 bool no_period_wakeup:1; 554 bool locked:1; 555 bool stripe:1; /* apply stripe control */ 556 557 u64 curr_pos; 558 /* timestamp */ 559 unsigned long start_wallclk; /* start + minimum wallclk */ 560 unsigned long period_wallclk; /* wallclk for period */ 561 struct timecounter tc; 562 struct cyclecounter cc; 563 int delay_negative_threshold; 564 565 struct list_head list; 566#ifdef CONFIG_SND_HDA_DSP_LOADER 567 /* DSP access mutex */ 568 struct mutex dsp_mutex; 569#endif 570}; 571 572void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev, 573 int idx, int direction, int tag); 574struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus, 575 struct snd_pcm_substream *substream); 576void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev); 577void snd_hdac_stream_release(struct hdac_stream *azx_dev); 578struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus, 579 int dir, int stream_tag); 580 581int snd_hdac_stream_setup(struct hdac_stream *azx_dev, bool code_loading); 582void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev); 583int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev); 584int snd_hdac_stream_set_params(struct hdac_stream *azx_dev, 585 unsigned int format_val); 586void snd_hdac_stream_start(struct hdac_stream *azx_dev); 587void snd_hdac_stream_stop(struct hdac_stream *azx_dev); 588void snd_hdac_stop_streams(struct hdac_bus *bus); 589void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus); 590void snd_hdac_stream_reset(struct hdac_stream *azx_dev); 591void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set, 592 unsigned int streams, unsigned int reg); 593void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start, 594 unsigned int streams); 595void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev, 596 unsigned int streams, bool start); 597int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus, 598 struct snd_pcm_substream *substream); 599 600void snd_hdac_stream_spbcap_enable(struct hdac_bus *chip, 601 bool enable, int index); 602int snd_hdac_stream_set_spib(struct hdac_bus *bus, 603 struct hdac_stream *azx_dev, u32 value); 604void snd_hdac_stream_drsm_enable(struct hdac_bus *bus, 605 bool enable, int index); 606int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev); 607int snd_hdac_stream_set_dpibr(struct hdac_bus *bus, 608 struct hdac_stream *azx_dev, u32 value); 609int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value); 610 611/* 612 * macros for easy use 613 */ 614/* read/write a register, pass without AZX_REG_ prefix */ 615#define snd_hdac_stream_writel(dev, reg, value) \ 616 snd_hdac_reg_writel((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value) 617#define snd_hdac_stream_writew(dev, reg, value) \ 618 snd_hdac_reg_writew((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value) 619#define snd_hdac_stream_writeb(dev, reg, value) \ 620 snd_hdac_reg_writeb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value) 621#define snd_hdac_stream_readl(dev, reg) \ 622 snd_hdac_reg_readl((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) 623#define snd_hdac_stream_readw(dev, reg) \ 624 snd_hdac_reg_readw((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) 625#define snd_hdac_stream_readb(dev, reg) \ 626 snd_hdac_reg_readb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) 627#define snd_hdac_stream_readb_poll(dev, reg, val, cond, delay_us, timeout_us) \ 628 read_poll_timeout_atomic(snd_hdac_reg_readb, val, cond, delay_us, timeout_us, \ 629 false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) 630#define snd_hdac_stream_readw_poll(dev, reg, val, cond, delay_us, timeout_us) \ 631 read_poll_timeout_atomic(snd_hdac_reg_readw, val, cond, delay_us, timeout_us, \ 632 false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) 633#define snd_hdac_stream_readl_poll(dev, reg, val, cond, delay_us, timeout_us) \ 634 read_poll_timeout_atomic(snd_hdac_reg_readl, val, cond, delay_us, timeout_us, \ 635 false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) 636 637/* update a register, pass without AZX_REG_ prefix */ 638#define snd_hdac_stream_updatel(dev, reg, mask, val) \ 639 snd_hdac_stream_writel(dev, reg, \ 640 (snd_hdac_stream_readl(dev, reg) & \ 641 ~(mask)) | (val)) 642#define snd_hdac_stream_updatew(dev, reg, mask, val) \ 643 snd_hdac_stream_writew(dev, reg, \ 644 (snd_hdac_stream_readw(dev, reg) & \ 645 ~(mask)) | (val)) 646#define snd_hdac_stream_updateb(dev, reg, mask, val) \ 647 snd_hdac_stream_writeb(dev, reg, \ 648 (snd_hdac_stream_readb(dev, reg) & \ 649 ~(mask)) | (val)) 650 651#ifdef CONFIG_SND_HDA_DSP_LOADER 652/* DSP lock helpers */ 653#define snd_hdac_dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex) 654#define snd_hdac_dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex) 655#define snd_hdac_dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex) 656#define snd_hdac_stream_is_locked(dev) ((dev)->locked) 657DEFINE_GUARD(snd_hdac_dsp_lock, struct hdac_stream *, snd_hdac_dsp_lock(_T), snd_hdac_dsp_unlock(_T)) 658/* DSP loader helpers */ 659int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, 660 unsigned int byte_size, struct snd_dma_buffer *bufp); 661void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start); 662void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, 663 struct snd_dma_buffer *dmab); 664#else /* CONFIG_SND_HDA_DSP_LOADER */ 665#define snd_hdac_dsp_lock_init(dev) do {} while (0) 666#define snd_hdac_dsp_lock(dev) do {} while (0) 667#define snd_hdac_dsp_unlock(dev) do {} while (0) 668#define snd_hdac_stream_is_locked(dev) 0 669 670static inline int 671snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, 672 unsigned int byte_size, struct snd_dma_buffer *bufp) 673{ 674 return 0; 675} 676 677static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start) 678{ 679} 680 681static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, 682 struct snd_dma_buffer *dmab) 683{ 684} 685#endif /* CONFIG_SND_HDA_DSP_LOADER */ 686 687/* 688 * Easy macros for widget capabilities 689 */ 690#define snd_hdac_get_wcaps(codec, nid) \ 691 snd_hdac_read_parm(codec, nid, AC_PAR_AUDIO_WIDGET_CAP) 692 693/* get the widget type from widget capability bits */ 694static inline int snd_hdac_get_wcaps_type(unsigned int wcaps) 695{ 696 if (!wcaps) 697 return -1; /* invalid type */ 698 return (wcaps & AC_WCAP_TYPE) >> AC_WCAP_TYPE_SHIFT; 699} 700 701/* get the number of supported channels */ 702static inline unsigned int snd_hdac_get_wcaps_channels(u32 wcaps) 703{ 704 unsigned int chans; 705 706 chans = (wcaps & AC_WCAP_CHAN_CNT_EXT) >> 13; 707 chans = (chans + 1) * 2; 708 709 return chans; 710} 711 712/* 713 * generic array helpers 714 */ 715void *snd_array_new(struct snd_array *array); 716void snd_array_free(struct snd_array *array); 717static inline void snd_array_init(struct snd_array *array, unsigned int size, 718 unsigned int align) 719{ 720 array->elem_size = size; 721 array->alloc_align = align; 722} 723 724static inline void *snd_array_elem(struct snd_array *array, unsigned int idx) 725{ 726 return array->list + idx * array->elem_size; 727} 728 729static inline unsigned int snd_array_index(struct snd_array *array, void *ptr) 730{ 731 return (unsigned long)(ptr - array->list) / array->elem_size; 732} 733 734/* a helper macro to iterate for each snd_array element */ 735#define snd_array_for_each(array, idx, ptr) \ 736 for ((idx) = 0, (ptr) = (array)->list; (idx) < (array)->used; \ 737 (ptr) = snd_array_elem(array, ++(idx))) 738 739/* 740 * Device matching 741 */ 742 743#define HDA_CONTROLLER_IS_HSW(pci) (pci_match_id((struct pci_device_id []){ \ 744 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_0) }, \ 745 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_2) }, \ 746 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_3) }, \ 747 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_BDW) }, \ 748 { } \ 749 }, pci)) 750 751#define HDA_CONTROLLER_IS_APL(pci) (pci_match_id((struct pci_device_id []){ \ 752 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_APL) }, \ 753 { } \ 754 }, pci)) 755 756#define HDA_CONTROLLER_IN_GPU(pci) (pci_match_id((struct pci_device_id []){ \ 757 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG1) }, \ 758 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_0) }, \ 759 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_1) }, \ 760 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_2) }, \ 761 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_BMG) }, \ 762 { } \ 763 }, pci) || HDA_CONTROLLER_IS_HSW(pci)) 764 765#endif /* __SOUND_HDAUDIO_H */
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