cs48l32_registers.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Register definitions for Cirrus Logic CS48L32
  4 *
  5 * Copyright (C) 2017-2018, 2020, 2022, 2025 Cirrus Logic, Inc. and
  6 *               Cirrus Logic International Semiconductor Ltd.
  7 */
  8
  9#ifndef CS48L32_REGISTERS_H
 10#define CS48L32_REGISTERS_H
 11
 12/* Register Addresses. */
 13#define CS48L32_DEVID				0x0
 14#define CS48L32_REVID				0x4
 15#define CS48L32_OTPID				0x10
 16#define CS48L32_SFT_RESET			0x20
 17#define CS48L32_CTRL_IF_DEBUG3			0xA8
 18#define CS48L32_MCU_CTRL1			0x804
 19#define CS48L32_GPIO1_CTRL1			0xc08
 20#define CS48L32_GPIO3_CTRL1			0xc10
 21#define CS48L32_GPIO7_CTRL1			0xc20
 22#define CS48L32_GPIO16_CTRL1			0xc44
 23#define CS48L32_OUTPUT_SYS_CLK			0x1020
 24#define CS48L32_AUXPDM_CTRL			0x1044
 25#define CS48L32_AUXPDM_CTRL2			0x105c
 26#define CS48L32_CLOCK32K			0x1400
 27#define CS48L32_SYSTEM_CLOCK1			0x1404
 28#define CS48L32_SYSTEM_CLOCK2			0x1408
 29#define CS48L32_SAMPLE_RATE1			0x1420
 30#define CS48L32_SAMPLE_RATE2			0x1424
 31#define CS48L32_SAMPLE_RATE3			0x1428
 32#define CS48L32_SAMPLE_RATE4			0x142c
 33#define CS48L32_DSP_CLOCK1			0x1510
 34#define CS48L32_FLL1_CONTROL1			0x1c00
 35#define CS48L32_FLL1_CONTROL5			0x1c10
 36#define CS48L32_FLL1_CONTROL6			0x1c14
 37#define CS48L32_FLL1_GPIO_CLOCK			0x1ca0
 38#define CS48L32_CHARGE_PUMP1			0x2000
 39#define CS48L32_LDO2_CTRL1			0x2408
 40#define CS48L32_MICBIAS_CTRL1			0x2410
 41#define CS48L32_MICBIAS_CTRL5			0x2418
 42#define CS48L32_IRQ1_CTRL_AOD			0x2710
 43#define CS48L32_AOD_PAD_CTRL			0x2718
 44#define CS48L32_INPUT_CONTROL			0x4000
 45#define CS48L32_INPUT_STATUS			0x4004
 46#define CS48L32_INPUT_RATE_CONTROL		0x4008
 47#define CS48L32_INPUT_CONTROL2			0x400c
 48#define CS48L32_INPUT_CONTROL3			0x4014
 49#define CS48L32_INPUT1_CONTROL1			0x4020
 50#define CS48L32_IN1L_CONTROL1			0x4024
 51#define CS48L32_IN1L_CONTROL2			0x4028
 52#define CS48L32_IN1R_CONTROL1			0x4044
 53#define CS48L32_IN1R_CONTROL2			0x4048
 54#define CS48L32_INPUT2_CONTROL1			0x4060
 55#define CS48L32_IN2L_CONTROL1			0x4064
 56#define CS48L32_IN2L_CONTROL2			0x4068
 57#define CS48L32_IN2R_CONTROL1			0x4084
 58#define CS48L32_IN2R_CONTROL2			0x4088
 59#define CS48L32_INPUT_HPF_CONTROL		0x4244
 60#define CS48L32_INPUT_VOL_CONTROL		0x4248
 61#define CS48L32_AUXPDM_CONTROL1			0x4300
 62#define CS48L32_AUXPDM_CONTROL2			0x4304
 63#define CS48L32_AUXPDM1_CONTROL1		0x4308
 64#define CS48L32_AUXPDM2_CONTROL1		0x4310
 65#define CS48L32_ADC1L_ANA_CONTROL1		0x4688
 66#define CS48L32_ADC1R_ANA_CONTROL1		0x468c
 67#define CS48L32_ASP1_ENABLES1			0x6000
 68#define CS48L32_ASP1_CONTROL3			0x600C
 69#define CS48L32_ASP1_DATA_CONTROL5		0x6040
 70#define CS48L32_ASP2_ENABLES1			0x6080
 71#define CS48L32_ASP2_CONTROL3			0x608C
 72#define CS48L32_ASP2_DATA_CONTROL5		0x60c0
 73#define CS48L32_ASP1TX1_INPUT1			0x8200
 74#define CS48L32_ASP1TX2_INPUT1			0x8210
 75#define CS48L32_ASP1TX3_INPUT1			0x8220
 76#define CS48L32_ASP1TX4_INPUT1			0x8230
 77#define CS48L32_ASP1TX5_INPUT1			0x8240
 78#define CS48L32_ASP1TX6_INPUT1			0x8250
 79#define CS48L32_ASP1TX7_INPUT1			0x8260
 80#define CS48L32_ASP1TX8_INPUT1			0x8270
 81#define CS48L32_ASP1TX8_INPUT4			0x827c
 82#define CS48L32_ASP2TX1_INPUT1			0x8300
 83#define CS48L32_ASP2TX2_INPUT1			0x8310
 84#define CS48L32_ASP2TX3_INPUT1			0x8320
 85#define CS48L32_ASP2TX4_INPUT1			0x8330
 86#define CS48L32_ASP2TX4_INPUT4			0x833c
 87#define CS48L32_ISRC1INT1_INPUT1		0x8980
 88#define CS48L32_ISRC1INT2_INPUT1		0x8990
 89#define CS48L32_ISRC1INT3_INPUT1		0x89a0
 90#define CS48L32_ISRC1INT4_INPUT1		0x89b0
 91#define CS48L32_ISRC1DEC1_INPUT1		0x89c0
 92#define CS48L32_ISRC1DEC2_INPUT1		0x89d0
 93#define CS48L32_ISRC1DEC3_INPUT1		0x89e0
 94#define CS48L32_ISRC1DEC4_INPUT1		0x89f0
 95#define CS48L32_ISRC2INT1_INPUT1		0x8a00
 96#define CS48L32_ISRC2INT2_INPUT1		0x8a10
 97#define CS48L32_ISRC2DEC1_INPUT1		0x8a40
 98#define CS48L32_ISRC2DEC2_INPUT1		0x8a50
 99#define CS48L32_ISRC3INT1_INPUT1		0x8a80
100#define CS48L32_ISRC3INT2_INPUT1		0x8a90
101#define CS48L32_ISRC3DEC1_INPUT1		0x8ac0
102#define CS48L32_ISRC3DEC2_INPUT1		0x8ad0
103#define CS48L32_EQ1_INPUT1			0x8b80
104#define CS48L32_EQ2_INPUT1			0x8b90
105#define CS48L32_EQ3_INPUT1			0x8ba0
106#define CS48L32_EQ4_INPUT1			0x8bb0
107#define CS48L32_EQ4_INPUT4			0x8bbc
108#define CS48L32_DRC1L_INPUT1			0x8c00
109#define CS48L32_DRC1R_INPUT1			0x8c10
110#define CS48L32_DRC1R_INPUT4			0x8c1c
111#define CS48L32_DRC2L_INPUT1			0x8c20
112#define CS48L32_DRC2R_INPUT1			0x8c30
113#define CS48L32_DRC2R_INPUT4			0x8c3c
114#define CS48L32_LHPF1_INPUT1			0x8c80
115#define CS48L32_LHPF1_INPUT4			0x8c8c
116#define CS48L32_LHPF2_INPUT1			0x8c90
117#define CS48L32_LHPF2_INPUT4			0x8c9c
118#define CS48L32_LHPF3_INPUT1			0x8ca0
119#define CS48L32_LHPF3_INPUT4			0x8cac
120#define CS48L32_LHPF4_INPUT1			0x8cb0
121#define CS48L32_LHPF4_INPUT4			0x8cbc
122#define CS48L32_DSP1RX1_INPUT1			0x9000
123#define CS48L32_DSP1RX2_INPUT1			0x9010
124#define CS48L32_DSP1RX3_INPUT1			0x9020
125#define CS48L32_DSP1RX4_INPUT1			0x9030
126#define CS48L32_DSP1RX5_INPUT1			0x9040
127#define CS48L32_DSP1RX6_INPUT1			0x9050
128#define CS48L32_DSP1RX7_INPUT1			0x9060
129#define CS48L32_DSP1RX8_INPUT1			0x9070
130#define CS48L32_DSP1RX8_INPUT4			0x907c
131#define CS48L32_ISRC1_CONTROL1			0xa400
132#define CS48L32_ISRC1_CONTROL2			0xa404
133#define CS48L32_ISRC2_CONTROL1			0xa510
134#define CS48L32_ISRC2_CONTROL2			0xa514
135#define CS48L32_ISRC3_CONTROL1			0xa620
136#define CS48L32_ISRC3_CONTROL2			0xa624
137#define CS48L32_FX_SAMPLE_RATE			0xa800
138#define CS48L32_EQ_CONTROL1			0xa808
139#define CS48L32_EQ_CONTROL2			0xa80c
140#define CS48L32_EQ1_GAIN1			0xa810
141#define CS48L32_EQ1_GAIN2			0xa814
142#define CS48L32_EQ1_BAND1_COEFF1		0xa818
143#define CS48L32_EQ1_BAND1_COEFF2		0xa81c
144#define CS48L32_EQ1_BAND1_PG			0xa820
145#define CS48L32_EQ1_BAND2_COEFF1		0xa824
146#define CS48L32_EQ1_BAND2_COEFF2		0xa828
147#define CS48L32_EQ1_BAND2_PG			0xa82c
148#define CS48L32_EQ1_BAND3_COEFF1		0xa830
149#define CS48L32_EQ1_BAND3_COEFF2		0xa834
150#define CS48L32_EQ1_BAND3_PG			0xa838
151#define CS48L32_EQ1_BAND4_COEFF1		0xa83c
152#define CS48L32_EQ1_BAND4_COEFF2		0xa840
153#define CS48L32_EQ1_BAND4_PG			0xa844
154#define CS48L32_EQ1_BAND5_COEFF1		0xa848
155#define CS48L32_EQ1_BAND5_PG			0xa850
156#define CS48L32_EQ2_GAIN1			0xa854
157#define CS48L32_EQ2_GAIN2			0xa858
158#define CS48L32_EQ2_BAND1_COEFF1		0xa85c
159#define CS48L32_EQ2_BAND1_COEFF2		0xa860
160#define CS48L32_EQ2_BAND1_PG			0xa864
161#define CS48L32_EQ2_BAND2_COEFF1		0xa868
162#define CS48L32_EQ2_BAND2_COEFF2		0xa86c
163#define CS48L32_EQ2_BAND2_PG			0xa870
164#define CS48L32_EQ2_BAND3_COEFF1		0xa874
165#define CS48L32_EQ2_BAND3_COEFF2		0xa878
166#define CS48L32_EQ2_BAND3_PG			0xa87c
167#define CS48L32_EQ2_BAND4_COEFF1		0xa880
168#define CS48L32_EQ2_BAND4_COEFF2		0xa884
169#define CS48L32_EQ2_BAND4_PG			0xa888
170#define CS48L32_EQ2_BAND5_COEFF1		0xa88c
171#define CS48L32_EQ2_BAND5_PG			0xa894
172#define CS48L32_EQ3_GAIN1			0xa898
173#define CS48L32_EQ3_GAIN2			0xa89c
174#define CS48L32_EQ3_BAND1_COEFF1		0xa8a0
175#define CS48L32_EQ3_BAND1_COEFF2		0xa8a4
176#define CS48L32_EQ3_BAND1_PG			0xa8a8
177#define CS48L32_EQ3_BAND2_COEFF1		0xa8ac
178#define CS48L32_EQ3_BAND2_COEFF2		0xa8b0
179#define CS48L32_EQ3_BAND2_PG			0xa8b4
180#define CS48L32_EQ3_BAND3_COEFF1		0xa8b8
181#define CS48L32_EQ3_BAND3_COEFF2		0xa8bc
182#define CS48L32_EQ3_BAND3_PG			0xa8c0
183#define CS48L32_EQ3_BAND4_COEFF1		0xa8c4
184#define CS48L32_EQ3_BAND4_COEFF2		0xa8c8
185#define CS48L32_EQ3_BAND4_PG			0xa8cc
186#define CS48L32_EQ3_BAND5_COEFF1		0xa8d0
187#define CS48L32_EQ3_BAND5_PG			0xa8d8
188#define CS48L32_EQ4_GAIN1			0xa8dc
189#define CS48L32_EQ4_GAIN2			0xa8e0
190#define CS48L32_EQ4_BAND1_COEFF1		0xa8e4
191#define CS48L32_EQ4_BAND1_COEFF2		0xa8e8
192#define CS48L32_EQ4_BAND1_PG			0xa8ec
193#define CS48L32_EQ4_BAND2_COEFF1		0xa8f0
194#define CS48L32_EQ4_BAND2_COEFF2		0xa8f4
195#define CS48L32_EQ4_BAND2_PG			0xa8f8
196#define CS48L32_EQ4_BAND3_COEFF1		0xa8fc
197#define CS48L32_EQ4_BAND3_COEFF2		0xa900
198#define CS48L32_EQ4_BAND3_PG			0xa904
199#define CS48L32_EQ4_BAND4_COEFF1		0xa908
200#define CS48L32_EQ4_BAND4_COEFF2		0xa90c
201#define CS48L32_EQ4_BAND4_PG			0xa910
202#define CS48L32_EQ4_BAND5_COEFF1		0xa914
203#define CS48L32_EQ4_BAND5_PG			0xa91c
204#define CS48L32_LHPF_CONTROL1			0xaa30
205#define CS48L32_LHPF_CONTROL2			0xaa34
206#define CS48L32_LHPF1_COEFF			0xaa38
207#define CS48L32_LHPF2_COEFF			0xaa3c
208#define CS48L32_LHPF3_COEFF			0xaa40
209#define CS48L32_LHPF4_COEFF			0xaa44
210#define CS48L32_DRC1_CONTROL1			0xab00
211#define CS48L32_DRC1_CONTROL4			0xab0c
212#define CS48L32_DRC2_CONTROL1			0xab14
213#define CS48L32_DRC2_CONTROL4			0xab20
214#define CS48L32_TONE_GENERATOR1			0xb000
215#define CS48L32_TONE_GENERATOR2			0xb004
216#define CS48L32_COMFORT_NOISE_GENERATOR		0xb400
217#define CS48L32_US_CONTROL			0xb800
218#define CS48L32_US1_CONTROL			0xb804
219#define CS48L32_US1_DET_CONTROL			0xb808
220#define CS48L32_US2_CONTROL			0xb814
221#define CS48L32_US2_DET_CONTROL			0xb818
222#define CS48L32_DSP1_XM_SRAM_IBUS_SETUP_0	0x1700c
223#define CS48L32_DSP1_XM_SRAM_IBUS_SETUP_1	0x17010
224#define CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24	0x1706c
225#define CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0	0x17070
226#define CS48L32_DSP1_YM_SRAM_IBUS_SETUP_1	0x17074
227#define CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8	0x17090
228#define CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0	0x17094
229#define CS48L32_DSP1_PM_SRAM_IBUS_SETUP_1	0x17098
230#define CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7	0x170b0
231#define CS48L32_IRQ1_STATUS			0x18004
232#define CS48L32_IRQ1_EINT_1			0x18010
233#define CS48L32_IRQ1_EINT_2			0x18014
234#define CS48L32_IRQ1_EINT_7			0x18028
235#define CS48L32_IRQ1_EINT_9			0x18030
236#define CS48L32_IRQ1_EINT_11			0x18038
237#define CS48L32_IRQ1_STS_1			0x18090
238#define CS48L32_IRQ1_STS_6			0x180a4
239#define CS48L32_IRQ1_STS_11			0x180b8
240#define CS48L32_IRQ1_MASK_1			0x18110
241#define CS48L32_IRQ1_MASK_2			0x18114
242#define CS48L32_IRQ1_MASK_7			0x18128
243#define CS48L32_IRQ1_MASK_9			0x18130
244#define CS48L32_IRQ1_MASK_11			0x18138
245#define CS48L32_DSP1_XMEM_PACKED_0		0x2000000
246#define CS48L32_DSP1_XMEM_PACKED_LAST		0x208fff0
247#define CS48L32_DSP1_SYS_INFO_ID		0x25e0000
248#define CS48L32_DSP1_AHBM_WINDOW_DEBUG_1	0x25e2044
249#define CS48L32_DSP1_XMEM_UNPACKED24_0		0x2800000
250#define CS48L32_DSP1_XMEM_UNPACKED24_LAST	0x28bfff4
251#define CS48L32_DSP1_CLOCK_FREQ			0x2b80000
252#define CS48L32_DSP1_SAMPLE_RATE_TX8		0x2b802b8
253#define CS48L32_DSP1_SCRATCH1			0x2b805c0
254#define CS48L32_DSP1_SCRATCH4			0x2b805d8
255#define CS48L32_DSP1_CCM_CORE_CONTROL		0x2bc1000
256#define CS48L32_DSP1_STREAM_ARB_RESYNC_MSK1	0x2bc5a00
257#define CS48L32_DSP1_YMEM_PACKED_0		0x2c00000
258#define CS48L32_DSP1_YMEM_PACKED_LAST		0x2c2fff0
259#define CS48L32_DSP1_YMEM_UNPACKED24_0		0x3400000
260#define CS48L32_DSP1_YMEM_UNPACKED24_LAST	0x343fff4
261#define CS48L32_DSP1_PMEM_0			0x3800000
262#define CS48L32_DSP1_PMEM_LAST			0x3845fe8
263
264/* (0x0) DEVID */
265#define CS48L32_DEVID_MASK			0x00ffffff
266#define CS48L32_DEVID_SHIFT				 0
267
268/* (0x4) REVID */
269#define CS48L32_AREVID_MASK			0x000000f0
270#define CS48L32_AREVID_SHIFT				 4
271#define CS48L32_MTLREVID_MASK			0x0000000f
272#define CS48L32_MTLREVID_SHIFT				 0
273
274/* (0x10) OTPID */
275#define CS48L32_OTPID_MASK			0x0000000f
276
277/* (0x0804) MCU_CTRL1 */
278#define CS48L32_MCU_STS_MASK			0x0000ff00
279#define CS48L32_MCU_STS_SHIFT				 8
280
281/* (0xc08) GPIO1_CTRL1 */
282#define CS48L32_GPIOX_CTRL1_FN_MASK		0x000003ff
283
284/* (0x1020) OUTPUT_SYS_CLK */
285#define CS48L32_OPCLK_EN_SHIFT				15
286#define CS48L32_OPCLK_DIV_MASK			0x000000f8
287#define CS48L32_OPCLK_DIV_SHIFT				 3
288#define CS48L32_OPCLK_SEL_MASK			0x00000007
289
290/* (0x105c) AUXPDM_CTRL2 */
291#define CS48L32_AUXPDMDAT2_SRC_SHIFT			 4
292#define CS48L32_AUXPDMDAT1_SRC_SHIFT			 0
293
294/* (0x1400) CLOCK32K */
295#define CS48L32_CLK_32K_EN_MASK			0x00000040
296#define CS48L32_CLK_32K_SRC_MASK		0x00000003
297
298/* (0x1404) SYSTEM_CLOCK1 */
299#define CS48L32_SYSCLK_FRAC_MASK		0x00008000
300#define CS48L32_SYSCLK_FREQ_MASK		0x00000700
301#define CS48L32_SYSCLK_FREQ_SHIFT			 8
302#define CS48L32_SYSCLK_EN_SHIFT				 6
303#define CS48L32_SYSCLK_SRC_MASK			0x0000001f
304#define CS48L32_SYSCLK_SRC_SHIFT			 0
305
306/* (0x1408) SYSTEM_CLOCK2 */
307#define CS48L32_SYSCLK_FREQ_STS_MASK		0x00000700
308#define CS48L32_SYSCLK_FREQ_STS_SHIFT			 8
309
310/* (0x1420) SAMPLE_RATE1 */
311#define CS48L32_SAMPLE_RATE_1_MASK		0x0000001f
312#define CS48L32_SAMPLE_RATE_1_SHIFT			 0
313
314/* (0x1510) DSP_CLOCK1 */
315#define CS48L32_DSP_CLK_FREQ_MASK		0xffff0000
316#define CS48L32_DSP_CLK_FREQ_SHIFT			16
317
318/* (0x1c00) FLL_CONTROL1 */
319#define CS48L32_FLL_CTRL_UPD_MASK		0x00000004
320#define CS48L32_FLL_HOLD_MASK			0x00000002
321#define CS48L32_FLL_EN_MASK			0x00000001
322
323/* (0x1c04) FLL_CONTROL2 */
324#define CS48L32_FLL_LOCKDET_THR_MASK		0xf0000000
325#define CS48L32_FLL_LOCKDET_THR_SHIFT			28
326#define CS48L32_FLL_LOCKDET_MASK		0x08000000
327#define CS48L32_FLL_PHASEDET_MASK		0x00400000
328#define CS48L32_FLL_PHASEDET_SHIFT			22
329#define CS48L32_FLL_REFCLK_DIV_MASK		0x00030000
330#define CS48L32_FLL_REFCLK_DIV_SHIFT			16
331#define CS48L32_FLL_REFCLK_SRC_MASK		0x0000f000
332#define CS48L32_FLL_REFCLK_SRC_SHIFT			12
333#define CS48L32_FLL_N_MASK			0x000003ff
334#define CS48L32_FLL_N_SHIFT				 0
335
336/* (0x1c08) FLL_CONTROL3 */
337#define CS48L32_FLL_LAMBDA_MASK			0xffff0000
338#define CS48L32_FLL_LAMBDA_SHIFT			16
339#define CS48L32_FLL_THETA_MASK			0x0000ffff
340#define CS48L32_FLL_THETA_SHIFT				 0
341
342/* (0x1c0c) FLL_CONTROL4 */
343#define CS48L32_FLL_FD_GAIN_COARSE_SHIFT		16
344#define CS48L32_FLL_HP_MASK			0x00003000
345#define CS48L32_FLL_HP_SHIFT				12
346#define CS48L32_FLL_FB_DIV_MASK			0x000003ff
347#define CS48L32_FLL_FB_DIV_SHIFT			 0
348
349/* (0x1c10) FLL_CONTROL5 */
350#define CS48L32_FLL_FRC_INTEG_UPD_MASK		0x00008000
351
352/* (0x2000) CHARGE_PUMP1 */
353#define CS48L32_CP2_BYPASS_SHIFT			 1
354#define CS48L32_CP2_EN_SHIFT				 0
355
356/* (0x2408) LDO2_CTRL1 */
357#define CS48L32_LDO2_VSEL_MASK			0x000007e0
358#define CS48L32_LDO2_VSEL_SHIFT				 5
359
360/* (0x2410) MICBIAS_CTRL1 */
361#define CS48L32_MICB1_LVL_MASK			0x000001e0
362#define CS48L32_MICB1_LVL_SHIFT				 5
363#define CS48L32_MICB1_EN_SHIFT				 0
364
365/* (0x2418) MICBIAS_CTRL5 */
366#define CS48L32_MICB1C_EN_SHIFT				 8
367#define CS48L32_MICB1B_EN_SHIFT				 4
368#define CS48L32_MICB1A_EN_SHIFT				 0
369
370/* (0x2710) IRQ1_CTRL_AOD */
371#define CS48L32_IRQ_POL_MASK			0x00000400
372
373/* (0x4000) INPUT_CONTROL */
374#define CS48L32_IN2L_EN_SHIFT				 3
375#define CS48L32_IN2R_EN_SHIFT				 2
376#define CS48L32_IN1L_EN_SHIFT				 1
377#define CS48L32_IN1R_EN_SHIFT				 0
378
379/* (0x400c) INPUT_CONTROL2 */
380#define CS48L32_PDM_FLLCLK_SRC_MASK		0x0000000f
381#define CS48L32_PDM_FLLCLK_SRC_SHIFT			 0
382
383/* (0x4014) INPUT_CONTROL3 */
384#define CS48L32_IN_VU				0x20000000
385#define CS48L32_IN_VU_MASK			0x20000000
386#define CS48L32_IN_VU_SHIFT				29
387#define CS48L32_IN_VU_WIDTH				 1
388
389/* (0x4020) INPUT1_CONTROL1 */
390#define CS48L32_IN1_OSR_SHIFT				16
391#define CS48L32_IN1_PDM_SUP_MASK		0x00000300
392#define CS48L32_IN1_PDM_SUP_SHIFT			 8
393#define CS48L32_IN1_MODE_SHIFT				 0
394
395/*
396 * (0x4024) IN1L_CONTROL1
397 * (0x4044) IN1R_CONTROL1
398 */
399#define CS48L32_INx_SRC_MASK			0x30000000
400#define CS48L32_INx_SRC_SHIFT				28
401#define CS48L32_INx_RATE_MASK			0x0000f800
402#define CS48L32_INx_RATE_SHIFT				11
403#define CS48L32_INx_HPF_SHIFT				 2
404#define CS48L32_INx_LP_MODE_SHIFT			 0
405
406/*
407 * (0x4028) IN1L_CONTROL2
408 * (0x4048) IN1R_CONTROL2
409 */
410#define CS48L32_INx_MUTE_MASK			0x10000000
411#define CS48L32_INx_VOL_SHIFT				16
412#define CS48L32_INx_PGA_VOL_SHIFT			 1
413
414/* (0x4244) INPUT_HPF_CONTROL */
415#define CS48L32_IN_HPF_CUT_SHIFT			 0
416
417/* (0x4248) INPUT_VOL_CONTROL */
418#define CS48L32_IN_VD_RAMP_SHIFT			 4
419#define CS48L32_IN_VI_RAMP_SHIFT			 0
420
421/* (0x4308) AUXPDM1_CONTROL1 */
422#define CS48L32_AUXPDM1_FREQ_SHIFT			16
423#define CS48L32_AUXPDM1_SRC_MASK		0x00000f00
424#define CS48L32_AUXPDM1_SRC_SHIFT			 8
425
426/* (0x4688) ADC1L_ANA_CONTROL1 */
427/* (0x468c) ADC1R_ANA_CONTROL1 */
428#define CS48L32_ADC1x_INT_ENA_FRC_MASK		0x00000002
429
430/* (0x6004) ASPn_CONTROL1 */
431#define CS48L32_ASP_RATE_MASK			0x00001f00
432#define CS48L32_ASP_RATE_SHIFT				 8
433#define CS48L32_ASP_BCLK_FREQ_MASK		0x0000003f
434
435/* (0x6008) ASPn_CONTROL2 */
436#define CS48L32_ASP_RX_WIDTH_MASK		0xff000000
437#define CS48L32_ASP_RX_WIDTH_SHIFT			24
438#define CS48L32_ASP_TX_WIDTH_MASK		0x00ff0000
439#define CS48L32_ASP_TX_WIDTH_SHIFT			16
440#define CS48L32_ASP_FMT_MASK			0x00000700
441#define CS48L32_ASP_FMT_SHIFT				 8
442#define CS48L32_ASP_BCLK_INV_MASK		0x00000040
443#define CS48L32_ASP_BCLK_MSTR_MASK		0x00000010
444#define CS48L32_ASP_FSYNC_INV_MASK		0x00000004
445#define CS48L32_ASP_FSYNC_MSTR_MASK		0x00000001
446
447/* (0x6010) ASPn_CONTROL3 */
448#define CS48L32_ASP_DOUT_HIZ_MASK		0x00000003
449
450/* (0x6030) ASPn_DATA_CONTROL1 */
451#define CS48L32_ASP_TX_WL_MASK			0x0000003f
452
453/* (0x6040) ASPn_DATA_CONTROL5 */
454#define CS48L32_ASP_RX_WL_MASK			0x0000003f
455
456/* (0x82xx - 0x90xx)  *_INPUT[1-4] */
457#define CS48L32_MIXER_VOL_MASK			0x00FE0000
458#define CS48L32_MIXER_VOL_SHIFT				17
459#define CS48L32_MIXER_VOL_WIDTH				 7
460#define CS48L32_MIXER_SRC_MASK			0x000001ff
461#define CS48L32_MIXER_SRC_SHIFT				 0
462#define CS48L32_MIXER_SRC_WIDTH				 9
463
464/* (0xa400) ISRC1_CONTROL1 */
465#define CS48L32_ISRC1_FSL_MASK			0xf8000000
466#define CS48L32_ISRC1_FSL_SHIFT				27
467#define CS48L32_ISRC1_FSH_MASK			0x0000f800
468#define CS48L32_ISRC1_FSH_SHIFT				11
469
470/* (0xa404) ISRC1_CONTROL2 */
471#define CS48L32_ISRC1_INT4_EN_SHIFT			11
472#define CS48L32_ISRC1_INT3_EN_SHIFT			10
473#define CS48L32_ISRC1_INT2_EN_SHIFT			 9
474#define CS48L32_ISRC1_INT1_EN_SHIFT			 8
475#define CS48L32_ISRC1_DEC4_EN_SHIFT			 3
476#define CS48L32_ISRC1_DEC3_EN_SHIFT			 2
477#define CS48L32_ISRC1_DEC2_EN_SHIFT			 1
478#define CS48L32_ISRC1_DEC1_EN_SHIFT			 0
479
480/* (0xa800) FX_SAMPLE_RATE */
481#define CS48L32_FX_RATE_MASK			0x0000f800
482#define CS48L32_FX_RATE_SHIFT				11
483
484/* (0xab00) DRC1_CONTROL1 */
485#define CS48L32_DRC1L_EN_SHIFT				 1
486#define CS48L32_DRC1R_EN_SHIFT				 0
487
488/* (0xb400) Comfort_Noise_Generator */
489#define CS48L32_NOISE_GEN_RATE_MASK		0x0000f800
490#define CS48L32_NOISE_GEN_RATE_SHIFT			11
491#define CS48L32_NOISE_GEN_EN_SHIFT			 5
492#define CS48L32_NOISE_GEN_GAIN_SHIFT			 0
493
494/* (0xb800) US_CONTROL */
495#define CS48L32_US1_DET_EN_SHIFT			 8
496
497/* (0xb804) US1_CONTROL */
498#define CS48L32_US1_RATE_MASK			0xf8000000
499#define CS48L32_US1_RATE_SHIFT				27
500#define CS48L32_US1_GAIN_SHIFT				12
501#define CS48L32_US1_SRC_MASK			0x00000f00
502#define CS48L32_US1_SRC_SHIFT				 8
503#define CS48L32_US1_FREQ_MASK			0x00000070
504#define CS48L32_US1_FREQ_SHIFT				 4
505
506/* (0xb808) US1_DET_CONTROL */
507#define CS48L32_US1_DET_DCY_SHIFT			28
508#define CS48L32_US1_DET_HOLD_SHIFT			24
509#define CS48L32_US1_DET_NUM_SHIFT			20
510#define CS48L32_US1_DET_THR_SHIFT			16
511#define CS48L32_US1_DET_LPF_CUT_SHIFT			 5
512#define CS48L32_US1_DET_LPF_SHIFT			 4
513
514/* (0x18004) IRQ1_STATUS */
515#define CS48L32_IRQ1_STS_MASK			0x00000001
516
517/* (0x18014) IRQ1_EINT_2 */
518#define CS48L32_BOOT_DONE_EINT1_MASK		0x00000008
519
520/* (0x18028) IRQ1_EINT_7 */
521#define CS48L32_DSP1_MPU_ERR_EINT1_MASK		0x00200000
522#define CS48L32_DSP1_WDT_EXPIRE_EINT1_MASK	0x00100000
523
524/* (0x18030) IRQ1_EINT_9 */
525#define CS48L32_DSP1_IRQ0_EINT1_MASK		0x00000001
526
527/* (0x180a4) IRQ1_STS_6 */
528#define CS48L32_FLL1_LOCK_STS1_MASK		0x00000001
529
530#endif