tcs.h

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
 4 */
 5
 6#ifndef __SOC_QCOM_TCS_H__
 7#define __SOC_QCOM_TCS_H__
 8
 9#include <linux/bitfield.h>
10#include <linux/bits.h>
11
12#define MAX_RPMH_PAYLOAD	16
13
14/**
15 * rpmh_state: state for the request
16 *
17 * RPMH_SLEEP_STATE:       State of the resource when the processor subsystem
18 *                         is powered down. There is no client using the
19 *                         resource actively.
20 * RPMH_WAKE_ONLY_STATE:   Resume resource state to the value previously
21 *                         requested before the processor was powered down.
22 * RPMH_ACTIVE_ONLY_STATE: Active or AMC mode requests. Resource state
23 *                         is aggregated immediately.
24 */
25enum rpmh_state {
26	RPMH_SLEEP_STATE,
27	RPMH_WAKE_ONLY_STATE,
28	RPMH_ACTIVE_ONLY_STATE,
29};
30
31/**
32 * struct tcs_cmd: an individual request to RPMH.
33 *
34 * @addr: the address of the resource slv_id:18:16 | offset:0:15
35 * @data: the resource state request
36 * @wait: ensure that this command is complete before returning.
37 *        Setting "wait" here only makes sense during rpmh_write_batch() for
38 *        active-only transfers, this is because:
39 *        rpmh_write() - Always waits.
40 *                       (DEFINE_RPMH_MSG_ONSTACK will set .wait_for_compl)
41 *        rpmh_write_async() - Never waits.
42 *                       (There's no request completion callback)
43 */
44struct tcs_cmd {
45	u32 addr;
46	u32 data;
47	u32 wait;
48};
49
50/**
51 * struct tcs_request: A set of tcs_cmds sent together in a TCS
52 *
53 * @state:          state for the request.
54 * @wait_for_compl: wait until we get a response from the h/w accelerator
55 *                  (same as setting cmd->wait for all commands in the request)
56 * @num_cmds:       the number of @cmds in this request
57 * @cmds:           an array of tcs_cmds
58 */
59struct tcs_request {
60	enum rpmh_state state;
61	u32 wait_for_compl;
62	u32 num_cmds;
63	struct tcs_cmd *cmds;
64};
65
66#define BCM_TCS_CMD_COMMIT_MASK		BIT(30)
67#define BCM_TCS_CMD_VALID_MASK		BIT(29)
68#define BCM_TCS_CMD_VOTE_MASK		GENMASK(13, 0)
69#define BCM_TCS_CMD_VOTE_Y_MASK		GENMASK(13, 0)
70#define BCM_TCS_CMD_VOTE_X_MASK		GENMASK(27, 14)
71
72/* Construct a Bus Clock Manager (BCM) specific TCS command */
73#define BCM_TCS_CMD(commit, valid, vote_x, vote_y)		\
74	(u32_encode_bits(commit, BCM_TCS_CMD_COMMIT_MASK) |	\
75	u32_encode_bits(valid, BCM_TCS_CMD_VALID_MASK) |	\
76	u32_encode_bits(vote_x, BCM_TCS_CMD_VOTE_X_MASK) |	\
77	u32_encode_bits(vote_y, BCM_TCS_CMD_VOTE_Y_MASK))
78
79#endif /* __SOC_QCOM_TCS_H__ */