ehci_def.h

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * Copyright (c) 2001-2002 by David Brownell
  4 */
  5
  6#ifndef __LINUX_USB_EHCI_DEF_H
  7#define __LINUX_USB_EHCI_DEF_H
  8
  9#include <linux/usb/ehci-dbgp.h>
 10
 11/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
 12
 13/* Section 2.2 Host Controller Capability Registers */
 14struct ehci_caps {
 15	/* these fields are specified as 8 and 16 bit registers,
 16	 * but some hosts can't perform 8 or 16 bit PCI accesses.
 17	 * some hosts treat caplength and hciversion as parts of a 32-bit
 18	 * register, others treat them as two separate registers, this
 19	 * affects the memory map for big endian controllers.
 20	 */
 21	u32		hc_capbase;
 22#define HC_LENGTH(ehci, p)	(0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
 23				(ehci_big_endian_capbase(ehci) ? 24 : 0)))
 24#define HC_VERSION(ehci, p)	(0xffff&((p) >> /* bits 31:16 / offset 02h */ \
 25				(ehci_big_endian_capbase(ehci) ? 0 : 16)))
 26	u32		hcs_params;     /* HCSPARAMS - offset 0x4 */
 27#define HCS_DEBUG_PORT(p)	(((p)>>20)&0xf)	/* bits 23:20, debug port? */
 28#define HCS_INDICATOR(p)	((p)&(1 << 16))	/* true: has port indicators */
 29#define HCS_N_CC(p)		(((p)>>12)&0xf)	/* bits 15:12, #companion HCs */
 30#define HCS_N_PCC(p)		(((p)>>8)&0xf)	/* bits 11:8, ports per CC */
 31#define HCS_PORTROUTED(p)	((p)&(1 << 7))	/* true: port routing */
 32#define HCS_PPC(p)		((p)&(1 << 4))	/* true: port power control */
 33#define HCS_N_PORTS(p)		(((p)>>0)&0xf)	/* bits 3:0, ports on HC */
 34#define HCS_N_PORTS_MAX		15		/* N_PORTS valid 0x1-0xF */
 35
 36	u32		hcc_params;      /* HCCPARAMS - offset 0x8 */
 37/* EHCI 1.1 addendum */
 38#define HCC_32FRAME_PERIODIC_LIST(p)	((p)&(1 << 19))
 39#define HCC_PER_PORT_CHANGE_EVENT(p)	((p)&(1 << 18))
 40#define HCC_LPM(p)			((p)&(1 << 17))
 41#define HCC_HW_PREFETCH(p)		((p)&(1 << 16))
 42
 43#define HCC_EXT_CAPS(p)		(((p)>>8)&0xff)	/* for pci extended caps */
 44#define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
 45#define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
 46#define HCC_CANPARK(p)		((p)&(1 << 2))  /* true: can park on async qh */
 47#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
 48#define HCC_64BIT_ADDR(p)       ((p)&(1))       /* true: can use 64-bit addr */
 49	u8		portroute[8];	 /* nibbles for routing - offset 0xC */
 50};
 51
 52
 53/* Section 2.3 Host Controller Operational Registers */
 54struct ehci_regs {
 55
 56	/* USBCMD: offset 0x00 */
 57	u32		command;
 58
 59/* EHCI 1.1 addendum */
 60#define CMD_HIRD	(0xf<<24)	/* host initiated resume duration */
 61#define CMD_PPCEE	(1<<15)		/* per port change event enable */
 62#define CMD_FSP		(1<<14)		/* fully synchronized prefetch */
 63#define CMD_ASPE	(1<<13)		/* async schedule prefetch enable */
 64#define CMD_PSPE	(1<<12)		/* periodic schedule prefetch enable */
 65/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
 66#define CMD_PARK	(1<<11)		/* enable "park" on async qh */
 67#define CMD_PARK_CNT(c)	(((c)>>8)&3)	/* how many transfers to park for */
 68#define CMD_LRESET	(1<<7)		/* partial reset (no ports, etc) */
 69#define CMD_IAAD	(1<<6)		/* "doorbell" interrupt async advance */
 70#define CMD_ASE		(1<<5)		/* async schedule enable */
 71#define CMD_PSE		(1<<4)		/* periodic schedule enable */
 72/* 3:2 is periodic frame list size */
 73#define CMD_RESET	(1<<1)		/* reset HC not bus */
 74#define CMD_RUN		(1<<0)		/* start/stop HC */
 75
 76	/* USBSTS: offset 0x04 */
 77	u32		status;
 78#define STS_PPCE_MASK	(0xff<<16)	/* Per-Port change event 1-16 */
 79#define STS_ASS		(1<<15)		/* Async Schedule Status */
 80#define STS_PSS		(1<<14)		/* Periodic Schedule Status */
 81#define STS_RECL	(1<<13)		/* Reclamation */
 82#define STS_HALT	(1<<12)		/* Not running (any reason) */
 83/* some bits reserved */
 84	/* these STS_* flags are also intr_enable bits (USBINTR) */
 85#define STS_IAA		(1<<5)		/* Interrupted on async advance */
 86#define STS_FATAL	(1<<4)		/* such as some PCI access errors */
 87#define STS_FLR		(1<<3)		/* frame list rolled over */
 88#define STS_PCD		(1<<2)		/* port change detect */
 89#define STS_ERR		(1<<1)		/* "error" completion (overflow, ...) */
 90#define STS_INT		(1<<0)		/* "normal" completion (short, ...) */
 91
 92	/* USBINTR: offset 0x08 */
 93	u32		intr_enable;
 94
 95	/* FRINDEX: offset 0x0C */
 96	u32		frame_index;	/* current microframe number */
 97	/* CTRLDSSEGMENT: offset 0x10 */
 98	u32		segment;	/* address bits 63:32 if needed */
 99	/* PERIODICLISTBASE: offset 0x14 */
100	u32		frame_list;	/* points to periodic list */
101	/* ASYNCLISTADDR: offset 0x18 */
102	u32		async_next;	/* address of next async queue head */
103
104	u32		reserved1[2];
105
106	/* TXFILLTUNING: offset 0x24 */
107	u32		txfill_tuning;	/* TX FIFO Tuning register */
108#define TXFIFO_DEFAULT	(8<<16)		/* FIFO burst threshold 8 */
109
110	u32		reserved2[6];
111
112	/* CONFIGFLAG: offset 0x40 */
113	u32		configured_flag;
114#define FLAG_CF		(1<<0)		/* true: we'll support "high speed" */
115
116	union {
117		/* PORTSC: offset 0x44 */
118		u32	port_status[HCS_N_PORTS_MAX];	/* up to N_PORTS */
119/* EHCI 1.1 addendum */
120#define PORTSC_SUSPEND_STS_ACK 0
121#define PORTSC_SUSPEND_STS_NYET 1
122#define PORTSC_SUSPEND_STS_STALL 2
123#define PORTSC_SUSPEND_STS_ERR 3
124
125#define PORT_DEV_ADDR	(0x7f<<25)		/* device address */
126#define PORT_SSTS	(0x3<<23)		/* suspend status */
127/* 31:23 reserved */
128#define PORT_WKOC_E	(1<<22)		/* wake on overcurrent (enable) */
129#define PORT_WKDISC_E	(1<<21)		/* wake on disconnect (enable) */
130#define PORT_WKCONN_E	(1<<20)		/* wake on connect (enable) */
131/* 19:16 for port testing */
132#define PORT_TEST(x)	(((x)&0xf)<<16)	/* Port Test Control */
133#define PORT_TEST_PKT	PORT_TEST(0x4)	/* Port Test Control - packet test */
134#define PORT_TEST_FORCE	PORT_TEST(0x5)	/* Port Test Control - force enable */
135#define PORT_LED_OFF	(0<<14)
136#define PORT_LED_AMBER	(1<<14)
137#define PORT_LED_GREEN	(2<<14)
138#define PORT_LED_MASK	(3<<14)
139#define PORT_OWNER	(1<<13)		/* true: companion hc owns this port */
140#define PORT_POWER	(1<<12)		/* true: has power (see PPC) */
141#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10))	/* USB 1.1 device */
142#define PORT_LS_MASK	(3<<10)		/* Link status (SE0, K or J */
143/* 9 reserved */
144#define PORT_LPM	(1<<9)		/* LPM transaction */
145#define PORT_RESET	(1<<8)		/* reset port */
146#define PORT_SUSPEND	(1<<7)		/* suspend port */
147#define PORT_RESUME	(1<<6)		/* resume it */
148#define PORT_OCC	(1<<5)		/* over current change */
149#define PORT_OC		(1<<4)		/* over current active */
150#define PORT_PEC	(1<<3)		/* port enable change */
151#define PORT_PE		(1<<2)		/* port enable */
152#define PORT_CSC	(1<<1)		/* connect status change */
153#define PORT_CONNECT	(1<<0)		/* device connected */
154#define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_OCC)
155		struct {
156			u32	reserved3[9];
157			/* USBMODE: offset 0x68 */
158			u32	usbmode;	/* USB Device mode */
159		};
160#define USBMODE_SDIS	(1<<3)		/* Stream disable */
161#define USBMODE_BE	(1<<2)		/* BE/LE endianness select */
162#define USBMODE_CM_HC	(3<<0)		/* host controller mode */
163#define USBMODE_CM_IDLE	(0<<0)		/* idle state */
164	};
165
166/* Moorestown has some non-standard registers, partially due to the fact that
167 * its EHCI controller has both TT and LPM support. HOSTPCx are extensions to
168 * PORTSCx
169 */
170	union {
171		struct {
172			u32	reserved4;
173			/* HOSTPC: offset 0x84 */
174			u32	hostpc[HCS_N_PORTS_MAX];
175#define HOSTPC_PHCD	(1<<22)		/* Phy clock disable */
176#define HOSTPC_PSPD	(3<<25)		/* Port speed detection */
177		};
178
179		/* Broadcom-proprietary USB_EHCI_INSNREG00 @ 0x80 */
180		u32	brcm_insnreg[4];
181	};
182
183	u32		reserved5[2];
184
185	/* USBMODE_EX: offset 0xc8 */
186	u32		usbmode_ex;	/* USB Device mode extension */
187#define USBMODE_EX_VBPS	(1<<5)		/* VBus Power Select On */
188#define USBMODE_EX_HC	(3<<0)		/* host controller mode */
189};
190
191#endif /* __LINUX_USB_EHCI_DEF_H */