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spi.h
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linux-6.19.14/include/linux/spi/spi.h
1/* SPDX-License-Identifier: GPL-2.0-or-later 2 * 3 * Copyright (C) 2005 David Brownell 4 */ 5 6#ifndef __LINUX_SPI_H 7#define __LINUX_SPI_H 8 9#include <linux/acpi.h> 10#include <linux/bits.h> 11#include <linux/completion.h> 12#include <linux/device.h> 13#include <linux/gpio/consumer.h> 14#include <linux/kthread.h> 15#include <linux/mod_devicetable.h> 16#include <linux/overflow.h> 17#include <linux/scatterlist.h> 18#include <linux/slab.h> 19#include <linux/u64_stats_sync.h> 20 21#include <uapi/linux/spi/spi.h> 22 23/* Max no. of CS supported per spi device */ 24#define SPI_DEVICE_CS_CNT_MAX 4 25 26struct dma_chan; 27struct software_node; 28struct ptp_system_timestamp; 29struct spi_controller; 30struct spi_transfer; 31struct spi_controller_mem_ops; 32struct spi_controller_mem_caps; 33struct spi_message; 34struct spi_offload; 35struct spi_offload_config; 36 37/* 38 * INTERFACES between SPI controller-side drivers and SPI target protocol handlers, 39 * and SPI infrastructure. 40 */ 41extern const struct bus_type spi_bus_type; 42 43/** 44 * struct spi_statistics - statistics for spi transfers 45 * @syncp: seqcount to protect members in this struct for per-cpu update 46 * on 32-bit systems 47 * 48 * @messages: number of spi-messages handled 49 * @transfers: number of spi_transfers handled 50 * @errors: number of errors during spi_transfer 51 * @timedout: number of timeouts during spi_transfer 52 * 53 * @spi_sync: number of times spi_sync is used 54 * @spi_sync_immediate: 55 * number of times spi_sync is executed immediately 56 * in calling context without queuing and scheduling 57 * @spi_async: number of times spi_async is used 58 * 59 * @bytes: number of bytes transferred to/from device 60 * @bytes_tx: number of bytes sent to device 61 * @bytes_rx: number of bytes received from device 62 * 63 * @transfer_bytes_histo: 64 * transfer bytes histogram 65 * 66 * @transfers_split_maxsize: 67 * number of transfers that have been split because of 68 * maxsize limit 69 */ 70struct spi_statistics { 71 struct u64_stats_sync syncp; 72 73 u64_stats_t messages; 74 u64_stats_t transfers; 75 u64_stats_t errors; 76 u64_stats_t timedout; 77 78 u64_stats_t spi_sync; 79 u64_stats_t spi_sync_immediate; 80 u64_stats_t spi_async; 81 82 u64_stats_t bytes; 83 u64_stats_t bytes_rx; 84 u64_stats_t bytes_tx; 85 86#define SPI_STATISTICS_HISTO_SIZE 17 87 u64_stats_t transfer_bytes_histo[SPI_STATISTICS_HISTO_SIZE]; 88 89 u64_stats_t transfers_split_maxsize; 90}; 91 92#define SPI_STATISTICS_ADD_TO_FIELD(pcpu_stats, field, count) \ 93 do { \ 94 struct spi_statistics *__lstats; \ 95 get_cpu(); \ 96 __lstats = this_cpu_ptr(pcpu_stats); \ 97 u64_stats_update_begin(&__lstats->syncp); \ 98 u64_stats_add(&__lstats->field, count); \ 99 u64_stats_update_end(&__lstats->syncp); \ 100 put_cpu(); \ 101 } while (0) 102 103#define SPI_STATISTICS_INCREMENT_FIELD(pcpu_stats, field) \ 104 do { \ 105 struct spi_statistics *__lstats; \ 106 get_cpu(); \ 107 __lstats = this_cpu_ptr(pcpu_stats); \ 108 u64_stats_update_begin(&__lstats->syncp); \ 109 u64_stats_inc(&__lstats->field); \ 110 u64_stats_update_end(&__lstats->syncp); \ 111 put_cpu(); \ 112 } while (0) 113 114/** 115 * struct spi_delay - SPI delay information 116 * @value: Value for the delay 117 * @unit: Unit for the delay 118 */ 119struct spi_delay { 120#define SPI_DELAY_UNIT_USECS 0 121#define SPI_DELAY_UNIT_NSECS 1 122#define SPI_DELAY_UNIT_SCK 2 123 u16 value; 124 u8 unit; 125}; 126 127extern int spi_delay_to_ns(struct spi_delay *_delay, struct spi_transfer *xfer); 128extern int spi_delay_exec(struct spi_delay *_delay, struct spi_transfer *xfer); 129extern void spi_transfer_cs_change_delay_exec(struct spi_message *msg, 130 struct spi_transfer *xfer); 131 132/** 133 * struct spi_device - Controller side proxy for an SPI target device 134 * @dev: Driver model representation of the device. 135 * @controller: SPI controller used with the device. 136 * @max_speed_hz: Maximum clock rate to be used with this chip 137 * (on this board); may be changed by the device's driver. 138 * The spi_transfer.speed_hz can override this for each transfer. 139 * @bits_per_word: Data transfers involve one or more words; word sizes 140 * like eight or 12 bits are common. In-memory wordsizes are 141 * powers of two bytes (e.g. 20 bit samples use 32 bits). 142 * This may be changed by the device's driver, or left at the 143 * default (0) indicating protocol words are eight bit bytes. 144 * The spi_transfer.bits_per_word can override this for each transfer. 145 * @rt: Make the pump thread real time priority. 146 * @mode: The spi mode defines how data is clocked out and in. 147 * This may be changed by the device's driver. 148 * The "active low" default for chipselect mode can be overridden 149 * (by specifying SPI_CS_HIGH) as can the "MSB first" default for 150 * each word in a transfer (by specifying SPI_LSB_FIRST). 151 * @irq: Negative, or the number passed to request_irq() to receive 152 * interrupts from this device. 153 * @controller_state: Controller's runtime state 154 * @controller_data: Board-specific definitions for controller, such as 155 * FIFO initialization parameters; from board_info.controller_data 156 * @modalias: Name of the driver to use with this device, or an alias 157 * for that name. This appears in the sysfs "modalias" attribute 158 * for driver coldplugging, and in uevents used for hotplugging 159 * @pcpu_statistics: statistics for the spi_device 160 * @word_delay: delay to be inserted between consecutive 161 * words of a transfer 162 * @cs_setup: delay to be introduced by the controller after CS is asserted 163 * @cs_hold: delay to be introduced by the controller before CS is deasserted 164 * @cs_inactive: delay to be introduced by the controller after CS is 165 * deasserted. If @cs_change_delay is used from @spi_transfer, then the 166 * two delays will be added up. 167 * @chip_select: Array of physical chipselect, spi->chipselect[i] gives 168 * the corresponding physical CS for logical CS i. 169 * @num_chipselect: Number of physical chipselects used. 170 * @cs_index_mask: Bit mask of the active chipselect(s) in the chipselect array 171 * @cs_gpiod: Array of GPIO descriptors of the corresponding chipselect lines 172 * (optional, NULL when not using a GPIO line) 173 * 174 * A @spi_device is used to interchange data between an SPI target device 175 * (usually a discrete chip) and CPU memory. 176 * 177 * In @dev, the platform_data is used to hold information about this 178 * device that's meaningful to the device's protocol driver, but not 179 * to its controller. One example might be an identifier for a chip 180 * variant with slightly different functionality; another might be 181 * information about how this particular board wires the chip's pins. 182 */ 183struct spi_device { 184 struct device dev; 185 struct spi_controller *controller; 186 u32 max_speed_hz; 187 u8 bits_per_word; 188 bool rt; 189#define SPI_NO_TX BIT(31) /* No transmit wire */ 190#define SPI_NO_RX BIT(30) /* No receive wire */ 191 /* 192 * TPM specification defines flow control over SPI. Client device 193 * can insert a wait state on MISO when address is transmitted by 194 * controller on MOSI. Detecting the wait state in software is only 195 * possible for full duplex controllers. For controllers that support 196 * only half-duplex, the wait state detection needs to be implemented 197 * in hardware. TPM devices would set this flag when hardware flow 198 * control is expected from SPI controller. 199 */ 200#define SPI_TPM_HW_FLOW BIT(29) /* TPM HW flow control */ 201 /* 202 * All bits defined above should be covered by SPI_MODE_KERNEL_MASK. 203 * The SPI_MODE_KERNEL_MASK has the SPI_MODE_USER_MASK counterpart, 204 * which is defined in 'include/uapi/linux/spi/spi.h'. 205 * The bits defined here are from bit 31 downwards, while in 206 * SPI_MODE_USER_MASK are from 0 upwards. 207 * These bits must not overlap. A static assert check should make sure of that. 208 * If adding extra bits, make sure to decrease the bit index below as well. 209 */ 210#define SPI_MODE_KERNEL_MASK (~(BIT(29) - 1)) 211 u32 mode; 212 int irq; 213 void *controller_state; 214 void *controller_data; 215 char modalias[SPI_NAME_SIZE]; 216 217 /* The statistics */ 218 struct spi_statistics __percpu *pcpu_statistics; 219 220 struct spi_delay word_delay; /* Inter-word delay */ 221 222 /* CS delays */ 223 struct spi_delay cs_setup; 224 struct spi_delay cs_hold; 225 struct spi_delay cs_inactive; 226 227 u8 chip_select[SPI_DEVICE_CS_CNT_MAX]; 228 u8 num_chipselect; 229 230 /* 231 * Bit mask of the chipselect(s) that the driver need to use from 232 * the chipselect array. When the controller is capable to handle 233 * multiple chip selects & memories are connected in parallel 234 * then more than one bit need to be set in cs_index_mask. 235 */ 236 u32 cs_index_mask : SPI_DEVICE_CS_CNT_MAX; 237 238 struct gpio_desc *cs_gpiod[SPI_DEVICE_CS_CNT_MAX]; /* Chip select gpio desc */ 239 240 /* 241 * Likely need more hooks for more protocol options affecting how 242 * the controller talks to each chip, like: 243 * - memory packing (12 bit samples into low bits, others zeroed) 244 * - priority 245 * - chipselect delays 246 * - ... 247 */ 248}; 249 250/* Make sure that SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK don't overlap */ 251static_assert((SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK) == 0, 252 "SPI_MODE_USER_MASK & SPI_MODE_KERNEL_MASK must not overlap"); 253 254#define to_spi_device(__dev) container_of_const(__dev, struct spi_device, dev) 255 256/* Most drivers won't need to care about device refcounting */ 257static inline struct spi_device *spi_dev_get(struct spi_device *spi) 258{ 259 return (spi && get_device(&spi->dev)) ? spi : NULL; 260} 261 262static inline void spi_dev_put(struct spi_device *spi) 263{ 264 if (spi) 265 put_device(&spi->dev); 266} 267 268/* ctldata is for the bus_controller driver's runtime state */ 269static inline void *spi_get_ctldata(const struct spi_device *spi) 270{ 271 return spi->controller_state; 272} 273 274static inline void spi_set_ctldata(struct spi_device *spi, void *state) 275{ 276 spi->controller_state = state; 277} 278 279/* Device driver data */ 280 281static inline void spi_set_drvdata(struct spi_device *spi, void *data) 282{ 283 dev_set_drvdata(&spi->dev, data); 284} 285 286static inline void *spi_get_drvdata(const struct spi_device *spi) 287{ 288 return dev_get_drvdata(&spi->dev); 289} 290 291static inline u8 spi_get_chipselect(const struct spi_device *spi, u8 idx) 292{ 293 return spi->chip_select[idx]; 294} 295 296static inline void spi_set_chipselect(struct spi_device *spi, u8 idx, u8 chipselect) 297{ 298 spi->chip_select[idx] = chipselect; 299} 300 301static inline struct gpio_desc *spi_get_csgpiod(const struct spi_device *spi, u8 idx) 302{ 303 return spi->cs_gpiod[idx]; 304} 305 306static inline void spi_set_csgpiod(struct spi_device *spi, u8 idx, struct gpio_desc *csgpiod) 307{ 308 spi->cs_gpiod[idx] = csgpiod; 309} 310 311static inline bool spi_is_csgpiod(struct spi_device *spi) 312{ 313 u8 idx; 314 315 for (idx = 0; idx < spi->num_chipselect; idx++) { 316 if (spi_get_csgpiod(spi, idx)) 317 return true; 318 } 319 return false; 320} 321 322/** 323 * struct spi_driver - Host side "protocol" driver 324 * @id_table: List of SPI devices supported by this driver 325 * @probe: Binds this driver to the SPI device. Drivers can verify 326 * that the device is actually present, and may need to configure 327 * characteristics (such as bits_per_word) which weren't needed for 328 * the initial configuration done during system setup. 329 * @remove: Unbinds this driver from the SPI device 330 * @shutdown: Standard shutdown callback used during system state 331 * transitions such as powerdown/halt and kexec 332 * @driver: SPI device drivers should initialize the name and owner 333 * field of this structure. 334 * 335 * This represents the kind of device driver that uses SPI messages to 336 * interact with the hardware at the other end of a SPI link. It's called 337 * a "protocol" driver because it works through messages rather than talking 338 * directly to SPI hardware (which is what the underlying SPI controller 339 * driver does to pass those messages). These protocols are defined in the 340 * specification for the device(s) supported by the driver. 341 * 342 * As a rule, those device protocols represent the lowest level interface 343 * supported by a driver, and it will support upper level interfaces too. 344 * Examples of such upper levels include frameworks like MTD, networking, 345 * MMC, RTC, filesystem character device nodes, and hardware monitoring. 346 */ 347struct spi_driver { 348 const struct spi_device_id *id_table; 349 int (*probe)(struct spi_device *spi); 350 void (*remove)(struct spi_device *spi); 351 void (*shutdown)(struct spi_device *spi); 352 struct device_driver driver; 353}; 354 355#define to_spi_driver(__drv) \ 356 ( __drv ? container_of_const(__drv, struct spi_driver, driver) : NULL ) 357 358extern int __spi_register_driver(struct module *owner, struct spi_driver *sdrv); 359 360/** 361 * spi_unregister_driver - reverse effect of spi_register_driver 362 * @sdrv: the driver to unregister 363 * Context: can sleep 364 */ 365static inline void spi_unregister_driver(struct spi_driver *sdrv) 366{ 367 if (sdrv) 368 driver_unregister(&sdrv->driver); 369} 370 371extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi, u8 chip_select); 372 373/* Use a define to avoid include chaining to get THIS_MODULE */ 374#define spi_register_driver(driver) \ 375 __spi_register_driver(THIS_MODULE, driver) 376 377/** 378 * module_spi_driver() - Helper macro for registering a SPI driver 379 * @__spi_driver: spi_driver struct 380 * 381 * Helper macro for SPI drivers which do not do anything special in module 382 * init/exit. This eliminates a lot of boilerplate. Each module may only 383 * use this macro once, and calling it replaces module_init() and module_exit() 384 */ 385#define module_spi_driver(__spi_driver) \ 386 module_driver(__spi_driver, spi_register_driver, \ 387 spi_unregister_driver) 388 389/** 390 * struct spi_controller - interface to SPI host or target controller 391 * @dev: device interface to this driver 392 * @list: link with the global spi_controller list 393 * @bus_num: board-specific (and often SOC-specific) identifier for a 394 * given SPI controller. 395 * @num_chipselect: chipselects are used to distinguish individual 396 * SPI targets, and are numbered from zero to num_chipselects. 397 * each target has a chipselect signal, but it's common that not 398 * every chipselect is connected to a target. 399 * @dma_alignment: SPI controller constraint on DMA buffers alignment. 400 * @mode_bits: flags understood by this controller driver 401 * @buswidth_override_bits: flags to override for this controller driver 402 * @bits_per_word_mask: A mask indicating which values of bits_per_word are 403 * supported by the driver. Bit n indicates that a bits_per_word n+1 is 404 * supported. If set, the SPI core will reject any transfer with an 405 * unsupported bits_per_word. If not set, this value is simply ignored, 406 * and it's up to the individual driver to perform any validation. 407 * @min_speed_hz: Lowest supported transfer speed 408 * @max_speed_hz: Highest supported transfer speed 409 * @flags: other constraints relevant to this driver 410 * @slave: indicates that this is an SPI slave controller 411 * @target: indicates that this is an SPI target controller 412 * @devm_allocated: whether the allocation of this struct is devres-managed 413 * @max_transfer_size: function that returns the max transfer size for 414 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. 415 * @max_message_size: function that returns the max message size for 416 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. 417 * @io_mutex: mutex for physical bus access 418 * @add_lock: mutex to avoid adding devices to the same chipselect 419 * @bus_lock_spinlock: spinlock for SPI bus locking 420 * @bus_lock_mutex: mutex for exclusion of multiple callers 421 * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use 422 * @setup: updates the device mode and clocking records used by a 423 * device's SPI controller; protocol code may call this. This 424 * must fail if an unrecognized or unsupported mode is requested. 425 * It's always safe to call this unless transfers are pending on 426 * the device whose settings are being modified. 427 * @set_cs_timing: optional hook for SPI devices to request SPI 428 * controller for configuring specific CS setup time, hold time and inactive 429 * delay in terms of clock counts 430 * @transfer: adds a message to the controller's transfer queue. 431 * @cleanup: frees controller-specific state 432 * @can_dma: determine whether this controller supports DMA 433 * @dma_map_dev: device which can be used for DMA mapping 434 * @cur_rx_dma_dev: device which is currently used for RX DMA mapping 435 * @cur_tx_dma_dev: device which is currently used for TX DMA mapping 436 * @queued: whether this controller is providing an internal message queue 437 * @kworker: pointer to thread struct for message pump 438 * @pump_messages: work struct for scheduling work to the message pump 439 * @queue_lock: spinlock to synchronise access to message queue 440 * @queue: message queue 441 * @cur_msg: the currently in-flight message 442 * @cur_msg_completion: a completion for the current in-flight message 443 * @cur_msg_incomplete: Flag used internally to opportunistically skip 444 * the @cur_msg_completion. This flag is used to check if the driver has 445 * already called spi_finalize_current_message(). 446 * @cur_msg_need_completion: Flag used internally to opportunistically skip 447 * the @cur_msg_completion. This flag is used to signal the context that 448 * is running spi_finalize_current_message() that it needs to complete() 449 * @fallback: fallback to PIO if DMA transfer return failure with 450 * SPI_TRANS_FAIL_NO_START. 451 * @last_cs_mode_high: was (mode & SPI_CS_HIGH) true on the last call to set_cs. 452 * @last_cs: the last chip_select that is recorded by set_cs, -1 on non chip 453 * selected 454 * @last_cs_index_mask: bit mask the last chip selects that were used 455 * @xfer_completion: used by core transfer_one_message() 456 * @busy: message pump is busy 457 * @running: message pump is running 458 * @rt: whether this queue is set to run as a realtime task 459 * @auto_runtime_pm: the core should ensure a runtime PM reference is held 460 * while the hardware is prepared, using the parent 461 * device for the spidev 462 * @max_dma_len: Maximum length of a DMA transfer for the device. 463 * @prepare_transfer_hardware: a message will soon arrive from the queue 464 * so the subsystem requests the driver to prepare the transfer hardware 465 * by issuing this call 466 * @transfer_one_message: the subsystem calls the driver to transfer a single 467 * message while queuing transfers that arrive in the meantime. When the 468 * driver is finished with this message, it must call 469 * spi_finalize_current_message() so the subsystem can issue the next 470 * message 471 * @unprepare_transfer_hardware: there are currently no more messages on the 472 * queue so the subsystem notifies the driver that it may relax the 473 * hardware by issuing this call 474 * 475 * @set_cs: set the logic level of the chip select line. May be called 476 * from interrupt context. 477 * @optimize_message: optimize the message for reuse 478 * @unoptimize_message: release resources allocated by optimize_message 479 * @prepare_message: set up the controller to transfer a single message, 480 * for example doing DMA mapping. Called from threaded 481 * context. 482 * @transfer_one: transfer a single spi_transfer. 483 * 484 * - return 0 if the transfer is finished, 485 * - return 1 if the transfer is still in progress. When 486 * the driver is finished with this transfer it must 487 * call spi_finalize_current_transfer() so the subsystem 488 * can issue the next transfer. If the transfer fails, the 489 * driver must set the flag SPI_TRANS_FAIL_IO to 490 * spi_transfer->error first, before calling 491 * spi_finalize_current_transfer(). 492 * Note: transfer_one and transfer_one_message are mutually 493 * exclusive; when both are set, the generic subsystem does 494 * not call your transfer_one callback. 495 * @handle_err: the subsystem calls the driver to handle an error that occurs 496 * in the generic implementation of transfer_one_message(). 497 * @mem_ops: optimized/dedicated operations for interactions with SPI memory. 498 * This field is optional and should only be implemented if the 499 * controller has native support for memory like operations. 500 * @get_offload: callback for controllers with offload support to get matching 501 * offload instance. Implementations should return -ENODEV if no match is 502 * found. 503 * @put_offload: release the offload instance acquired by @get_offload. 504 * @mem_caps: controller capabilities for the handling of memory operations. 505 * @dtr_caps: true if controller has dtr(single/dual transfer rate) capability. 506 * QSPI based controller should fill this based on controller's capability. 507 * @unprepare_message: undo any work done by prepare_message(). 508 * @target_abort: abort the ongoing transfer request on an SPI target controller 509 * @cs_gpiods: Array of GPIO descriptors to use as chip select lines; one per CS 510 * number. Any individual value may be NULL for CS lines that 511 * are not GPIOs (driven by the SPI controller itself). 512 * @use_gpio_descriptors: Turns on the code in the SPI core to parse and grab 513 * GPIO descriptors. This will fill in @cs_gpiods and SPI devices will have 514 * the cs_gpiod assigned if a GPIO line is found for the chipselect. 515 * @unused_native_cs: When cs_gpiods is used, spi_register_controller() will 516 * fill in this field with the first unused native CS, to be used by SPI 517 * controller drivers that need to drive a native CS when using GPIO CS. 518 * @max_native_cs: When cs_gpiods is used, and this field is filled in, 519 * spi_register_controller() will validate all native CS (including the 520 * unused native CS) against this value. 521 * @pcpu_statistics: statistics for the spi_controller 522 * @dma_tx: DMA transmit channel 523 * @dma_rx: DMA receive channel 524 * @dummy_rx: dummy receive buffer for full-duplex devices 525 * @dummy_tx: dummy transmit buffer for full-duplex devices 526 * @fw_translate_cs: If the boot firmware uses different numbering scheme 527 * what Linux expects, this optional hook can be used to translate 528 * between the two. 529 * @ptp_sts_supported: If the driver sets this to true, it must provide a 530 * time snapshot in @spi_transfer->ptp_sts as close as possible to the 531 * moment in time when @spi_transfer->ptp_sts_word_pre and 532 * @spi_transfer->ptp_sts_word_post were transmitted. 533 * If the driver does not set this, the SPI core takes the snapshot as 534 * close to the driver hand-over as possible. 535 * @irq_flags: Interrupt enable state during PTP system timestamping 536 * @queue_empty: signal green light for opportunistically skipping the queue 537 * for spi_sync transfers. 538 * @must_async: disable all fast paths in the core 539 * @defer_optimize_message: set to true if controller cannot pre-optimize messages 540 * and needs to defer the optimization step until the message is actually 541 * being transferred 542 * 543 * Each SPI controller can communicate with one or more @spi_device 544 * children. These make a small bus, sharing MOSI, MISO and SCK signals 545 * but not chip select signals. Each device may be configured to use a 546 * different clock rate, since those shared signals are ignored unless 547 * the chip is selected. 548 * 549 * The driver for an SPI controller manages access to those devices through 550 * a queue of spi_message transactions, copying data between CPU memory and 551 * an SPI target device. For each such message it queues, it calls the 552 * message's completion function when the transaction completes. 553 */ 554struct spi_controller { 555 struct device dev; 556 557 struct list_head list; 558 559 /* 560 * Other than negative (== assign one dynamically), bus_num is fully 561 * board-specific. Usually that simplifies to being SoC-specific. 562 * example: one SoC has three SPI controllers, numbered 0..2, 563 * and one board's schematics might show it using SPI-2. Software 564 * would normally use bus_num=2 for that controller. 565 */ 566 s16 bus_num; 567 568 /* 569 * Chipselects will be integral to many controllers; some others 570 * might use board-specific GPIOs. 571 */ 572 u16 num_chipselect; 573 574 /* Some SPI controllers pose alignment requirements on DMAable 575 * buffers; let protocol drivers know about these requirements. 576 */ 577 u16 dma_alignment; 578 579 /* spi_device.mode flags understood by this controller driver */ 580 u32 mode_bits; 581 582 /* spi_device.mode flags override flags for this controller */ 583 u32 buswidth_override_bits; 584 585 /* Bitmask of supported bits_per_word for transfers */ 586 u32 bits_per_word_mask; 587#define SPI_BPW_MASK(bits) BIT((bits) - 1) 588#define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1) 589 590 /* Limits on transfer speed */ 591 u32 min_speed_hz; 592 u32 max_speed_hz; 593 594 /* Other constraints relevant to this driver */ 595 u16 flags; 596#define SPI_CONTROLLER_HALF_DUPLEX BIT(0) /* Can't do full duplex */ 597#define SPI_CONTROLLER_NO_RX BIT(1) /* Can't do buffer read */ 598#define SPI_CONTROLLER_NO_TX BIT(2) /* Can't do buffer write */ 599#define SPI_CONTROLLER_MUST_RX BIT(3) /* Requires rx */ 600#define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx */ 601#define SPI_CONTROLLER_GPIO_SS BIT(5) /* GPIO CS must select target device */ 602#define SPI_CONTROLLER_SUSPENDED BIT(6) /* Currently suspended */ 603 /* 604 * The spi-controller has multi chip select capability and can 605 * assert/de-assert more than one chip select at once. 606 */ 607#define SPI_CONTROLLER_MULTI_CS BIT(7) 608 609 /* Flag indicating if the allocation of this struct is devres-managed */ 610 bool devm_allocated; 611 612 union { 613 /* Flag indicating this is an SPI slave controller */ 614 bool slave; 615 /* Flag indicating this is an SPI target controller */ 616 bool target; 617 }; 618 619 /* 620 * On some hardware transfer / message size may be constrained 621 * the limit may depend on device transfer settings. 622 */ 623 size_t (*max_transfer_size)(struct spi_device *spi); 624 size_t (*max_message_size)(struct spi_device *spi); 625 626 /* I/O mutex */ 627 struct mutex io_mutex; 628 629 /* Used to avoid adding the same CS twice */ 630 struct mutex add_lock; 631 632 /* Lock and mutex for SPI bus locking */ 633 spinlock_t bus_lock_spinlock; 634 struct mutex bus_lock_mutex; 635 636 /* Flag indicating that the SPI bus is locked for exclusive use */ 637 bool bus_lock_flag; 638 639 /* 640 * Setup mode and clock, etc (SPI driver may call many times). 641 * 642 * IMPORTANT: this may be called when transfers to another 643 * device are active. DO NOT UPDATE SHARED REGISTERS in ways 644 * which could break those transfers. 645 */ 646 int (*setup)(struct spi_device *spi); 647 648 /* 649 * set_cs_timing() method is for SPI controllers that supports 650 * configuring CS timing. 651 * 652 * This hook allows SPI client drivers to request SPI controllers 653 * to configure specific CS timing through spi_set_cs_timing() after 654 * spi_setup(). 655 */ 656 int (*set_cs_timing)(struct spi_device *spi); 657 658 /* 659 * Bidirectional bulk transfers 660 * 661 * + The transfer() method may not sleep; its main role is 662 * just to add the message to the queue. 663 * + For now there's no remove-from-queue operation, or 664 * any other request management 665 * + To a given spi_device, message queueing is pure FIFO 666 * 667 * + The controller's main job is to process its message queue, 668 * selecting a chip (for controllers), then transferring data 669 * + If there are multiple spi_device children, the i/o queue 670 * arbitration algorithm is unspecified (round robin, FIFO, 671 * priority, reservations, preemption, etc) 672 * 673 * + Chipselect stays active during the entire message 674 * (unless modified by spi_transfer.cs_change != 0). 675 * + The message transfers use clock and SPI mode parameters 676 * previously established by setup() for this device 677 */ 678 int (*transfer)(struct spi_device *spi, 679 struct spi_message *mesg); 680 681 /* Called on release() to free memory provided by spi_controller */ 682 void (*cleanup)(struct spi_device *spi); 683 684 /* 685 * Used to enable core support for DMA handling, if can_dma() 686 * exists and returns true then the transfer will be mapped 687 * prior to transfer_one() being called. The driver should 688 * not modify or store xfer and dma_tx and dma_rx must be set 689 * while the device is prepared. 690 */ 691 bool (*can_dma)(struct spi_controller *ctlr, 692 struct spi_device *spi, 693 struct spi_transfer *xfer); 694 struct device *dma_map_dev; 695 struct device *cur_rx_dma_dev; 696 struct device *cur_tx_dma_dev; 697 698 /* 699 * These hooks are for drivers that want to use the generic 700 * controller transfer queueing mechanism. If these are used, the 701 * transfer() function above must NOT be specified by the driver. 702 * Over time we expect SPI drivers to be phased over to this API. 703 */ 704 bool queued; 705 struct kthread_worker *kworker; 706 struct kthread_work pump_messages; 707 spinlock_t queue_lock; 708 struct list_head queue; 709 struct spi_message *cur_msg; 710 struct completion cur_msg_completion; 711 bool cur_msg_incomplete; 712 bool cur_msg_need_completion; 713 bool busy; 714 bool running; 715 bool rt; 716 bool auto_runtime_pm; 717 bool fallback; 718 bool last_cs_mode_high; 719 s8 last_cs[SPI_DEVICE_CS_CNT_MAX]; 720 u32 last_cs_index_mask : SPI_DEVICE_CS_CNT_MAX; 721 struct completion xfer_completion; 722 size_t max_dma_len; 723 724 int (*optimize_message)(struct spi_message *msg); 725 int (*unoptimize_message)(struct spi_message *msg); 726 int (*prepare_transfer_hardware)(struct spi_controller *ctlr); 727 int (*transfer_one_message)(struct spi_controller *ctlr, 728 struct spi_message *mesg); 729 int (*unprepare_transfer_hardware)(struct spi_controller *ctlr); 730 int (*prepare_message)(struct spi_controller *ctlr, 731 struct spi_message *message); 732 int (*unprepare_message)(struct spi_controller *ctlr, 733 struct spi_message *message); 734 int (*target_abort)(struct spi_controller *ctlr); 735 736 /* 737 * These hooks are for drivers that use a generic implementation 738 * of transfer_one_message() provided by the core. 739 */ 740 void (*set_cs)(struct spi_device *spi, bool enable); 741 int (*transfer_one)(struct spi_controller *ctlr, struct spi_device *spi, 742 struct spi_transfer *transfer); 743 void (*handle_err)(struct spi_controller *ctlr, 744 struct spi_message *message); 745 746 /* Optimized handlers for SPI memory-like operations. */ 747 const struct spi_controller_mem_ops *mem_ops; 748 const struct spi_controller_mem_caps *mem_caps; 749 750 /* SPI or QSPI controller can set to true if supports SDR/DDR transfer rate */ 751 bool dtr_caps; 752 753 struct spi_offload *(*get_offload)(struct spi_device *spi, 754 const struct spi_offload_config *config); 755 void (*put_offload)(struct spi_offload *offload); 756 757 /* GPIO chip select */ 758 struct gpio_desc **cs_gpiods; 759 bool use_gpio_descriptors; 760 s8 unused_native_cs; 761 s8 max_native_cs; 762 763 /* Statistics */ 764 struct spi_statistics __percpu *pcpu_statistics; 765 766 /* DMA channels for use with core dmaengine helpers */ 767 struct dma_chan *dma_tx; 768 struct dma_chan *dma_rx; 769 770 /* Dummy data for full duplex devices */ 771 void *dummy_rx; 772 void *dummy_tx; 773 774 int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs); 775 776 /* 777 * Driver sets this field to indicate it is able to snapshot SPI 778 * transfers (needed e.g. for reading the time of POSIX clocks) 779 */ 780 bool ptp_sts_supported; 781 782 /* Interrupt enable state during PTP system timestamping */ 783 unsigned long irq_flags; 784 785 /* Flag for enabling opportunistic skipping of the queue in spi_sync */ 786 bool queue_empty; 787 bool must_async; 788 bool defer_optimize_message; 789}; 790 791static inline void *spi_controller_get_devdata(struct spi_controller *ctlr) 792{ 793 return dev_get_drvdata(&ctlr->dev); 794} 795 796static inline void spi_controller_set_devdata(struct spi_controller *ctlr, 797 void *data) 798{ 799 dev_set_drvdata(&ctlr->dev, data); 800} 801 802static inline struct spi_controller *spi_controller_get(struct spi_controller *ctlr) 803{ 804 if (!ctlr || !get_device(&ctlr->dev)) 805 return NULL; 806 return ctlr; 807} 808 809static inline void spi_controller_put(struct spi_controller *ctlr) 810{ 811 if (ctlr) 812 put_device(&ctlr->dev); 813} 814 815static inline bool spi_controller_is_target(struct spi_controller *ctlr) 816{ 817 return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->target; 818} 819 820/* PM calls that need to be issued by the driver */ 821extern int spi_controller_suspend(struct spi_controller *ctlr); 822extern int spi_controller_resume(struct spi_controller *ctlr); 823 824/* Calls the driver make to interact with the message queue */ 825extern struct spi_message *spi_get_next_queued_message(struct spi_controller *ctlr); 826extern void spi_finalize_current_message(struct spi_controller *ctlr); 827extern void spi_finalize_current_transfer(struct spi_controller *ctlr); 828 829/* Helper calls for driver to timestamp transfer */ 830void spi_take_timestamp_pre(struct spi_controller *ctlr, 831 struct spi_transfer *xfer, 832 size_t progress, bool irqs_off); 833void spi_take_timestamp_post(struct spi_controller *ctlr, 834 struct spi_transfer *xfer, 835 size_t progress, bool irqs_off); 836 837/* The SPI driver core manages memory for the spi_controller classdev */ 838extern struct spi_controller *__spi_alloc_controller(struct device *host, 839 unsigned int size, bool target); 840 841static inline struct spi_controller *spi_alloc_host(struct device *dev, 842 unsigned int size) 843{ 844 return __spi_alloc_controller(dev, size, false); 845} 846 847static inline struct spi_controller *spi_alloc_target(struct device *dev, 848 unsigned int size) 849{ 850 if (!IS_ENABLED(CONFIG_SPI_SLAVE)) 851 return NULL; 852 853 return __spi_alloc_controller(dev, size, true); 854} 855 856struct spi_controller *__devm_spi_alloc_controller(struct device *dev, 857 unsigned int size, 858 bool target); 859 860static inline struct spi_controller *devm_spi_alloc_host(struct device *dev, 861 unsigned int size) 862{ 863 return __devm_spi_alloc_controller(dev, size, false); 864} 865 866static inline struct spi_controller *devm_spi_alloc_target(struct device *dev, 867 unsigned int size) 868{ 869 if (!IS_ENABLED(CONFIG_SPI_SLAVE)) 870 return NULL; 871 872 return __devm_spi_alloc_controller(dev, size, true); 873} 874 875extern int spi_register_controller(struct spi_controller *ctlr); 876extern int devm_spi_register_controller(struct device *dev, 877 struct spi_controller *ctlr); 878extern void spi_unregister_controller(struct spi_controller *ctlr); 879 880#if IS_ENABLED(CONFIG_ACPI) && IS_ENABLED(CONFIG_SPI_MASTER) 881extern struct spi_controller *acpi_spi_find_controller_by_adev(struct acpi_device *adev); 882extern struct spi_device *acpi_spi_device_alloc(struct spi_controller *ctlr, 883 struct acpi_device *adev, 884 int index); 885int acpi_spi_count_resources(struct acpi_device *adev); 886#else 887static inline struct spi_controller *acpi_spi_find_controller_by_adev(struct acpi_device *adev) 888{ 889 return NULL; 890} 891 892static inline struct spi_device *acpi_spi_device_alloc(struct spi_controller *ctlr, 893 struct acpi_device *adev, 894 int index) 895{ 896 return ERR_PTR(-ENODEV); 897} 898 899static inline int acpi_spi_count_resources(struct acpi_device *adev) 900{ 901 return 0; 902} 903#endif 904 905/* 906 * SPI resource management while processing a SPI message 907 */ 908 909typedef void (*spi_res_release_t)(struct spi_controller *ctlr, 910 struct spi_message *msg, 911 void *res); 912 913/** 914 * struct spi_res - SPI resource management structure 915 * @entry: list entry 916 * @release: release code called prior to freeing this resource 917 * @data: extra data allocated for the specific use-case 918 * 919 * This is based on ideas from devres, but focused on life-cycle 920 * management during spi_message processing. 921 */ 922struct spi_res { 923 struct list_head entry; 924 spi_res_release_t release; 925 unsigned long long data[]; /* Guarantee ull alignment */ 926}; 927 928/*---------------------------------------------------------------------------*/ 929 930/* 931 * I/O INTERFACE between SPI controller and protocol drivers 932 * 933 * Protocol drivers use a queue of spi_messages, each transferring data 934 * between the controller and memory buffers. 935 * 936 * The spi_messages themselves consist of a series of read+write transfer 937 * segments. Those segments always read the same number of bits as they 938 * write; but one or the other is easily ignored by passing a NULL buffer 939 * pointer. (This is unlike most types of I/O API, because SPI hardware 940 * is full duplex.) 941 * 942 * NOTE: Allocation of spi_transfer and spi_message memory is entirely 943 * up to the protocol driver, which guarantees the integrity of both (as 944 * well as the data buffers) for as long as the message is queued. 945 */ 946 947/** 948 * struct spi_transfer - a read/write buffer pair 949 * @tx_buf: data to be written (DMA-safe memory), or NULL 950 * @rx_buf: data to be read (DMA-safe memory), or NULL 951 * @tx_dma: DMA address of tx_buf, currently not for client use 952 * @rx_dma: DMA address of rx_buf, currently not for client use 953 * @tx_nbits: number of bits used for writing. If 0 the default 954 * (SPI_NBITS_SINGLE) is used. 955 * @rx_nbits: number of bits used for reading. If 0 the default 956 * (SPI_NBITS_SINGLE) is used. 957 * @len: size of rx and tx buffers (in bytes) 958 * @speed_hz: Select a speed other than the device default for this 959 * transfer. If 0 the default (from @spi_device) is used. 960 * @bits_per_word: select a bits_per_word other than the device default 961 * for this transfer. If 0 the default (from @spi_device) is used. 962 * @dummy_data: indicates transfer is dummy bytes transfer. 963 * @cs_off: performs the transfer with chipselect off. 964 * @cs_change: affects chipselect after this transfer completes 965 * @cs_change_delay: delay between cs deassert and assert when 966 * @cs_change is set and @spi_transfer is not the last in @spi_message 967 * @delay: delay to be introduced after this transfer before 968 * (optionally) changing the chipselect status, then starting 969 * the next transfer or completing this @spi_message. 970 * @word_delay: inter word delay to be introduced after each word size 971 * (set by bits_per_word) transmission. 972 * @effective_speed_hz: the effective SCK-speed that was used to 973 * transfer this transfer. Set to 0 if the SPI bus driver does 974 * not support it. 975 * @transfer_list: transfers are sequenced through @spi_message.transfers 976 * @tx_sg_mapped: If true, the @tx_sg is mapped for DMA 977 * @rx_sg_mapped: If true, the @rx_sg is mapped for DMA 978 * @tx_sg: Scatterlist for transmit, currently not for client use 979 * @rx_sg: Scatterlist for receive, currently not for client use 980 * @offload_flags: Flags that are only applicable to specialized SPI offload 981 * transfers. See %SPI_OFFLOAD_XFER_* in spi-offload.h. 982 * @ptp_sts_word_pre: The word (subject to bits_per_word semantics) offset 983 * within @tx_buf for which the SPI device is requesting that the time 984 * snapshot for this transfer begins. Upon completing the SPI transfer, 985 * this value may have changed compared to what was requested, depending 986 * on the available snapshotting resolution (DMA transfer, 987 * @ptp_sts_supported is false, etc). 988 * @ptp_sts_word_post: See @ptp_sts_word_post. The two can be equal (meaning 989 * that a single byte should be snapshotted). 990 * If the core takes care of the timestamp (if @ptp_sts_supported is false 991 * for this controller), it will set @ptp_sts_word_pre to 0, and 992 * @ptp_sts_word_post to the length of the transfer. This is done 993 * purposefully (instead of setting to spi_transfer->len - 1) to denote 994 * that a transfer-level snapshot taken from within the driver may still 995 * be of higher quality. 996 * @ptp_sts: Pointer to a memory location held by the SPI target device where a 997 * PTP system timestamp structure may lie. If drivers use PIO or their 998 * hardware has some sort of assist for retrieving exact transfer timing, 999 * they can (and should) assert @ptp_sts_supported and populate this 1000 * structure using the ptp_read_system_*ts helper functions. 1001 * The timestamp must represent the time at which the SPI target device has 1002 * processed the word, i.e. the "pre" timestamp should be taken before 1003 * transmitting the "pre" word, and the "post" timestamp after receiving 1004 * transmit confirmation from the controller for the "post" word. 1005 * @dtr_mode: true if supports double transfer rate. 1006 * @timestamped: true if the transfer has been timestamped 1007 * @error: Error status logged by SPI controller driver. 1008 * 1009 * SPI transfers always write the same number of bytes as they read. 1010 * Protocol drivers should always provide @rx_buf and/or @tx_buf. 1011 * In some cases, they may also want to provide DMA addresses for 1012 * the data being transferred; that may reduce overhead, when the 1013 * underlying driver uses DMA. 1014 * 1015 * If the transmit buffer is NULL, zeroes will be shifted out 1016 * while filling @rx_buf. If the receive buffer is NULL, the data 1017 * shifted in will be discarded. Only "len" bytes shift out (or in). 1018 * It's an error to try to shift out a partial word. (For example, by 1019 * shifting out three bytes with word size of sixteen or twenty bits; 1020 * the former uses two bytes per word, the latter uses four bytes.) 1021 * 1022 * In-memory data values are always in native CPU byte order, translated 1023 * from the wire byte order (big-endian except with SPI_LSB_FIRST). So 1024 * for example when bits_per_word is sixteen, buffers are 2N bytes long 1025 * (@len = 2N) and hold N sixteen bit words in CPU byte order. 1026 * 1027 * When the word size of the SPI transfer is not a power-of-two multiple 1028 * of eight bits, those in-memory words include extra bits. In-memory 1029 * words are always seen by protocol drivers as right-justified, so the 1030 * undefined (rx) or unused (tx) bits are always the most significant bits. 1031 * 1032 * All SPI transfers start with the relevant chipselect active. Normally 1033 * it stays selected until after the last transfer in a message. Drivers 1034 * can affect the chipselect signal using cs_change. 1035 * 1036 * (i) If the transfer isn't the last one in the message, this flag is 1037 * used to make the chipselect briefly go inactive in the middle of the 1038 * message. Toggling chipselect in this way may be needed to terminate 1039 * a chip command, letting a single spi_message perform all of group of 1040 * chip transactions together. 1041 * 1042 * (ii) When the transfer is the last one in the message, the chip may 1043 * stay selected until the next transfer. On multi-device SPI busses 1044 * with nothing blocking messages going to other devices, this is just 1045 * a performance hint; starting a message to another device deselects 1046 * this one. But in other cases, this can be used to ensure correctness. 1047 * Some devices need protocol transactions to be built from a series of 1048 * spi_message submissions, where the content of one message is determined 1049 * by the results of previous messages and where the whole transaction 1050 * ends when the chipselect goes inactive. 1051 * 1052 * When SPI can transfer in 1x,2x or 4x. It can get this transfer information 1053 * from device through @tx_nbits and @rx_nbits. In Bi-direction, these 1054 * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x) 1055 * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer. 1056 * 1057 * User may also set dtr_mode to true to use dual transfer mode if desired. if 1058 * not, default considered as single transfer mode. 1059 * 1060 * The code that submits an spi_message (and its spi_transfers) 1061 * to the lower layers is responsible for managing its memory. 1062 * Zero-initialize every field you don't set up explicitly, to 1063 * insulate against future API updates. After you submit a message 1064 * and its transfers, ignore them until its completion callback. 1065 */ 1066struct spi_transfer { 1067 /* 1068 * It's okay if tx_buf == rx_buf (right?). 1069 * For MicroWire, one buffer must be NULL. 1070 * Buffers must work with dma_*map_single() calls. 1071 */ 1072 const void *tx_buf; 1073 void *rx_buf; 1074 unsigned len; 1075 1076#define SPI_TRANS_FAIL_NO_START BIT(0) 1077#define SPI_TRANS_FAIL_IO BIT(1) 1078 u16 error; 1079 1080 bool tx_sg_mapped; 1081 bool rx_sg_mapped; 1082 1083 struct sg_table tx_sg; 1084 struct sg_table rx_sg; 1085 dma_addr_t tx_dma; 1086 dma_addr_t rx_dma; 1087 1088 unsigned dummy_data:1; 1089 unsigned cs_off:1; 1090 unsigned cs_change:1; 1091 unsigned tx_nbits:4; 1092 unsigned rx_nbits:4; 1093 unsigned timestamped:1; 1094 bool dtr_mode; 1095#define SPI_NBITS_SINGLE 0x01 /* 1-bit transfer */ 1096#define SPI_NBITS_DUAL 0x02 /* 2-bit transfer */ 1097#define SPI_NBITS_QUAD 0x04 /* 4-bit transfer */ 1098#define SPI_NBITS_OCTAL 0x08 /* 8-bit transfer */ 1099 u8 bits_per_word; 1100 struct spi_delay delay; 1101 struct spi_delay cs_change_delay; 1102 struct spi_delay word_delay; 1103 u32 speed_hz; 1104 1105 u32 effective_speed_hz; 1106 1107 /* Use %SPI_OFFLOAD_XFER_* from spi-offload.h */ 1108 unsigned int offload_flags; 1109 1110 unsigned int ptp_sts_word_pre; 1111 unsigned int ptp_sts_word_post; 1112 1113 struct ptp_system_timestamp *ptp_sts; 1114 1115 struct list_head transfer_list; 1116}; 1117 1118/** 1119 * struct spi_message - one multi-segment SPI transaction 1120 * @transfers: list of transfer segments in this transaction 1121 * @spi: SPI device to which the transaction is queued 1122 * @pre_optimized: peripheral driver pre-optimized the message 1123 * @optimized: the message is in the optimized state 1124 * @prepared: spi_prepare_message was called for the this message 1125 * @status: zero for success, else negative errno 1126 * @complete: called to report transaction completions 1127 * @context: the argument to complete() when it's called 1128 * @frame_length: the total number of bytes in the message 1129 * @actual_length: the total number of bytes that were transferred in all 1130 * successful segments 1131 * @queue: for use by whichever driver currently owns the message 1132 * @state: for use by whichever driver currently owns the message 1133 * @opt_state: for use by whichever driver currently owns the message 1134 * @resources: for resource management when the SPI message is processed 1135 * @offload: (optional) offload instance used by this message 1136 * 1137 * A @spi_message is used to execute an atomic sequence of data transfers, 1138 * each represented by a struct spi_transfer. The sequence is "atomic" 1139 * in the sense that no other spi_message may use that SPI bus until that 1140 * sequence completes. On some systems, many such sequences can execute as 1141 * a single programmed DMA transfer. On all systems, these messages are 1142 * queued, and might complete after transactions to other devices. Messages 1143 * sent to a given spi_device are always executed in FIFO order. 1144 * 1145 * The code that submits an spi_message (and its spi_transfers) 1146 * to the lower layers is responsible for managing its memory. 1147 * Zero-initialize every field you don't set up explicitly, to 1148 * insulate against future API updates. After you submit a message 1149 * and its transfers, ignore them until its completion callback. 1150 */ 1151struct spi_message { 1152 struct list_head transfers; 1153 1154 struct spi_device *spi; 1155 1156 /* spi_optimize_message() was called for this message */ 1157 bool pre_optimized; 1158 /* __spi_optimize_message() was called for this message */ 1159 bool optimized; 1160 1161 /* spi_prepare_message() was called for this message */ 1162 bool prepared; 1163 1164 /* 1165 * REVISIT: we might want a flag affecting the behavior of the 1166 * last transfer ... allowing things like "read 16 bit length L" 1167 * immediately followed by "read L bytes". Basically imposing 1168 * a specific message scheduling algorithm. 1169 * 1170 * Some controller drivers (message-at-a-time queue processing) 1171 * could provide that as their default scheduling algorithm. But 1172 * others (with multi-message pipelines) could need a flag to 1173 * tell them about such special cases. 1174 */ 1175 1176 /* Completion is reported through a callback */ 1177 int status; 1178 void (*complete)(void *context); 1179 void *context; 1180 unsigned frame_length; 1181 unsigned actual_length; 1182 1183 /* 1184 * For optional use by whatever driver currently owns the 1185 * spi_message ... between calls to spi_async and then later 1186 * complete(), that's the spi_controller controller driver. 1187 */ 1188 struct list_head queue; 1189 void *state; 1190 /* 1191 * Optional state for use by controller driver between calls to 1192 * __spi_optimize_message() and __spi_unoptimize_message(). 1193 */ 1194 void *opt_state; 1195 1196 /* 1197 * Optional offload instance used by this message. This must be set 1198 * by the peripheral driver before calling spi_optimize_message(). 1199 */ 1200 struct spi_offload *offload; 1201 1202 /* List of spi_res resources when the SPI message is processed */ 1203 struct list_head resources; 1204}; 1205 1206static inline void spi_message_init_no_memset(struct spi_message *m) 1207{ 1208 INIT_LIST_HEAD(&m->transfers); 1209 INIT_LIST_HEAD(&m->resources); 1210} 1211 1212static inline void spi_message_init(struct spi_message *m) 1213{ 1214 memset(m, 0, sizeof *m); 1215 spi_message_init_no_memset(m); 1216} 1217 1218static inline void 1219spi_message_add_tail(struct spi_transfer *t, struct spi_message *m) 1220{ 1221 list_add_tail(&t->transfer_list, &m->transfers); 1222} 1223 1224static inline void 1225spi_transfer_del(struct spi_transfer *t) 1226{ 1227 list_del(&t->transfer_list); 1228} 1229 1230static inline int 1231spi_transfer_delay_exec(struct spi_transfer *t) 1232{ 1233 return spi_delay_exec(&t->delay, t); 1234} 1235 1236/** 1237 * spi_message_init_with_transfers - Initialize spi_message and append transfers 1238 * @m: spi_message to be initialized 1239 * @xfers: An array of SPI transfers 1240 * @num_xfers: Number of items in the xfer array 1241 * 1242 * This function initializes the given spi_message and adds each spi_transfer in 1243 * the given array to the message. 1244 */ 1245static inline void 1246spi_message_init_with_transfers(struct spi_message *m, 1247struct spi_transfer *xfers, unsigned int num_xfers) 1248{ 1249 unsigned int i; 1250 1251 spi_message_init(m); 1252 for (i = 0; i < num_xfers; ++i) 1253 spi_message_add_tail(&xfers[i], m); 1254} 1255 1256/* 1257 * It's fine to embed message and transaction structures in other data 1258 * structures so long as you don't free them while they're in use. 1259 */ 1260static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags) 1261{ 1262 struct spi_message_with_transfers { 1263 struct spi_message m; 1264 struct spi_transfer t[]; 1265 } *mwt; 1266 unsigned i; 1267 1268 mwt = kzalloc(struct_size(mwt, t, ntrans), flags); 1269 if (!mwt) 1270 return NULL; 1271 1272 spi_message_init_no_memset(&mwt->m); 1273 for (i = 0; i < ntrans; i++) 1274 spi_message_add_tail(&mwt->t[i], &mwt->m); 1275 1276 return &mwt->m; 1277} 1278 1279static inline void spi_message_free(struct spi_message *m) 1280{ 1281 kfree(m); 1282} 1283 1284extern int spi_optimize_message(struct spi_device *spi, struct spi_message *msg); 1285extern void spi_unoptimize_message(struct spi_message *msg); 1286extern int devm_spi_optimize_message(struct device *dev, struct spi_device *spi, 1287 struct spi_message *msg); 1288 1289extern int spi_setup(struct spi_device *spi); 1290extern int spi_async(struct spi_device *spi, struct spi_message *message); 1291extern int spi_target_abort(struct spi_device *spi); 1292 1293static inline size_t 1294spi_max_message_size(struct spi_device *spi) 1295{ 1296 struct spi_controller *ctlr = spi->controller; 1297 1298 if (!ctlr->max_message_size) 1299 return SIZE_MAX; 1300 return ctlr->max_message_size(spi); 1301} 1302 1303static inline size_t 1304spi_max_transfer_size(struct spi_device *spi) 1305{ 1306 struct spi_controller *ctlr = spi->controller; 1307 size_t tr_max = SIZE_MAX; 1308 size_t msg_max = spi_max_message_size(spi); 1309 1310 if (ctlr->max_transfer_size) 1311 tr_max = ctlr->max_transfer_size(spi); 1312 1313 /* Transfer size limit must not be greater than message size limit */ 1314 return min(tr_max, msg_max); 1315} 1316 1317/** 1318 * spi_is_bpw_supported - Check if bits per word is supported 1319 * @spi: SPI device 1320 * @bpw: Bits per word 1321 * 1322 * This function checks to see if the SPI controller supports @bpw. 1323 * 1324 * Returns: 1325 * True if @bpw is supported, false otherwise. 1326 */ 1327static inline bool spi_is_bpw_supported(struct spi_device *spi, u32 bpw) 1328{ 1329 u32 bpw_mask = spi->controller->bits_per_word_mask; 1330 1331 if (bpw == 8 || (bpw <= 32 && bpw_mask & SPI_BPW_MASK(bpw))) 1332 return true; 1333 1334 return false; 1335} 1336 1337/** 1338 * spi_bpw_to_bytes - Covert bits per word to bytes 1339 * @bpw: Bits per word 1340 * 1341 * This function converts the given @bpw to bytes. The result is always 1342 * power-of-two, e.g., 1343 * 1344 * =============== ================= 1345 * Input (in bits) Output (in bytes) 1346 * =============== ================= 1347 * 5 1 1348 * 9 2 1349 * 21 4 1350 * 37 8 1351 * =============== ================= 1352 * 1353 * It will return 0 for the 0 input. 1354 * 1355 * Returns: 1356 * Bytes for the given @bpw. 1357 */ 1358static inline u32 spi_bpw_to_bytes(u32 bpw) 1359{ 1360 return roundup_pow_of_two(BITS_TO_BYTES(bpw)); 1361} 1362 1363/** 1364 * spi_controller_xfer_timeout - Compute a suitable timeout value 1365 * @ctlr: SPI device 1366 * @xfer: Transfer descriptor 1367 * 1368 * Compute a relevant timeout value for the given transfer. We derive the time 1369 * that it would take on a single data line and take twice this amount of time 1370 * with a minimum of 500ms to avoid false positives on loaded systems. 1371 * 1372 * Returns: Transfer timeout value in milliseconds. 1373 */ 1374static inline unsigned int spi_controller_xfer_timeout(struct spi_controller *ctlr, 1375 struct spi_transfer *xfer) 1376{ 1377 return max(xfer->len * 8 * 2 / (xfer->speed_hz / 1000), 500U); 1378} 1379 1380/*---------------------------------------------------------------------------*/ 1381 1382/* SPI transfer replacement methods which make use of spi_res */ 1383 1384struct spi_replaced_transfers; 1385typedef void (*spi_replaced_release_t)(struct spi_controller *ctlr, 1386 struct spi_message *msg, 1387 struct spi_replaced_transfers *res); 1388/** 1389 * struct spi_replaced_transfers - structure describing the spi_transfer 1390 * replacements that have occurred 1391 * so that they can get reverted 1392 * @release: some extra release code to get executed prior to 1393 * releasing this structure 1394 * @extradata: pointer to some extra data if requested or NULL 1395 * @replaced_transfers: transfers that have been replaced and which need 1396 * to get restored 1397 * @replaced_after: the transfer after which the @replaced_transfers 1398 * are to get re-inserted 1399 * @inserted: number of transfers inserted 1400 * @inserted_transfers: array of spi_transfers of array-size @inserted, 1401 * that have been replacing replaced_transfers 1402 * 1403 * Note: that @extradata will point to @inserted_transfers[@inserted] 1404 * if some extra allocation is requested, so alignment will be the same 1405 * as for spi_transfers. 1406 */ 1407struct spi_replaced_transfers { 1408 spi_replaced_release_t release; 1409 void *extradata; 1410 struct list_head replaced_transfers; 1411 struct list_head *replaced_after; 1412 size_t inserted; 1413 struct spi_transfer inserted_transfers[]; 1414}; 1415 1416/*---------------------------------------------------------------------------*/ 1417 1418/* SPI transfer transformation methods */ 1419 1420extern int spi_split_transfers_maxsize(struct spi_controller *ctlr, 1421 struct spi_message *msg, 1422 size_t maxsize); 1423extern int spi_split_transfers_maxwords(struct spi_controller *ctlr, 1424 struct spi_message *msg, 1425 size_t maxwords); 1426 1427/*---------------------------------------------------------------------------*/ 1428 1429/* 1430 * All these synchronous SPI transfer routines are utilities layered 1431 * over the core async transfer primitive. Here, "synchronous" means 1432 * they will sleep uninterruptibly until the async transfer completes. 1433 */ 1434 1435extern int spi_sync(struct spi_device *spi, struct spi_message *message); 1436extern int spi_sync_locked(struct spi_device *spi, struct spi_message *message); 1437extern int spi_bus_lock(struct spi_controller *ctlr); 1438extern int spi_bus_unlock(struct spi_controller *ctlr); 1439 1440/** 1441 * spi_sync_transfer - synchronous SPI data transfer 1442 * @spi: device with which data will be exchanged 1443 * @xfers: An array of spi_transfers 1444 * @num_xfers: Number of items in the xfer array 1445 * Context: can sleep 1446 * 1447 * Does a synchronous SPI data transfer of the given spi_transfer array. 1448 * 1449 * For more specific semantics see spi_sync(). 1450 * 1451 * Return: zero on success, else a negative error code. 1452 */ 1453static inline int 1454spi_sync_transfer(struct spi_device *spi, struct spi_transfer *xfers, 1455 unsigned int num_xfers) 1456{ 1457 struct spi_message msg; 1458 1459 spi_message_init_with_transfers(&msg, xfers, num_xfers); 1460 1461 return spi_sync(spi, &msg); 1462} 1463 1464/** 1465 * spi_write - SPI synchronous write 1466 * @spi: device to which data will be written 1467 * @buf: data buffer 1468 * @len: data buffer size 1469 * Context: can sleep 1470 * 1471 * This function writes the buffer @buf. 1472 * Callable only from contexts that can sleep. 1473 * 1474 * Return: zero on success, else a negative error code. 1475 */ 1476static inline int 1477spi_write(struct spi_device *spi, const void *buf, size_t len) 1478{ 1479 struct spi_transfer t = { 1480 .tx_buf = buf, 1481 .len = len, 1482 }; 1483 1484 return spi_sync_transfer(spi, &t, 1); 1485} 1486 1487/** 1488 * spi_read - SPI synchronous read 1489 * @spi: device from which data will be read 1490 * @buf: data buffer 1491 * @len: data buffer size 1492 * Context: can sleep 1493 * 1494 * This function reads the buffer @buf. 1495 * Callable only from contexts that can sleep. 1496 * 1497 * Return: zero on success, else a negative error code. 1498 */ 1499static inline int 1500spi_read(struct spi_device *spi, void *buf, size_t len) 1501{ 1502 struct spi_transfer t = { 1503 .rx_buf = buf, 1504 .len = len, 1505 }; 1506 1507 return spi_sync_transfer(spi, &t, 1); 1508} 1509 1510/* This copies txbuf and rxbuf data; for small transfers only! */ 1511extern int spi_write_then_read(struct spi_device *spi, 1512 const void *txbuf, unsigned n_tx, 1513 void *rxbuf, unsigned n_rx); 1514 1515/** 1516 * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read 1517 * @spi: device with which data will be exchanged 1518 * @cmd: command to be written before data is read back 1519 * Context: can sleep 1520 * 1521 * Callable only from contexts that can sleep. 1522 * 1523 * Return: the (unsigned) eight bit number returned by the 1524 * device, or else a negative error code. 1525 */ 1526static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd) 1527{ 1528 ssize_t status; 1529 u8 result; 1530 1531 status = spi_write_then_read(spi, &cmd, 1, &result, 1); 1532 1533 /* Return negative errno or unsigned value */ 1534 return (status < 0) ? status : result; 1535} 1536 1537/** 1538 * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read 1539 * @spi: device with which data will be exchanged 1540 * @cmd: command to be written before data is read back 1541 * Context: can sleep 1542 * 1543 * The number is returned in wire-order, which is at least sometimes 1544 * big-endian. 1545 * 1546 * Callable only from contexts that can sleep. 1547 * 1548 * Return: the (unsigned) sixteen bit number returned by the 1549 * device, or else a negative error code. 1550 */ 1551static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd) 1552{ 1553 ssize_t status; 1554 u16 result; 1555 1556 status = spi_write_then_read(spi, &cmd, 1, &result, 2); 1557 1558 /* Return negative errno or unsigned value */ 1559 return (status < 0) ? status : result; 1560} 1561 1562/** 1563 * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read 1564 * @spi: device with which data will be exchanged 1565 * @cmd: command to be written before data is read back 1566 * Context: can sleep 1567 * 1568 * This function is similar to spi_w8r16, with the exception that it will 1569 * convert the read 16 bit data word from big-endian to native endianness. 1570 * 1571 * Callable only from contexts that can sleep. 1572 * 1573 * Return: the (unsigned) sixteen bit number returned by the device in CPU 1574 * endianness, or else a negative error code. 1575 */ 1576static inline ssize_t spi_w8r16be(struct spi_device *spi, u8 cmd) 1577 1578{ 1579 ssize_t status; 1580 __be16 result; 1581 1582 status = spi_write_then_read(spi, &cmd, 1, &result, 2); 1583 if (status < 0) 1584 return status; 1585 1586 return be16_to_cpu(result); 1587} 1588 1589/*---------------------------------------------------------------------------*/ 1590 1591/* 1592 * INTERFACE between board init code and SPI infrastructure. 1593 * 1594 * No SPI driver ever sees these SPI device table segments, but 1595 * it's how the SPI core (or adapters that get hotplugged) grows 1596 * the driver model tree. 1597 * 1598 * As a rule, SPI devices can't be probed. Instead, board init code 1599 * provides a table listing the devices which are present, with enough 1600 * information to bind and set up the device's driver. There's basic 1601 * support for non-static configurations too; enough to handle adding 1602 * parport adapters, or microcontrollers acting as USB-to-SPI bridges. 1603 */ 1604 1605/** 1606 * struct spi_board_info - board-specific template for a SPI device 1607 * @modalias: Initializes spi_device.modalias; identifies the driver. 1608 * @platform_data: Initializes spi_device.platform_data; the particular 1609 * data stored there is driver-specific. 1610 * @swnode: Software node for the device. 1611 * @controller_data: Initializes spi_device.controller_data; some 1612 * controllers need hints about hardware setup, e.g. for DMA. 1613 * @irq: Initializes spi_device.irq; depends on how the board is wired. 1614 * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits 1615 * from the chip datasheet and board-specific signal quality issues. 1616 * @bus_num: Identifies which spi_controller parents the spi_device; unused 1617 * by spi_new_device(), and otherwise depends on board wiring. 1618 * @chip_select: Initializes spi_device.chip_select; depends on how 1619 * the board is wired. 1620 * @mode: Initializes spi_device.mode; based on the chip datasheet, board 1621 * wiring (some devices support both 3WIRE and standard modes), and 1622 * possibly presence of an inverter in the chipselect path. 1623 * 1624 * When adding new SPI devices to the device tree, these structures serve 1625 * as a partial device template. They hold information which can't always 1626 * be determined by drivers. Information that probe() can establish (such 1627 * as the default transfer wordsize) is not included here. 1628 * 1629 * These structures are used in two places. Their primary role is to 1630 * be stored in tables of board-specific device descriptors, which are 1631 * declared early in board initialization and then used (much later) to 1632 * populate a controller's device tree after the that controller's driver 1633 * initializes. A secondary (and atypical) role is as a parameter to 1634 * spi_new_device() call, which happens after those controller drivers 1635 * are active in some dynamic board configuration models. 1636 */ 1637struct spi_board_info { 1638 /* 1639 * The device name and module name are coupled, like platform_bus; 1640 * "modalias" is normally the driver name. 1641 * 1642 * platform_data goes to spi_device.dev.platform_data, 1643 * controller_data goes to spi_device.controller_data, 1644 * IRQ is copied too. 1645 */ 1646 char modalias[SPI_NAME_SIZE]; 1647 const void *platform_data; 1648 const struct software_node *swnode; 1649 void *controller_data; 1650 int irq; 1651 1652 /* Slower signaling on noisy or low voltage boards */ 1653 u32 max_speed_hz; 1654 1655 1656 /* 1657 * bus_num is board specific and matches the bus_num of some 1658 * spi_controller that will probably be registered later. 1659 * 1660 * chip_select reflects how this chip is wired to that controller; 1661 * it's less than num_chipselect. 1662 */ 1663 u16 bus_num; 1664 u16 chip_select; 1665 1666 /* 1667 * mode becomes spi_device.mode, and is essential for chips 1668 * where the default of SPI_CS_HIGH = 0 is wrong. 1669 */ 1670 u32 mode; 1671 1672 /* 1673 * ... may need additional spi_device chip config data here. 1674 * avoid stuff protocol drivers can set; but include stuff 1675 * needed to behave without being bound to a driver: 1676 * - quirks like clock rate mattering when not selected 1677 */ 1678}; 1679 1680#ifdef CONFIG_SPI 1681extern int 1682spi_register_board_info(struct spi_board_info const *info, unsigned n); 1683#else 1684/* Board init code may ignore whether SPI is configured or not */ 1685static inline int 1686spi_register_board_info(struct spi_board_info const *info, unsigned n) 1687 { return 0; } 1688#endif 1689 1690/* 1691 * If you're hotplugging an adapter with devices (parport, USB, etc) 1692 * use spi_new_device() to describe each device. You can also call 1693 * spi_unregister_device() to start making that device vanish, but 1694 * normally that would be handled by spi_unregister_controller(). 1695 * 1696 * You can also use spi_alloc_device() and spi_add_device() to use a two 1697 * stage registration sequence for each spi_device. This gives the caller 1698 * some more control over the spi_device structure before it is registered, 1699 * but requires that caller to initialize fields that would otherwise 1700 * be defined using the board info. 1701 */ 1702extern struct spi_device * 1703spi_alloc_device(struct spi_controller *ctlr); 1704 1705extern int 1706spi_add_device(struct spi_device *spi); 1707 1708extern struct spi_device * 1709spi_new_device(struct spi_controller *, struct spi_board_info *); 1710 1711extern void spi_unregister_device(struct spi_device *spi); 1712 1713extern const struct spi_device_id * 1714spi_get_device_id(const struct spi_device *sdev); 1715 1716extern const void * 1717spi_get_device_match_data(const struct spi_device *sdev); 1718 1719static inline bool 1720spi_transfer_is_last(struct spi_controller *ctlr, struct spi_transfer *xfer) 1721{ 1722 return list_is_last(&xfer->transfer_list, &ctlr->cur_msg->transfers); 1723} 1724 1725#endif /* __LINUX_SPI_H */
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