sdw_registers.h

  1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
  2/* Copyright(c) 2015-17 Intel Corporation. */
  3
  4#ifndef __SDW_REGISTERS_H
  5#define __SDW_REGISTERS_H
  6
  7#include <linux/bitfield.h>
  8#include <linux/bits.h>
  9
 10/*
 11 * SDW registers as defined by MIPI 1.2 Spec
 12 */
 13#define SDW_REGADDR				GENMASK(14, 0)
 14#define SDW_SCP_ADDRPAGE2_MASK			GENMASK(22, 15)
 15#define SDW_SCP_ADDRPAGE1_MASK			GENMASK(30, 23)
 16
 17#define SDW_REG_NO_PAGE				0x00008000
 18#define SDW_REG_OPTIONAL_PAGE			0x00010000
 19#define SDW_REG_MAX				0x48000000
 20
 21#define SDW_DPN_SIZE				0x100
 22#define SDW_BANK1_OFFSET			0x10
 23
 24/*
 25 * DP0 Interrupt register & bits
 26 *
 27 * Spec treats Status (RO) and Clear (WC) as separate but they are same
 28 * address, so treat as same register with WC.
 29 */
 30
 31/* both INT and STATUS register are same */
 32#define SDW_DP0_INT				0x0
 33#define SDW_DP0_INTMASK				0x1
 34#define SDW_DP0_PORTCTRL			0x2
 35#define SDW_DP0_BLOCKCTRL1			0x3
 36#define SDW_DP0_PREPARESTATUS			0x4
 37#define SDW_DP0_PREPARECTRL			0x5
 38
 39#define SDW_DP0_INT_TEST_FAIL			BIT(0)
 40#define SDW_DP0_INT_PORT_READY			BIT(1)
 41#define SDW_DP0_INT_BRA_FAILURE			BIT(2)
 42#define SDW_DP0_SDCA_CASCADE			BIT(3)
 43/* BIT(4) not allocated in SoundWire specification 1.2 */
 44#define SDW_DP0_INT_IMPDEF1			BIT(5)
 45#define SDW_DP0_INT_IMPDEF2			BIT(6)
 46#define SDW_DP0_INT_IMPDEF3			BIT(7)
 47#define SDW_DP0_INTERRUPTS			(SDW_DP0_INT_TEST_FAIL | \
 48						 SDW_DP0_INT_PORT_READY | \
 49						 SDW_DP0_INT_BRA_FAILURE | \
 50						 SDW_DP0_INT_IMPDEF1 | \
 51						 SDW_DP0_INT_IMPDEF2 | \
 52						 SDW_DP0_INT_IMPDEF3)
 53
 54#define SDW_DP0_PORTCTRL_DATAMODE		GENMASK(3, 2)
 55#define SDW_DP0_PORTCTRL_NXTINVBANK		BIT(4)
 56#define SDW_DP0_PORTCTRL_BPT_PAYLD		GENMASK(7, 6)
 57
 58#define SDW_DP0_CHANNELEN			0x20
 59#define SDW_DP0_SAMPLECTRL1			0x22
 60#define SDW_DP0_SAMPLECTRL2			0x23
 61#define SDW_DP0_OFFSETCTRL1			0x24
 62#define SDW_DP0_OFFSETCTRL2			0x25
 63#define SDW_DP0_HCTRL				0x26
 64#define SDW_DP0_LANECTRL			0x28
 65
 66/* Both INT and STATUS register are same */
 67#define SDW_SCP_INT1				0x40
 68#define SDW_SCP_INTMASK1			0x41
 69
 70#define SDW_SCP_INT1_PARITY			BIT(0)
 71#define SDW_SCP_INT1_BUS_CLASH			BIT(1)
 72#define SDW_SCP_INT1_IMPL_DEF			BIT(2)
 73#define SDW_SCP_INT1_SCP2_CASCADE		BIT(7)
 74#define SDW_SCP_INT1_PORT0_3			GENMASK(6, 3)
 75
 76#define SDW_SCP_INTSTAT2			0x42
 77#define SDW_SCP_INTSTAT2_SCP3_CASCADE		BIT(7)
 78#define SDW_SCP_INTSTAT2_PORT4_10		GENMASK(6, 0)
 79
 80#define SDW_SCP_INTSTAT3			0x43
 81#define SDW_SCP_INTSTAT3_PORT11_14		GENMASK(3, 0)
 82
 83/* Number of interrupt status registers */
 84#define SDW_NUM_INT_STAT_REGISTERS		3
 85
 86/* Number of interrupt clear registers */
 87#define SDW_NUM_INT_CLEAR_REGISTERS		1
 88
 89#define SDW_SCP_CTRL				0x44
 90#define SDW_SCP_CTRL_CLK_STP_NOW		BIT(1)
 91#define SDW_SCP_CTRL_FORCE_RESET		BIT(7)
 92
 93#define SDW_SCP_STAT				0x44
 94#define SDW_SCP_STAT_CLK_STP_NF			BIT(0)
 95#define SDW_SCP_STAT_HPHY_NOK			BIT(5)
 96#define SDW_SCP_STAT_CURR_BANK			BIT(6)
 97
 98#define SDW_SCP_SYSTEMCTRL			0x45
 99#define SDW_SCP_SYSTEMCTRL_CLK_STP_PREP		BIT(0)
100#define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE		BIT(2)
101#define SDW_SCP_SYSTEMCTRL_WAKE_UP_EN		BIT(3)
102#define SDW_SCP_SYSTEMCTRL_HIGH_PHY		BIT(4)
103
104#define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE0	0
105#define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE1	BIT(2)
106
107#define SDW_SCP_DEVNUMBER			0x46
108#define SDW_SCP_HIGH_PHY_CHECK			0x47
109#define SDW_SCP_ADDRPAGE1			0x48
110#define SDW_SCP_ADDRPAGE2			0x49
111#define SDW_SCP_KEEPEREN			0x4A
112#define SDW_SCP_BANKDELAY			0x4B
113#define SDW_SCP_COMMIT				0x4C
114
115#define SDW_SCP_BUS_CLOCK_BASE			0x4D
116#define SDW_SCP_BASE_CLOCK_FREQ			GENMASK(2, 0)
117#define SDW_SCP_BASE_CLOCK_UNKNOWN		0x0
118#define SDW_SCP_BASE_CLOCK_19200000_HZ		0x1
119#define SDW_SCP_BASE_CLOCK_24000000_HZ		0x2
120#define SDW_SCP_BASE_CLOCK_24576000_HZ		0x3
121#define SDW_SCP_BASE_CLOCK_22579200_HZ		0x4
122#define SDW_SCP_BASE_CLOCK_32000000_HZ		0x5
123#define SDW_SCP_BASE_CLOCK_RESERVED		0x6
124#define SDW_SCP_BASE_CLOCK_IMP_DEF		0x7
125
126/* 0x4E is not allocated in SoundWire specification 1.2 */
127#define SDW_SCP_TESTMODE			0x4F
128#define SDW_SCP_DEVID_0				0x50
129#define SDW_SCP_DEVID_1				0x51
130#define SDW_SCP_DEVID_2				0x52
131#define SDW_SCP_DEVID_3				0x53
132#define SDW_SCP_DEVID_4				0x54
133#define SDW_SCP_DEVID_5				0x55
134
135/* Both INT and STATUS register are same */
136#define SDW_SCP_SDCA_INT1			0x58
137#define SDW_SCP_SDCA_INT_SDCA_0			BIT(0)
138#define SDW_SCP_SDCA_INT_SDCA_1			BIT(1)
139#define SDW_SCP_SDCA_INT_SDCA_2			BIT(2)
140#define SDW_SCP_SDCA_INT_SDCA_3			BIT(3)
141#define SDW_SCP_SDCA_INT_SDCA_4			BIT(4)
142#define SDW_SCP_SDCA_INT_SDCA_5			BIT(5)
143#define SDW_SCP_SDCA_INT_SDCA_6			BIT(6)
144#define SDW_SCP_SDCA_INT_SDCA_7			BIT(7)
145
146#define SDW_SCP_SDCA_INT2			0x59
147#define SDW_SCP_SDCA_INT_SDCA_8			BIT(0)
148#define SDW_SCP_SDCA_INT_SDCA_9			BIT(1)
149#define SDW_SCP_SDCA_INT_SDCA_10		BIT(2)
150#define SDW_SCP_SDCA_INT_SDCA_11		BIT(3)
151#define SDW_SCP_SDCA_INT_SDCA_12		BIT(4)
152#define SDW_SCP_SDCA_INT_SDCA_13		BIT(5)
153#define SDW_SCP_SDCA_INT_SDCA_14		BIT(6)
154#define SDW_SCP_SDCA_INT_SDCA_15		BIT(7)
155
156#define SDW_SCP_SDCA_INT3			0x5A
157#define SDW_SCP_SDCA_INT_SDCA_16		BIT(0)
158#define SDW_SCP_SDCA_INT_SDCA_17		BIT(1)
159#define SDW_SCP_SDCA_INT_SDCA_18		BIT(2)
160#define SDW_SCP_SDCA_INT_SDCA_19		BIT(3)
161#define SDW_SCP_SDCA_INT_SDCA_20		BIT(4)
162#define SDW_SCP_SDCA_INT_SDCA_21		BIT(5)
163#define SDW_SCP_SDCA_INT_SDCA_22		BIT(6)
164#define SDW_SCP_SDCA_INT_SDCA_23		BIT(7)
165
166#define SDW_SCP_SDCA_INT4			0x5B
167#define SDW_SCP_SDCA_INT_SDCA_24		BIT(0)
168#define SDW_SCP_SDCA_INT_SDCA_25		BIT(1)
169#define SDW_SCP_SDCA_INT_SDCA_26		BIT(2)
170#define SDW_SCP_SDCA_INT_SDCA_27		BIT(3)
171#define SDW_SCP_SDCA_INT_SDCA_28		BIT(4)
172#define SDW_SCP_SDCA_INT_SDCA_29		BIT(5)
173#define SDW_SCP_SDCA_INT_SDCA_30		BIT(6)
174/* BIT(7) not allocated in SoundWire 1.2 specification */
175
176#define SDW_SCP_SDCA_INTMASK1			0x5C
177#define SDW_SCP_SDCA_INTMASK_SDCA_0		BIT(0)
178#define SDW_SCP_SDCA_INTMASK_SDCA_1		BIT(1)
179#define SDW_SCP_SDCA_INTMASK_SDCA_2		BIT(2)
180#define SDW_SCP_SDCA_INTMASK_SDCA_3		BIT(3)
181#define SDW_SCP_SDCA_INTMASK_SDCA_4		BIT(4)
182#define SDW_SCP_SDCA_INTMASK_SDCA_5		BIT(5)
183#define SDW_SCP_SDCA_INTMASK_SDCA_6		BIT(6)
184#define SDW_SCP_SDCA_INTMASK_SDCA_7		BIT(7)
185
186#define SDW_SCP_SDCA_INTMASK2			0x5D
187#define SDW_SCP_SDCA_INTMASK_SDCA_8		BIT(0)
188#define SDW_SCP_SDCA_INTMASK_SDCA_9		BIT(1)
189#define SDW_SCP_SDCA_INTMASK_SDCA_10		BIT(2)
190#define SDW_SCP_SDCA_INTMASK_SDCA_11		BIT(3)
191#define SDW_SCP_SDCA_INTMASK_SDCA_12		BIT(4)
192#define SDW_SCP_SDCA_INTMASK_SDCA_13		BIT(5)
193#define SDW_SCP_SDCA_INTMASK_SDCA_14		BIT(6)
194#define SDW_SCP_SDCA_INTMASK_SDCA_15		BIT(7)
195
196#define SDW_SCP_SDCA_INTMASK3			0x5E
197#define SDW_SCP_SDCA_INTMASK_SDCA_16		BIT(0)
198#define SDW_SCP_SDCA_INTMASK_SDCA_17		BIT(1)
199#define SDW_SCP_SDCA_INTMASK_SDCA_18		BIT(2)
200#define SDW_SCP_SDCA_INTMASK_SDCA_19		BIT(3)
201#define SDW_SCP_SDCA_INTMASK_SDCA_20		BIT(4)
202#define SDW_SCP_SDCA_INTMASK_SDCA_21		BIT(5)
203#define SDW_SCP_SDCA_INTMASK_SDCA_22		BIT(6)
204#define SDW_SCP_SDCA_INTMASK_SDCA_23		BIT(7)
205
206#define SDW_SCP_SDCA_INTMASK4			0x5F
207#define SDW_SCP_SDCA_INTMASK_SDCA_24		BIT(0)
208#define SDW_SCP_SDCA_INTMASK_SDCA_25		BIT(1)
209#define SDW_SCP_SDCA_INTMASK_SDCA_26		BIT(2)
210#define SDW_SCP_SDCA_INTMASK_SDCA_27		BIT(3)
211#define SDW_SCP_SDCA_INTMASK_SDCA_28		BIT(4)
212#define SDW_SCP_SDCA_INTMASK_SDCA_29		BIT(5)
213#define SDW_SCP_SDCA_INTMASK_SDCA_30		BIT(6)
214/* BIT(7) not allocated in SoundWire 1.2 specification */
215
216/* Banked Registers */
217#define SDW_SCP_FRAMECTRL_B0			0x60
218#define SDW_SCP_FRAMECTRL_B1			(0x60 + SDW_BANK1_OFFSET)
219#define SDW_SCP_NEXTFRAME_B0			0x61
220#define SDW_SCP_NEXTFRAME_B1			(0x61 + SDW_BANK1_OFFSET)
221
222#define SDW_SCP_BUSCLOCK_SCALE_B0		0x62
223#define SDW_SCP_BUSCLOCK_SCALE_B1		(0x62 + SDW_BANK1_OFFSET)
224#define SDW_SCP_CLOCK_SCALE			GENMASK(3, 0)
225
226/* PHY registers - CTRL and STAT are the same address */
227#define SDW_SCP_PHY_OUT_CTRL_0			0x80
228#define SDW_SCP_PHY_OUT_CTRL_1			0x81
229#define SDW_SCP_PHY_OUT_CTRL_2			0x82
230#define SDW_SCP_PHY_OUT_CTRL_3			0x83
231#define SDW_SCP_PHY_OUT_CTRL_4			0x84
232#define SDW_SCP_PHY_OUT_CTRL_5			0x85
233#define SDW_SCP_PHY_OUT_CTRL_6			0x86
234#define SDW_SCP_PHY_OUT_CTRL_7			0x87
235
236#define SDW_SCP_CAP_LOAD_CTRL			GENMASK(2, 0)
237#define SDW_SCP_DRIVE_STRENGTH_CTRL		GENMASK(5, 3)
238#define SDW_SCP_SLEW_TIME_CTRL			GENMASK(7, 6)
239
240/* Both INT and STATUS register is same */
241#define SDW_DPN_INT(n)				(0x0 + SDW_DPN_SIZE * (n))
242#define SDW_DPN_INTMASK(n)			(0x1 + SDW_DPN_SIZE * (n))
243#define SDW_DPN_PORTCTRL(n)			(0x2 + SDW_DPN_SIZE * (n))
244#define SDW_DPN_BLOCKCTRL1(n)			(0x3 + SDW_DPN_SIZE * (n))
245#define SDW_DPN_PREPARESTATUS(n)		(0x4 + SDW_DPN_SIZE * (n))
246#define SDW_DPN_PREPARECTRL(n)			(0x5 + SDW_DPN_SIZE * (n))
247
248#define SDW_DPN_INT_TEST_FAIL			BIT(0)
249#define SDW_DPN_INT_PORT_READY			BIT(1)
250#define SDW_DPN_INT_IMPDEF1			BIT(5)
251#define SDW_DPN_INT_IMPDEF2			BIT(6)
252#define SDW_DPN_INT_IMPDEF3			BIT(7)
253#define SDW_DPN_INTERRUPTS			(SDW_DPN_INT_TEST_FAIL | \
254						 SDW_DPN_INT_PORT_READY | \
255						 SDW_DPN_INT_IMPDEF1 | \
256						 SDW_DPN_INT_IMPDEF2 | \
257						 SDW_DPN_INT_IMPDEF3)
258
259#define SDW_DPN_PORTCTRL_FLOWMODE		GENMASK(1, 0)
260#define SDW_DPN_PORTCTRL_DATAMODE		GENMASK(3, 2)
261#define SDW_DPN_PORTCTRL_NXTINVBANK		BIT(4)
262
263#define SDW_DPN_BLOCKCTRL1_WDLEN		GENMASK(5, 0)
264
265#define SDW_DPN_PREPARECTRL_CH_PREP		GENMASK(7, 0)
266
267#define SDW_DPN_CHANNELEN_B0(n)			(0x20 + SDW_DPN_SIZE * (n))
268#define SDW_DPN_CHANNELEN_B1(n)			(0x30 + SDW_DPN_SIZE * (n))
269
270#define SDW_DPN_BLOCKCTRL2_B0(n)		(0x21 + SDW_DPN_SIZE * (n))
271#define SDW_DPN_BLOCKCTRL2_B1(n)		(0x31 + SDW_DPN_SIZE * (n))
272
273#define SDW_DPN_SAMPLECTRL1_B0(n)		(0x22 + SDW_DPN_SIZE * (n))
274#define SDW_DPN_SAMPLECTRL1_B1(n)		(0x32 + SDW_DPN_SIZE * (n))
275
276#define SDW_DPN_SAMPLECTRL2_B0(n)		(0x23 + SDW_DPN_SIZE * (n))
277#define SDW_DPN_SAMPLECTRL2_B1(n)		(0x33 + SDW_DPN_SIZE * (n))
278
279#define SDW_DPN_OFFSETCTRL1_B0(n)		(0x24 + SDW_DPN_SIZE * (n))
280#define SDW_DPN_OFFSETCTRL1_B1(n)		(0x34 + SDW_DPN_SIZE * (n))
281
282#define SDW_DPN_OFFSETCTRL2_B0(n)		(0x25 + SDW_DPN_SIZE * (n))
283#define SDW_DPN_OFFSETCTRL2_B1(n)		(0x35 + SDW_DPN_SIZE * (n))
284
285#define SDW_DPN_HCTRL_B0(n)			(0x26 + SDW_DPN_SIZE * (n))
286#define SDW_DPN_HCTRL_B1(n)			(0x36 + SDW_DPN_SIZE * (n))
287
288#define SDW_DPN_BLOCKCTRL3_B0(n)		(0x27 + SDW_DPN_SIZE * (n))
289#define SDW_DPN_BLOCKCTRL3_B1(n)		(0x37 + SDW_DPN_SIZE * (n))
290
291#define SDW_DPN_LANECTRL_B0(n)			(0x28 + SDW_DPN_SIZE * (n))
292#define SDW_DPN_LANECTRL_B1(n)			(0x38 + SDW_DPN_SIZE * (n))
293
294#define SDW_DPN_SAMPLECTRL_LOW			GENMASK(7, 0)
295#define SDW_DPN_SAMPLECTRL_HIGH			GENMASK(15, 8)
296
297#define SDW_DPN_HCTRL_HSTART			GENMASK(7, 4)
298#define SDW_DPN_HCTRL_HSTOP			GENMASK(3, 0)
299
300#define SDW_NUM_CASC_PORT_INTSTAT1		4
301#define SDW_CASC_PORT_START_INTSTAT1		0
302#define SDW_CASC_PORT_MASK_INTSTAT1		0x8
303#define SDW_CASC_PORT_REG_OFFSET_INTSTAT1	0x0
304
305#define SDW_NUM_CASC_PORT_INTSTAT2		7
306#define SDW_CASC_PORT_START_INTSTAT2		4
307#define SDW_CASC_PORT_MASK_INTSTAT2		1
308#define SDW_CASC_PORT_REG_OFFSET_INTSTAT2	1
309
310#define SDW_NUM_CASC_PORT_INTSTAT3		4
311#define SDW_CASC_PORT_START_INTSTAT3		11
312#define SDW_CASC_PORT_MASK_INTSTAT3		1
313#define SDW_CASC_PORT_REG_OFFSET_INTSTAT3	2
314
315/*
316 * v1.2 device - SDCA address mapping
317 *
318 * Spec definition
319 *	Bits		Contents
320 *	31		0 (required by addressing range)
321 *	30:26		0b10000 (Control Prefix)
322 *	25		0 (Reserved)
323 *	24:22		Function Number [2:0]
324 *	21		Entity[6]
325 *	20:19		Control Selector[5:4]
326 *	18		0 (Reserved)
327 *	17:15		Control Number[5:3]
328 *	14		Next
329 *	13		MBQ
330 *	12:7		Entity[5:0]
331 *	6:3		Control Selector[3:0]
332 *	2:0		Control Number[2:0]
333 */
334
335#define SDW_SDCA_CTL(fun, ent, ctl, ch)		(BIT(30) |				\
336						 (((fun) & GENMASK(2, 0)) << 22) |	\
337						 (((ent) & BIT(6)) << 15) |		\
338						 (((ent) & GENMASK(5, 0)) << 7) |	\
339						 (((ctl) & GENMASK(5, 4)) << 15) |	\
340						 (((ctl) & GENMASK(3, 0)) << 3) |	\
341						 (((ch) & GENMASK(5, 3)) << 12) |	\
342						 ((ch) & GENMASK(2, 0)))
343
344#define SDW_SDCA_CTL_FUNC(reg) FIELD_GET(GENMASK(24, 22), (reg))
345#define SDW_SDCA_CTL_ENT(reg) ((FIELD_GET(BIT(21), (reg)) << 6) | \
346				FIELD_GET(GENMASK(12, 7), (reg)))
347#define SDW_SDCA_CTL_CSEL(reg) ((FIELD_GET(GENMASK(20, 19), (reg)) << 4) | \
348				 FIELD_GET(GENMASK(6, 3), (reg)))
349#define SDW_SDCA_CTL_CNUM(reg) ((FIELD_GET(GENMASK(17, 15), (reg)) << 3) | \
350				 FIELD_GET(GENMASK(2, 0), (reg)))
351
352#define SDW_SDCA_MBQ_CTL(reg)			((reg) | BIT(13))
353#define SDW_SDCA_NEXT_CTL(reg)			((reg) | BIT(14))
354
355/* Check the reserved and fixed bits in address */
356#define SDW_SDCA_VALID_CTL(reg) (((reg) & (GENMASK(31, 25) | BIT(18) | BIT(13))) == BIT(30))
357
358#define SDW_SDCA_MAX_REGISTER			0x47FFFFFF
359
360#endif /* __SDW_REGISTERS_H */