mtk-mmsys.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2015 MediaTek Inc.
  4 */
  5
  6#ifndef __MTK_MMSYS_H
  7#define __MTK_MMSYS_H
  8
  9#include <linux/mailbox_controller.h>
 10#include <linux/mailbox/mtk-cmdq-mailbox.h>
 11#include <linux/soc/mediatek/mtk-cmdq.h>
 12
 13enum mtk_ddp_comp_id;
 14struct device;
 15
 16enum mtk_dpi_out_format_con {
 17	MTK_DPI_RGB888_SDR_CON,
 18	MTK_DPI_RGB888_DDR_CON,
 19	MTK_DPI_RGB565_SDR_CON,
 20	MTK_DPI_RGB565_DDR_CON
 21};
 22
 23enum mtk_ddp_comp_id {
 24	DDP_COMPONENT_AAL0,
 25	DDP_COMPONENT_AAL1,
 26	DDP_COMPONENT_BLS,
 27	DDP_COMPONENT_CCORR,
 28	DDP_COMPONENT_COLOR0,
 29	DDP_COMPONENT_COLOR1,
 30	DDP_COMPONENT_DITHER0,
 31	DDP_COMPONENT_DITHER1,
 32	DDP_COMPONENT_DP_INTF0,
 33	DDP_COMPONENT_DP_INTF1,
 34	DDP_COMPONENT_DPI0,
 35	DDP_COMPONENT_DPI1,
 36	DDP_COMPONENT_DSC0,
 37	DDP_COMPONENT_DSC1,
 38	DDP_COMPONENT_DSI0,
 39	DDP_COMPONENT_DSI1,
 40	DDP_COMPONENT_DSI2,
 41	DDP_COMPONENT_DSI3,
 42	DDP_COMPONENT_ETHDR_MIXER,
 43	DDP_COMPONENT_GAMMA,
 44	DDP_COMPONENT_MDP_RDMA0,
 45	DDP_COMPONENT_MDP_RDMA1,
 46	DDP_COMPONENT_MDP_RDMA2,
 47	DDP_COMPONENT_MDP_RDMA3,
 48	DDP_COMPONENT_MDP_RDMA4,
 49	DDP_COMPONENT_MDP_RDMA5,
 50	DDP_COMPONENT_MDP_RDMA6,
 51	DDP_COMPONENT_MDP_RDMA7,
 52	DDP_COMPONENT_MERGE0,
 53	DDP_COMPONENT_MERGE1,
 54	DDP_COMPONENT_MERGE2,
 55	DDP_COMPONENT_MERGE3,
 56	DDP_COMPONENT_MERGE4,
 57	DDP_COMPONENT_MERGE5,
 58	DDP_COMPONENT_OD0,
 59	DDP_COMPONENT_OD1,
 60	DDP_COMPONENT_OVL0,
 61	DDP_COMPONENT_OVL_2L0,
 62	DDP_COMPONENT_OVL_2L1,
 63	DDP_COMPONENT_OVL_2L2,
 64	DDP_COMPONENT_OVL1,
 65	DDP_COMPONENT_PADDING0,
 66	DDP_COMPONENT_PADDING1,
 67	DDP_COMPONENT_PADDING2,
 68	DDP_COMPONENT_PADDING3,
 69	DDP_COMPONENT_PADDING4,
 70	DDP_COMPONENT_PADDING5,
 71	DDP_COMPONENT_PADDING6,
 72	DDP_COMPONENT_PADDING7,
 73	DDP_COMPONENT_POSTMASK0,
 74	DDP_COMPONENT_PWM0,
 75	DDP_COMPONENT_PWM1,
 76	DDP_COMPONENT_PWM2,
 77	DDP_COMPONENT_RDMA0,
 78	DDP_COMPONENT_RDMA1,
 79	DDP_COMPONENT_RDMA2,
 80	DDP_COMPONENT_RDMA4,
 81	DDP_COMPONENT_UFOE,
 82	DDP_COMPONENT_WDMA0,
 83	DDP_COMPONENT_WDMA1,
 84	DDP_COMPONENT_ID_MAX,
 85};
 86
 87void mtk_mmsys_ddp_connect(struct device *dev,
 88			   enum mtk_ddp_comp_id cur,
 89			   enum mtk_ddp_comp_id next);
 90
 91void mtk_mmsys_ddp_disconnect(struct device *dev,
 92			      enum mtk_ddp_comp_id cur,
 93			      enum mtk_ddp_comp_id next);
 94
 95void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val);
 96
 97void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width,
 98				  int height, struct cmdq_pkt *cmdq_pkt);
 99
100void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height,
101			  struct cmdq_pkt *cmdq_pkt);
102
103void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha,
104			       u8 mode, u32 biwidth, struct cmdq_pkt *cmdq_pkt);
105
106void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap,
107				     struct cmdq_pkt *cmdq_pkt);
108
109void mtk_mmsys_vpp_rsz_merge_config(struct device *dev, u32 id, bool enable,
110				    struct cmdq_pkt *cmdq_pkt);
111
112void mtk_mmsys_vpp_rsz_dcm_config(struct device *dev, bool enable,
113				  struct cmdq_pkt *cmdq_pkt);
114
115#endif /* __MTK_MMSYS_H */