rtsx_usb.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/* Driver for Realtek RTS5139 USB card reader
  3 *
  4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
  5 *
  6 * Author:
  7 *   Roger Tseng <rogerable@realtek.com>
  8 */
  9
 10#ifndef __RTSX_USB_H
 11#define __RTSX_USB_H
 12
 13#include <linux/usb.h>
 14
 15#define DRV_NAME_RTSX_USB		"rtsx_usb"
 16#define DRV_NAME_RTSX_USB_SDMMC		"rtsx_usb_sdmmc"
 17#define DRV_NAME_RTSX_USB_MS		"rtsx_usb_ms"
 18
 19/* related module names */
 20#define RTSX_USB_SD_CARD	0
 21#define RTSX_USB_MS_CARD	1
 22
 23/* endpoint numbers */
 24#define EP_BULK_OUT		1
 25#define EP_BULK_IN		2
 26#define EP_INTR_IN		3
 27
 28/* USB vendor requests */
 29#define RTSX_USB_REQ_REG_OP	0x00
 30#define RTSX_USB_REQ_POLL	0x02
 31
 32/* miscellaneous parameters */
 33#define MIN_DIV_N		60
 34#define MAX_DIV_N		120
 35
 36#define MAX_PHASE		15
 37#define RX_TUNING_CNT		3
 38
 39#define QFN24			0
 40#define LQFP48			1
 41#define CHECK_PKG(ucr, pkg)	((ucr)->package == (pkg))
 42
 43/* data structures */
 44struct rtsx_ucr {
 45	u16			vendor_id;
 46	u16			product_id;
 47
 48	int			package;
 49	u8			ic_version;
 50	bool			is_rts5179;
 51
 52	unsigned int		cur_clk;
 53
 54	u8			*cmd_buf;
 55	unsigned int		cmd_idx;
 56	u8			*rsp_buf;
 57
 58	struct usb_device	*pusb_dev;
 59	struct usb_interface	*pusb_intf;
 60	struct usb_sg_request	current_sg;
 61
 62	struct timer_list	sg_timer;
 63	struct mutex		dev_mutex;
 64};
 65
 66/* buffer size */
 67#define IOBUF_SIZE		1024
 68
 69/* prototypes of exported functions */
 70extern int rtsx_usb_get_card_status(struct rtsx_ucr *ucr, u16 *status);
 71
 72extern int rtsx_usb_read_register(struct rtsx_ucr *ucr, u16 addr, u8 *data);
 73extern int rtsx_usb_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask,
 74		u8 data);
 75
 76extern int rtsx_usb_ep0_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask,
 77		u8 data);
 78extern int rtsx_usb_ep0_read_register(struct rtsx_ucr *ucr, u16 addr,
 79		u8 *data);
 80
 81extern void rtsx_usb_add_cmd(struct rtsx_ucr *ucr, u8 cmd_type,
 82		u16 reg_addr, u8 mask, u8 data);
 83extern int rtsx_usb_send_cmd(struct rtsx_ucr *ucr, u8 flag, int timeout);
 84extern int rtsx_usb_get_rsp(struct rtsx_ucr *ucr, int rsp_len, int timeout);
 85extern int rtsx_usb_transfer_data(struct rtsx_ucr *ucr, unsigned int pipe,
 86			      void *buf, unsigned int len, int use_sg,
 87			      unsigned int *act_len, int timeout);
 88
 89extern int rtsx_usb_read_ppbuf(struct rtsx_ucr *ucr, u8 *buf, int buf_len);
 90extern int rtsx_usb_write_ppbuf(struct rtsx_ucr *ucr, u8 *buf, int buf_len);
 91extern int rtsx_usb_switch_clock(struct rtsx_ucr *ucr, unsigned int card_clock,
 92		u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
 93extern int rtsx_usb_card_exclusive_check(struct rtsx_ucr *ucr, int card);
 94
 95/* card status */
 96#define SD_CD		0x01
 97#define MS_CD		0x02
 98#define XD_CD		0x04
 99#define CD_MASK		(SD_CD | MS_CD | XD_CD)
100#define SD_WP		0x08
101
102/* OCPCTL */
103#define MS_OCP_DETECT_EN		0x08
104#define	MS_OCP_INT_EN			0x04
105#define	MS_OCP_INT_CLR			0x02
106#define	MS_OCP_CLEAR			0x01
107
108/* OCPSTAT */
109#define MS_OCP_DETECT			0x80
110#define MS_OCP_NOW			0x02
111#define MS_OCP_EVER			0x01
112
113/* reader command field offset & parameters */
114#define READ_REG_CMD		0
115#define WRITE_REG_CMD		1
116#define CHECK_REG_CMD		2
117
118#define PACKET_TYPE		4
119#define CNT_H			5
120#define CNT_L			6
121#define STAGE_FLAG		7
122#define CMD_OFFSET		8
123#define SEQ_WRITE_DATA_OFFSET	12
124
125#define BATCH_CMD		0
126#define SEQ_READ		1
127#define SEQ_WRITE		2
128
129#define STAGE_R			0x01
130#define STAGE_DI		0x02
131#define STAGE_DO		0x04
132#define STAGE_MS_STATUS		0x08
133#define STAGE_XD_STATUS		0x10
134#define MODE_C			0x00
135#define MODE_CR			(STAGE_R)
136#define MODE_CDIR		(STAGE_R | STAGE_DI)
137#define MODE_CDOR		(STAGE_R | STAGE_DO)
138
139#define EP0_OP_SHIFT		14
140#define EP0_READ_REG_CMD	2
141#define EP0_WRITE_REG_CMD	3
142
143#define rtsx_usb_cmd_hdr_tag(ucr)		\
144	do {					\
145		ucr->cmd_buf[0] = 'R';		\
146		ucr->cmd_buf[1] = 'T';		\
147		ucr->cmd_buf[2] = 'C';		\
148		ucr->cmd_buf[3] = 'R';		\
149	} while (0)
150
151static inline void rtsx_usb_init_cmd(struct rtsx_ucr *ucr)
152{
153	rtsx_usb_cmd_hdr_tag(ucr);
154	ucr->cmd_idx = 0;
155	ucr->cmd_buf[PACKET_TYPE] = BATCH_CMD;
156}
157
158/* internal register address */
159#define FPDCTL				0xFC00
160#define SSC_DIV_N_0			0xFC07
161#define SSC_CTL1			0xFC09
162#define SSC_CTL2			0xFC0A
163#define CFG_MODE			0xFC0E
164#define CFG_MODE_1			0xFC0F
165#define RCCTL				0xFC14
166#define SOF_WDOG			0xFC28
167#define SYS_DUMMY0			0xFC30
168
169#define MS_BLKEND			0xFD30
170#define MS_READ_START			0xFD31
171#define MS_READ_COUNT			0xFD32
172#define MS_WRITE_START			0xFD33
173#define MS_WRITE_COUNT			0xFD34
174#define MS_COMMAND			0xFD35
175#define MS_OLD_BLOCK_0			0xFD36
176#define MS_OLD_BLOCK_1			0xFD37
177#define MS_NEW_BLOCK_0			0xFD38
178#define MS_NEW_BLOCK_1			0xFD39
179#define MS_LOG_BLOCK_0			0xFD3A
180#define MS_LOG_BLOCK_1			0xFD3B
181#define MS_BUS_WIDTH			0xFD3C
182#define MS_PAGE_START			0xFD3D
183#define MS_PAGE_LENGTH			0xFD3E
184#define MS_CFG				0xFD40
185#define MS_TPC				0xFD41
186#define MS_TRANS_CFG			0xFD42
187#define MS_TRANSFER			0xFD43
188#define MS_INT_REG			0xFD44
189#define MS_BYTE_CNT			0xFD45
190#define MS_SECTOR_CNT_L			0xFD46
191#define MS_SECTOR_CNT_H			0xFD47
192#define MS_DBUS_H			0xFD48
193
194#define CARD_DMA1_CTL			0xFD5C
195#define CARD_PULL_CTL1			0xFD60
196#define CARD_PULL_CTL2			0xFD61
197#define CARD_PULL_CTL3			0xFD62
198#define CARD_PULL_CTL4			0xFD63
199#define CARD_PULL_CTL5			0xFD64
200#define CARD_PULL_CTL6			0xFD65
201#define CARD_EXIST			0xFD6F
202#define CARD_INT_PEND			0xFD71
203
204#define LDO_POWER_CFG			0xFD7B
205
206#define SD_CFG1				0xFDA0
207#define SD_CFG2				0xFDA1
208#define SD_CFG3				0xFDA2
209#define SD_STAT1			0xFDA3
210#define SD_STAT2			0xFDA4
211#define SD_BUS_STAT			0xFDA5
212#define SD_PAD_CTL			0xFDA6
213#define SD_SAMPLE_POINT_CTL		0xFDA7
214#define SD_PUSH_POINT_CTL		0xFDA8
215#define SD_CMD0				0xFDA9
216#define SD_CMD1				0xFDAA
217#define SD_CMD2				0xFDAB
218#define SD_CMD3				0xFDAC
219#define SD_CMD4				0xFDAD
220#define SD_CMD5				0xFDAE
221#define SD_BYTE_CNT_L			0xFDAF
222#define SD_BYTE_CNT_H			0xFDB0
223#define SD_BLOCK_CNT_L			0xFDB1
224#define SD_BLOCK_CNT_H			0xFDB2
225#define SD_TRANSFER			0xFDB3
226#define SD_CMD_STATE			0xFDB5
227#define SD_DATA_STATE			0xFDB6
228#define SD_VPCLK0_CTL			0xFC2A
229#define SD_VPCLK1_CTL			0xFC2B
230#define SD_DCMPS0_CTL			0xFC2C
231#define SD_DCMPS1_CTL			0xFC2D
232
233#define CARD_DMA1_CTL			0xFD5C
234
235#define HW_VERSION			0xFC01
236
237#define SSC_CLK_FPGA_SEL		0xFC02
238#define CLK_DIV				0xFC03
239#define SFSM_ED				0xFC04
240
241#define CD_DEGLITCH_WIDTH		0xFC20
242#define CD_DEGLITCH_EN			0xFC21
243#define AUTO_DELINK_EN			0xFC23
244
245#define FPGA_PULL_CTL			0xFC1D
246#define CARD_CLK_SOURCE			0xFC2E
247
248#define CARD_SHARE_MODE			0xFD51
249#define CARD_DRIVE_SEL			0xFD52
250#define CARD_STOP			0xFD53
251#define CARD_OE				0xFD54
252#define CARD_AUTO_BLINK			0xFD55
253#define CARD_GPIO			0xFD56
254#define SD30_DRIVE_SEL			0xFD57
255
256#define CARD_DATA_SOURCE		0xFD5D
257#define CARD_SELECT			0xFD5E
258
259#define CARD_CLK_EN			0xFD79
260#define CARD_PWR_CTL			0xFD7A
261
262#define OCPCTL				0xFD80
263#define OCPPARA1			0xFD81
264#define OCPPARA2			0xFD82
265#define OCPSTAT				0xFD83
266
267#define HS_USB_STAT			0xFE01
268#define HS_VCONTROL			0xFE26
269#define HS_VSTAIN			0xFE27
270#define HS_VLOADM			0xFE28
271#define HS_VSTAOUT			0xFE29
272
273#define MC_IRQ				0xFF00
274#define MC_IRQEN			0xFF01
275#define MC_FIFO_CTL			0xFF02
276#define MC_FIFO_BC0			0xFF03
277#define MC_FIFO_BC1			0xFF04
278#define MC_FIFO_STAT			0xFF05
279#define MC_FIFO_MODE			0xFF06
280#define MC_FIFO_RD_PTR0			0xFF07
281#define MC_FIFO_RD_PTR1			0xFF08
282#define MC_DMA_CTL			0xFF10
283#define MC_DMA_TC0			0xFF11
284#define MC_DMA_TC1			0xFF12
285#define MC_DMA_TC2			0xFF13
286#define MC_DMA_TC3			0xFF14
287#define MC_DMA_RST			0xFF15
288
289#define RBUF_SIZE_MASK			0xFBFF
290#define RBUF_BASE			0xF000
291#define PPBUF_BASE1			0xF800
292#define PPBUF_BASE2			0xFA00
293
294/* internal register value macros */
295#define POWER_OFF			0x03
296#define PARTIAL_POWER_ON		0x02
297#define POWER_ON			0x00
298#define POWER_MASK			0x03
299#define LDO3318_PWR_MASK		0x0C
300#define LDO_ON				0x00
301#define LDO_SUSPEND			0x08
302#define LDO_OFF				0x0C
303#define DV3318_AUTO_PWR_OFF		0x10
304#define FORCE_LDO_POWERB		0x60
305
306/* LDO_POWER_CFG */
307#define TUNE_SD18_MASK			0x1C
308#define TUNE_SD18_1V7			0x00
309#define TUNE_SD18_1V8			(0x01 << 2)
310#define TUNE_SD18_1V9			(0x02 << 2)
311#define TUNE_SD18_2V0			(0x03 << 2)
312#define TUNE_SD18_2V7			(0x04 << 2)
313#define TUNE_SD18_2V8			(0x05 << 2)
314#define TUNE_SD18_2V9			(0x06 << 2)
315#define TUNE_SD18_3V3			(0x07 << 2)
316
317/* CLK_DIV */
318#define CLK_CHANGE			0x80
319#define CLK_DIV_1			0x00
320#define CLK_DIV_2			0x01
321#define CLK_DIV_4			0x02
322#define CLK_DIV_8			0x03
323
324#define SSC_POWER_MASK			0x01
325#define SSC_POWER_DOWN			0x01
326#define SSC_POWER_ON			0x00
327
328#define FPGA_VER			0x80
329#define HW_VER_MASK			0x0F
330
331#define EXTEND_DMA1_ASYNC_SIGNAL	0x02
332
333/* CFG_MODE*/
334#define XTAL_FREE			0x80
335#define CLK_MODE_MASK			0x03
336#define CLK_MODE_12M_XTAL		0x00
337#define CLK_MODE_NON_XTAL		0x01
338#define CLK_MODE_24M_OSC		0x02
339#define CLK_MODE_48M_OSC		0x03
340
341/* CFG_MODE_1*/
342#define RTS5179				0x02
343
344#define NYET_EN				0x01
345#define NYET_MSAK			0x01
346
347#define SD30_DRIVE_MASK			0x07
348#define SD20_DRIVE_MASK			0x03
349
350#define DISABLE_SD_CD			0x08
351#define DISABLE_MS_CD			0x10
352#define DISABLE_XD_CD			0x20
353#define SD_CD_DEGLITCH_EN		0x01
354#define MS_CD_DEGLITCH_EN		0x02
355#define XD_CD_DEGLITCH_EN		0x04
356
357#define	CARD_SHARE_LQFP48		0x04
358#define	CARD_SHARE_QFN24		0x00
359#define CARD_SHARE_LQFP_SEL		0x04
360#define	CARD_SHARE_XD			0x00
361#define	CARD_SHARE_SD			0x01
362#define	CARD_SHARE_MS			0x02
363#define CARD_SHARE_MASK			0x03
364
365
366/* SD30_DRIVE_SEL */
367#define DRIVER_TYPE_A			0x05
368#define DRIVER_TYPE_B			0x03
369#define DRIVER_TYPE_C			0x02
370#define DRIVER_TYPE_D			0x01
371
372/* SD_BUS_STAT */
373#define	SD_CLK_TOGGLE_EN		0x80
374#define	SD_CLK_FORCE_STOP	        0x40
375#define	SD_DAT3_STATUS		        0x10
376#define	SD_DAT2_STATUS		        0x08
377#define	SD_DAT1_STATUS		        0x04
378#define	SD_DAT0_STATUS		        0x02
379#define	SD_CMD_STATUS			0x01
380
381/* SD_PAD_CTL */
382#define	SD_IO_USING_1V8		        0x80
383#define	SD_IO_USING_3V3		        0x7F
384#define	TYPE_A_DRIVING		        0x00
385#define	TYPE_B_DRIVING			0x01
386#define	TYPE_C_DRIVING			0x02
387#define	TYPE_D_DRIVING		        0x03
388
389/* CARD_CLK_EN */
390#define SD_CLK_EN			0x04
391#define MS_CLK_EN			0x08
392
393/* CARD_SELECT */
394#define SD_MOD_SEL			2
395#define MS_MOD_SEL			3
396
397/* CARD_SHARE_MODE */
398#define	CARD_SHARE_LQFP48		0x04
399#define	CARD_SHARE_QFN24		0x00
400#define CARD_SHARE_LQFP_SEL		0x04
401#define	CARD_SHARE_XD			0x00
402#define	CARD_SHARE_SD			0x01
403#define	CARD_SHARE_MS			0x02
404#define CARD_SHARE_MASK			0x03
405
406/* SSC_CTL1 */
407#define SSC_RSTB			0x80
408#define SSC_8X_EN			0x40
409#define SSC_FIX_FRAC			0x20
410#define SSC_SEL_1M			0x00
411#define SSC_SEL_2M			0x08
412#define SSC_SEL_4M			0x10
413#define SSC_SEL_8M			0x18
414
415/* SSC_CTL2 */
416#define SSC_DEPTH_MASK			0x03
417#define SSC_DEPTH_DISALBE		0x00
418#define SSC_DEPTH_2M			0x01
419#define SSC_DEPTH_1M			0x02
420#define SSC_DEPTH_512K			0x03
421
422/* SD_VPCLK0_CTL */
423#define PHASE_CHANGE			0x80
424#define PHASE_NOT_RESET			0x40
425
426/* SD_TRANSFER */
427#define	SD_TRANSFER_START		0x80
428#define	SD_TRANSFER_END			0x40
429#define SD_STAT_IDLE			0x20
430#define	SD_TRANSFER_ERR			0x10
431#define	SD_TM_NORMAL_WRITE		0x00
432#define	SD_TM_AUTO_WRITE_3		0x01
433#define	SD_TM_AUTO_WRITE_4		0x02
434#define	SD_TM_AUTO_READ_3		0x05
435#define	SD_TM_AUTO_READ_4		0x06
436#define	SD_TM_CMD_RSP			0x08
437#define	SD_TM_AUTO_WRITE_1		0x09
438#define	SD_TM_AUTO_WRITE_2		0x0A
439#define	SD_TM_NORMAL_READ		0x0C
440#define	SD_TM_AUTO_READ_1		0x0D
441#define	SD_TM_AUTO_READ_2		0x0E
442#define	SD_TM_AUTO_TUNING		0x0F
443
444/* SD_CFG1 */
445#define SD_CLK_DIVIDE_0			0x00
446#define	SD_CLK_DIVIDE_256		0xC0
447#define	SD_CLK_DIVIDE_128		0x80
448#define SD_CLK_DIVIDE_MASK		0xC0
449#define	SD_BUS_WIDTH_1BIT		0x00
450#define	SD_BUS_WIDTH_4BIT		0x01
451#define	SD_BUS_WIDTH_8BIT		0x02
452#define	SD_ASYNC_FIFO_RST		0x10
453#define	SD_20_MODE			0x00
454#define	SD_DDR_MODE			0x04
455#define	SD_30_MODE			0x08
456
457/* SD_CFG2 */
458#define	SD_CALCULATE_CRC7		0x00
459#define	SD_NO_CALCULATE_CRC7		0x80
460#define	SD_CHECK_CRC16			0x00
461#define	SD_NO_CHECK_CRC16		0x40
462#define SD_WAIT_CRC_TO_EN		0x20
463#define	SD_WAIT_BUSY_END		0x08
464#define	SD_NO_WAIT_BUSY_END		0x00
465#define	SD_CHECK_CRC7			0x00
466#define	SD_NO_CHECK_CRC7		0x04
467#define	SD_RSP_LEN_0			0x00
468#define	SD_RSP_LEN_6			0x01
469#define	SD_RSP_LEN_17			0x02
470#define	SD_RSP_TYPE_R0			0x04
471#define	SD_RSP_TYPE_R1			0x01
472#define	SD_RSP_TYPE_R1b			0x09
473#define	SD_RSP_TYPE_R2			0x02
474#define	SD_RSP_TYPE_R3			0x05
475#define	SD_RSP_TYPE_R4			0x05
476#define	SD_RSP_TYPE_R5			0x01
477#define	SD_RSP_TYPE_R6			0x01
478#define	SD_RSP_TYPE_R7			0x01
479
480/* SD_STAT1 */
481#define	SD_CRC7_ERR			0x80
482#define	SD_CRC16_ERR			0x40
483#define	SD_CRC_WRITE_ERR		0x20
484#define	SD_CRC_WRITE_ERR_MASK		0x1C
485#define	GET_CRC_TIME_OUT		0x02
486#define	SD_TUNING_COMPARE_ERR		0x01
487
488/* SD_DATA_STATE */
489#define SD_DATA_IDLE			0x80
490
491/* CARD_DATA_SOURCE */
492#define PINGPONG_BUFFER			0x01
493#define RING_BUFFER			0x00
494
495/* CARD_OE */
496#define SD_OUTPUT_EN			0x04
497#define MS_OUTPUT_EN			0x08
498
499/* CARD_STOP */
500#define SD_STOP				0x04
501#define MS_STOP				0x08
502#define SD_CLR_ERR			0x40
503#define MS_CLR_ERR			0x80
504
505/* CARD_CLK_SOURCE */
506#define CRC_FIX_CLK			(0x00 << 0)
507#define CRC_VAR_CLK0			(0x01 << 0)
508#define CRC_VAR_CLK1			(0x02 << 0)
509#define SD30_FIX_CLK			(0x00 << 2)
510#define SD30_VAR_CLK0			(0x01 << 2)
511#define SD30_VAR_CLK1			(0x02 << 2)
512#define SAMPLE_FIX_CLK			(0x00 << 4)
513#define SAMPLE_VAR_CLK0			(0x01 << 4)
514#define SAMPLE_VAR_CLK1			(0x02 << 4)
515
516/* SD_SAMPLE_POINT_CTL */
517#define	DDR_FIX_RX_DAT			0x00
518#define	DDR_VAR_RX_DAT			0x80
519#define	DDR_FIX_RX_DAT_EDGE		0x00
520#define	DDR_FIX_RX_DAT_14_DELAY		0x40
521#define	DDR_FIX_RX_CMD			0x00
522#define	DDR_VAR_RX_CMD			0x20
523#define	DDR_FIX_RX_CMD_POS_EDGE		0x00
524#define	DDR_FIX_RX_CMD_14_DELAY		0x10
525#define	SD20_RX_POS_EDGE		0x00
526#define	SD20_RX_14_DELAY		0x08
527#define SD20_RX_SEL_MASK		0x08
528
529/* SD_PUSH_POINT_CTL */
530#define	DDR_FIX_TX_CMD_DAT		0x00
531#define	DDR_VAR_TX_CMD_DAT		0x80
532#define	DDR_FIX_TX_DAT_14_TSU		0x00
533#define	DDR_FIX_TX_DAT_12_TSU		0x40
534#define	DDR_FIX_TX_CMD_NEG_EDGE		0x00
535#define	DDR_FIX_TX_CMD_14_AHEAD		0x20
536#define	SD20_TX_NEG_EDGE		0x00
537#define	SD20_TX_14_AHEAD		0x10
538#define SD20_TX_SEL_MASK		0x10
539#define	DDR_VAR_SDCLK_POL_SWAP		0x01
540
541/* MS_CFG */
542#define	SAMPLE_TIME_RISING		0x00
543#define	SAMPLE_TIME_FALLING		0x80
544#define	PUSH_TIME_DEFAULT		0x00
545#define	PUSH_TIME_ODD			0x40
546#define	NO_EXTEND_TOGGLE		0x00
547#define	EXTEND_TOGGLE_CHK		0x20
548#define	MS_BUS_WIDTH_1			0x00
549#define	MS_BUS_WIDTH_4			0x10
550#define	MS_BUS_WIDTH_8			0x18
551#define	MS_2K_SECTOR_MODE		0x04
552#define	MS_512_SECTOR_MODE		0x00
553#define	MS_TOGGLE_TIMEOUT_EN		0x00
554#define	MS_TOGGLE_TIMEOUT_DISEN		0x01
555#define MS_NO_CHECK_INT			0x02
556
557/* MS_TRANS_CFG */
558#define	WAIT_INT			0x80
559#define	NO_WAIT_INT			0x00
560#define	NO_AUTO_READ_INT_REG		0x00
561#define	AUTO_READ_INT_REG		0x40
562#define	MS_CRC16_ERR			0x20
563#define	MS_RDY_TIMEOUT			0x10
564#define	MS_INT_CMDNK			0x08
565#define	MS_INT_BREQ			0x04
566#define	MS_INT_ERR			0x02
567#define	MS_INT_CED			0x01
568
569/* MS_TRANSFER */
570#define	MS_TRANSFER_START		0x80
571#define	MS_TRANSFER_END			0x40
572#define	MS_TRANSFER_ERR			0x20
573#define	MS_BS_STATE			0x10
574#define	MS_TM_READ_BYTES		0x00
575#define	MS_TM_NORMAL_READ		0x01
576#define	MS_TM_WRITE_BYTES		0x04
577#define	MS_TM_NORMAL_WRITE		0x05
578#define	MS_TM_AUTO_READ			0x08
579#define	MS_TM_AUTO_WRITE		0x0C
580#define MS_TM_SET_CMD			0x06
581#define MS_TM_COPY_PAGE			0x07
582#define MS_TM_MULTI_READ		0x02
583#define MS_TM_MULTI_WRITE		0x03
584
585/* MC_FIFO_CTL */
586#define FIFO_FLUSH			0x01
587
588/* MC_DMA_RST */
589#define DMA_RESET  0x01
590
591/* MC_DMA_CTL */
592#define DMA_TC_EQ_0			0x80
593#define DMA_DIR_TO_CARD			0x00
594#define DMA_DIR_FROM_CARD		0x02
595#define DMA_EN				0x01
596#define DMA_128				(0 << 2)
597#define DMA_256				(1 << 2)
598#define DMA_512				(2 << 2)
599#define DMA_1024			(3 << 2)
600#define DMA_PACK_SIZE_MASK		0x0C
601
602/* CARD_INT_PEND */
603#define XD_INT				0x10
604#define MS_INT				0x08
605#define SD_INT				0x04
606
607/* LED operations*/
608static inline int rtsx_usb_turn_on_led(struct rtsx_ucr *ucr)
609{
610	return  rtsx_usb_ep0_write_register(ucr, CARD_GPIO, 0x03, 0x02);
611}
612
613static inline int rtsx_usb_turn_off_led(struct rtsx_ucr *ucr)
614{
615	return rtsx_usb_ep0_write_register(ucr, CARD_GPIO, 0x03, 0x03);
616}
617
618/* HW error clearing */
619static inline void rtsx_usb_clear_fsm_err(struct rtsx_ucr *ucr)
620{
621	rtsx_usb_ep0_write_register(ucr, SFSM_ED, 0xf8, 0xf8);
622}
623
624static inline void rtsx_usb_clear_dma_err(struct rtsx_ucr *ucr)
625{
626	rtsx_usb_ep0_write_register(ucr, MC_FIFO_CTL,
627			FIFO_FLUSH, FIFO_FLUSH);
628	rtsx_usb_ep0_write_register(ucr, MC_DMA_RST, DMA_RESET, DMA_RESET);
629}
630#endif /* __RTS51139_H */