mt6363-regulator.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Copyright (c) 2024 MediaTek Inc.
  4 * Copyright (c) 2025 Collabora Ltd
  5 */
  6
  7#include <linux/bits.h>
  8
  9#ifndef __LINUX_REGULATOR_MT6363_H
 10#define __LINUX_REGULATOR_MT6363_H
 11
 12/* Register */
 13#define MT6363_TOP_TRAP				0x6
 14#define MT6363_TOP_TMA_KEY_L			0x36e
 15#define MT6363_RG_BUCK0_EN_ADDR			0x210
 16#define MT6363_RG_BUCK_VS2_EN_BIT		0
 17#define MT6363_RG_BUCK_VBUCK1_EN_BIT		1
 18#define MT6363_RG_BUCK_VBUCK2_EN_BIT		2
 19#define MT6363_RG_BUCK_VBUCK3_EN_BIT		3
 20#define MT6363_RG_BUCK_VBUCK4_EN_BIT		4
 21#define MT6363_RG_BUCK_VBUCK5_EN_BIT		5
 22#define MT6363_RG_BUCK_VBUCK6_EN_BIT		6
 23#define MT6363_RG_BUCK_VBUCK7_EN_BIT		7
 24#define MT6363_RG_BUCK1_EN_ADDR			0x213
 25#define MT6363_RG_BUCK_VS1_EN_BIT		0
 26#define MT6363_RG_BUCK_VS3_EN_BIT		1
 27#define MT6363_RG_LDO_VSRAM_DIGRF_EN_BIT	4
 28#define MT6363_RG_LDO_VSRAM_MDFE_EN_BIT		5
 29#define MT6363_RG_LDO_VSRAM_MODEM_EN_BIT	6
 30#define MT6363_RG_BUCK0_LP_ADDR			0x216
 31#define MT6363_RG_BUCK_VS2_LP_BIT		0
 32#define MT6363_RG_BUCK_VBUCK1_LP_BIT		1
 33#define MT6363_RG_BUCK_VBUCK2_LP_BIT		2
 34#define MT6363_RG_BUCK_VBUCK3_LP_BIT		3
 35#define MT6363_RG_BUCK_VBUCK4_LP_BIT		4
 36#define MT6363_RG_BUCK_VBUCK5_LP_BIT		5
 37#define MT6363_RG_BUCK_VBUCK6_LP_BIT		6
 38#define MT6363_RG_BUCK_VBUCK7_LP_BIT		7
 39#define MT6363_RG_BUCK1_LP_ADDR			0x219
 40#define MT6363_RG_BUCK_VS1_LP_BIT		0
 41#define MT6363_RG_BUCK_VS3_LP_BIT		1
 42#define MT6363_RG_LDO_VSRAM_DIGRF_LP_BIT	4
 43#define MT6363_RG_LDO_VSRAM_MDFE_LP_BIT		5
 44#define MT6363_RG_LDO_VSRAM_MODEM_LP_BIT	6
 45#define MT6363_RG_BUCK_VS2_VOSEL_ADDR		0x21c
 46#define MT6363_RG_BUCK_VS2_VOSEL_MASK		GENMASK(7, 0)
 47#define MT6363_RG_BUCK_VBUCK1_VOSEL_ADDR	0x21d
 48#define MT6363_RG_BUCK_VBUCK1_VOSEL_MASK	GENMASK(7, 0)
 49#define MT6363_RG_BUCK_VBUCK2_VOSEL_ADDR	0x21e
 50#define MT6363_RG_BUCK_VBUCK2_VOSEL_MASK	GENMASK(7, 0)
 51#define MT6363_RG_BUCK_VBUCK3_VOSEL_ADDR	0x21f
 52#define MT6363_RG_BUCK_VBUCK3_VOSEL_MASK	GENMASK(7, 0)
 53#define MT6363_RG_BUCK_VBUCK4_VOSEL_ADDR	0x220
 54#define MT6363_RG_BUCK_VBUCK4_VOSEL_MASK	GENMASK(7, 0)
 55#define MT6363_RG_BUCK_VBUCK5_VOSEL_ADDR	0x221
 56#define MT6363_RG_BUCK_VBUCK5_VOSEL_MASK	GENMASK(7, 0)
 57#define MT6363_RG_BUCK_VBUCK6_VOSEL_ADDR	0x222
 58#define MT6363_RG_BUCK_VBUCK6_VOSEL_MASK	GENMASK(7, 0)
 59#define MT6363_RG_BUCK_VBUCK7_VOSEL_ADDR	0x223
 60#define MT6363_RG_BUCK_VBUCK7_VOSEL_MASK	GENMASK(7, 0)
 61#define MT6363_RG_BUCK_VS1_VOSEL_ADDR		0x224
 62#define MT6363_RG_BUCK_VS1_VOSEL_MASK		GENMASK(7, 0)
 63#define MT6363_RG_BUCK_VS3_VOSEL_ADDR		0x225
 64#define MT6363_RG_BUCK_VS3_VOSEL_MASK		GENMASK(7, 0)
 65#define MT6363_RG_LDO_VSRAM_DIGRF_VOSEL_ADDR	0x228
 66#define MT6363_RG_LDO_VSRAM_DIGRF_VOSEL_MASK	GENMASK(6, 0)
 67#define MT6363_RG_LDO_VSRAM_MDFE_VOSEL_ADDR	0x229
 68#define MT6363_RG_LDO_VSRAM_MDFE_VOSEL_MASK	GENMASK(6, 0)
 69#define MT6363_RG_LDO_VSRAM_MODEM_VOSEL_ADDR	0x22a
 70#define MT6363_RG_LDO_VSRAM_MODEM_VOSEL_MASK	GENMASK(6, 0)
 71#define MT6363_BUCK_TOP_KEY_PROT_LO		0x13fa
 72#define MT6363_BUCK_VS2_WDTDBG_VOSEL_ADDR	0x13fc
 73#define MT6363_BUCK_VBUCK1_WDTDBG_VOSEL_ADDR	0x13fd
 74#define MT6363_BUCK_VBUCK2_WDTDBG_VOSEL_ADDR	0x13fe
 75#define MT6363_BUCK_VBUCK3_WDTDBG_VOSEL_ADDR	0x13ff
 76#define MT6363_BUCK_VBUCK4_WDTDBG_VOSEL_ADDR	0x1400
 77#define MT6363_BUCK_VBUCK5_WDTDBG_VOSEL_ADDR	0x1401
 78#define MT6363_BUCK_VBUCK6_WDTDBG_VOSEL_ADDR	0x1402
 79#define MT6363_BUCK_VBUCK7_WDTDBG_VOSEL_ADDR	0x1403
 80#define MT6363_BUCK_VS1_WDTDBG_VOSEL_ADDR	0x1404
 81#define MT6363_BUCK_VS3_WDTDBG_VOSEL_ADDR	0x1405
 82#define MT6363_RG_BUCK_EFUSE_RSV1		0x1417
 83#define MT6363_RG_BUCK_EFUSE_RSV1_MASK		GENMASK(7, 4)
 84#define MT6363_BUCK_VS2_OP_EN_0			0x145d
 85#define MT6363_BUCK_VS2_HW_LP_MODE		0x1468
 86#define MT6363_BUCK_VBUCK1_OP_EN_0		0x14dd
 87#define MT6363_BUCK_VBUCK1_HW_LP_MODE		0x14e8
 88#define MT6363_RG_BUCK_VBUCK1_SSHUB_EN_ADDR	0x14ea
 89#define MT6363_RG_BUCK_VBUCK1_SSHUB_VOSEL_ADDR	0x14eb
 90#define MT6363_RG_BUCK_VBUCK1_SSHUB_VOSEL_MASK	GENMASK(7, 0)
 91#define MT6363_BUCK_VBUCK2_OP_EN_0		0x155d
 92#define MT6363_BUCK_VBUCK2_HW_LP_MODE		0x1568
 93#define MT6363_RG_BUCK_VBUCK2_SSHUB_EN_ADDR	0x156a
 94#define MT6363_RG_BUCK_VBUCK2_SSHUB_VOSEL_ADDR	0x156b
 95#define MT6363_RG_BUCK_VBUCK2_SSHUB_VOSEL_MASK	GENMASK(7, 0)
 96#define MT6363_BUCK_VBUCK3_OP_EN_0		0x15dd
 97#define MT6363_BUCK_VBUCK3_HW_LP_MODE		0x15e8
 98#define MT6363_BUCK_VBUCK4_OP_EN_0		0x165d
 99#define MT6363_BUCK_VBUCK4_HW_LP_MODE		0x1668
100#define MT6363_RG_BUCK_VBUCK4_SSHUB_EN_ADDR	0x166a
101#define MT6363_RG_BUCK_VBUCK4_SSHUB_VOSEL_ADDR	0x166b
102#define MT6363_RG_BUCK_VBUCK4_SSHUB_VOSEL_MASK	GENMASK(7, 0)
103#define MT6363_BUCK_VBUCK5_OP_EN_0		0x16dd
104#define MT6363_BUCK_VBUCK5_HW_LP_MODE		0x16e8
105#define MT6363_BUCK_VBUCK6_OP_EN_0		0x175d
106#define MT6363_BUCK_VBUCK6_HW_LP_MODE		0x1768
107#define MT6363_BUCK_VBUCK7_OP_EN_0		0x17dd
108#define MT6363_BUCK_VBUCK7_HW_LP_MODE		0x17e8
109#define MT6363_BUCK_VS1_OP_EN_0			0x185d
110#define MT6363_BUCK_VS1_HW_LP_MODE		0x1868
111#define MT6363_BUCK_VS3_OP_EN_0			0x18dd
112#define MT6363_BUCK_VS3_HW_LP_MODE		0x18e8
113#define MT6363_RG_VS1_FCCM_ADDR			0x1964
114#define MT6363_RG_VS1_FCCM_BIT			0
115#define MT6363_RG_VS3_FCCM_ADDR			0x1973
116#define MT6363_RG_VS3_FCCM_BIT			0
117#define MT6363_RG_BUCK0_FCCM_ADDR		0x1a02
118#define MT6363_RG_VBUCK1_FCCM_BIT		0
119#define MT6363_RG_VBUCK2_FCCM_BIT		1
120#define MT6363_RG_VBUCK3_FCCM_BIT		2
121#define MT6363_RG_VS2_FCCM_BIT			3
122#define MT6363_RG_BUCK0_1_FCCM_ADDR		0x1a82
123#define MT6363_RG_VBUCK4_FCCM_BIT		0
124#define MT6363_RG_VBUCK5_FCCM_BIT		1
125#define MT6363_RG_VBUCK6_FCCM_BIT		2
126#define MT6363_RG_VBUCK7_FCCM_BIT		3
127#define MT6363_RG_VCN13_VOSEL_ADDR		0x1b0f
128#define MT6363_RG_VCN13_VOSEL_MASK		GENMASK(3, 0)
129#define MT6363_RG_VEMC_VOSEL_ADDR		0x1b10
130#define MT6363_RG_VEMC_VOSEL_MASK		GENMASK(3, 0)
131#define MT6363_RG_VEMC_VOSEL_1_MASK		GENMASK(7, 4)
132#define MT6363_RG_LDO_VSRAM_CPUB_VOSEL_ADDR	0x1b14
133#define MT6363_RG_LDO_VSRAM_CPUB_VOSEL_MASK	GENMASK(6, 0)
134#define MT6363_RG_LDO_VSRAM_CPUM_VOSEL_ADDR	0x1b15
135#define MT6363_RG_LDO_VSRAM_CPUM_VOSEL_MASK	GENMASK(6, 0)
136#define MT6363_RG_LDO_VSRAM_CPUL_VOSEL_ADDR	0x1b16
137#define MT6363_RG_LDO_VSRAM_CPUL_VOSEL_MASK	GENMASK(6, 0)
138#define MT6363_RG_LDO_VSRAM_APU_VOSEL_ADDR	0x1b17
139#define MT6363_RG_LDO_VSRAM_APU_VOSEL_MASK	GENMASK(6, 0)
140#define MT6363_RG_VEMC_VOCAL_ADDR		0x1b1b
141#define MT6363_RG_VEMC_VOCAL_MASK		GENMASK(3, 0)
142#define MT6363_RG_LDO_VCN15_ADDR		0x1b57
143#define MT6363_RG_LDO_VCN15_EN_BIT		0
144#define MT6363_RG_LDO_VCN15_LP_BIT		1
145#define MT6363_LDO_VCN15_HW_LP_MODE		0x1b5b
146#define MT6363_LDO_VCN15_OP_EN0			0x1b5c
147#define MT6363_RG_LDO_VRF09_ADDR		0x1b65
148#define MT6363_RG_LDO_VRF09_EN_BIT		0
149#define MT6363_RG_LDO_VRF09_LP_BIT		1
150#define MT6363_LDO_VRF09_HW_LP_MODE		0x1b69
151#define MT6363_LDO_VRF09_OP_EN0			0x1b6a
152#define MT6363_RG_LDO_VRF12_ADDR		0x1b73
153#define MT6363_RG_LDO_VRF12_EN_BIT		0
154#define MT6363_RG_LDO_VRF12_LP_BIT		1
155#define MT6363_LDO_VRF12_HW_LP_MODE		0x1b77
156#define MT6363_LDO_VRF12_OP_EN0			0x1b78
157#define MT6363_RG_LDO_VRF13_ADDR		0x1b81
158#define MT6363_RG_LDO_VRF13_EN_BIT		0
159#define MT6363_RG_LDO_VRF13_LP_BIT		1
160#define MT6363_LDO_VRF13_HW_LP_MODE		0x1b85
161#define MT6363_LDO_VRF13_OP_EN0			0x1b86
162#define MT6363_RG_LDO_VRF18_ADDR		0x1b8f
163#define MT6363_RG_LDO_VRF18_EN_BIT		0
164#define MT6363_RG_LDO_VRF18_LP_BIT		1
165#define MT6363_LDO_VRF18_HW_LP_MODE		0x1b93
166#define MT6363_LDO_VRF18_OP_EN0			0x1b94
167#define MT6363_RG_LDO_VRFIO18_ADDR		0x1b9d
168#define MT6363_RG_LDO_VRFIO18_EN_BIT		0
169#define MT6363_RG_LDO_VRFIO18_LP_BIT		1
170#define MT6363_LDO_VRFIO18_HW_LP_MODE		0x1ba1
171#define MT6363_LDO_VRFIO18_OP_EN0		0x1ba2
172#define MT6363_RG_LDO_VTREF18_ADDR		0x1bd7
173#define MT6363_RG_LDO_VTREF18_EN_BIT		0
174#define MT6363_RG_LDO_VTREF18_LP_BIT		1
175#define MT6363_LDO_VTREF18_HW_LP_MODE		0x1bdb
176#define MT6363_LDO_VTREF18_OP_EN0		0x1bdc
177#define MT6363_RG_LDO_VAUX18_ADDR		0x1be5
178#define MT6363_RG_LDO_VAUX18_EN_BIT		0
179#define MT6363_RG_LDO_VAUX18_LP_BIT		1
180#define MT6363_LDO_VAUX18_HW_LP_MODE		0x1be9
181#define MT6363_LDO_VAUX18_OP_EN0		0x1bea
182#define MT6363_RG_LDO_VEMC_ADDR			0x1bf3
183#define MT6363_RG_LDO_VEMC_EN_BIT		0
184#define MT6363_RG_LDO_VEMC_LP_BIT		1
185#define MT6363_LDO_VEMC_HW_LP_MODE		0x1bf7
186#define MT6363_LDO_VEMC_OP_EN0			0x1bf8
187#define MT6363_RG_LDO_VUFS12_ADDR		0x1c01
188#define MT6363_RG_LDO_VUFS12_EN_BIT		0
189#define MT6363_RG_LDO_VUFS12_LP_BIT		1
190#define MT6363_LDO_VUFS12_HW_LP_MODE		0x1c05
191#define MT6363_LDO_VUFS12_OP_EN0		0x1c06
192#define MT6363_RG_LDO_VUFS18_ADDR		0x1c0f
193#define MT6363_RG_LDO_VUFS18_EN_BIT		0
194#define MT6363_RG_LDO_VUFS18_LP_BIT		1
195#define MT6363_LDO_VUFS18_HW_LP_MODE		0x1c13
196#define MT6363_LDO_VUFS18_OP_EN0		0x1c14
197#define MT6363_RG_LDO_VIO18_ADDR		0x1c1d
198#define MT6363_RG_LDO_VIO18_EN_BIT		0
199#define MT6363_RG_LDO_VIO18_LP_BIT		1
200#define MT6363_LDO_VIO18_HW_LP_MODE		0x1c21
201#define MT6363_LDO_VIO18_OP_EN0			0x1c22
202#define MT6363_RG_LDO_VIO075_ADDR		0x1c57
203#define MT6363_RG_LDO_VIO075_EN_BIT		0
204#define MT6363_RG_LDO_VIO075_LP_BIT		1
205#define MT6363_LDO_VIO075_HW_LP_MODE		0x1c5b
206#define MT6363_LDO_VIO075_OP_EN0		0x1c5c
207#define MT6363_RG_LDO_VA12_1_ADDR		0x1c65
208#define MT6363_RG_LDO_VA12_1_EN_BIT		0
209#define MT6363_RG_LDO_VA12_1_LP_BIT		1
210#define MT6363_LDO_VA12_1_HW_LP_MODE		0x1c69
211#define MT6363_LDO_VA12_1_OP_EN0		0x1c6a
212#define MT6363_RG_LDO_VA12_2_ADDR		0x1c73
213#define MT6363_RG_LDO_VA12_2_EN_BIT		0
214#define MT6363_RG_LDO_VA12_2_LP_BIT		1
215#define MT6363_LDO_VA12_2_HW_LP_MODE		0x1c77
216#define MT6363_LDO_VA12_2_OP_EN0		0x1c78
217#define MT6363_RG_LDO_VA15_ADDR			0x1c81
218#define MT6363_RG_LDO_VA15_EN_BIT		0
219#define MT6363_RG_LDO_VA15_LP_BIT		1
220#define MT6363_LDO_VA15_HW_LP_MODE		0x1c85
221#define MT6363_LDO_VA15_OP_EN0			0x1c86
222#define MT6363_RG_LDO_VM18_ADDR			0x1c8f
223#define MT6363_RG_LDO_VM18_EN_BIT		0
224#define MT6363_RG_LDO_VM18_LP_BIT		1
225#define MT6363_LDO_VM18_HW_LP_MODE		0x1c93
226#define MT6363_LDO_VM18_OP_EN0			0x1c94
227#define MT6363_RG_LDO_VCN13_ADDR		0x1cd7
228#define MT6363_RG_LDO_VCN13_EN_BIT		0
229#define MT6363_RG_LDO_VCN13_LP_BIT		1
230#define MT6363_LDO_VCN13_HW_LP_MODE		0x1cdb
231#define MT6363_LDO_VCN13_OP_EN0			0x1ce4
232#define MT6363_LDO_VSRAM_DIGRF_HW_LP_MODE	0x1cf1
233#define MT6363_LDO_VSRAM_DIGRF_OP_EN0		0x1cfa
234#define MT6363_LDO_VSRAM_MDFE_HW_LP_MODE	0x1d5b
235#define MT6363_LDO_VSRAM_MDFE_OP_EN0		0x1d64
236#define MT6363_LDO_VSRAM_MODEM_HW_LP_MODE	0x1d76
237#define MT6363_LDO_VSRAM_MODEM_OP_EN0		0x1d7f
238#define MT6363_RG_LDO_VSRAM_CPUB_ADDR		0x1dd7
239#define MT6363_RG_LDO_VSRAM_CPUB_EN_BIT		0
240#define MT6363_RG_LDO_VSRAM_CPUB_LP_BIT		1
241#define MT6363_LDO_VSRAM_CPUB_HW_LP_MODE	0x1ddb
242#define MT6363_LDO_VSRAM_CPUB_OP_EN0		0x1de4
243#define MT6363_RG_LDO_VSRAM_CPUM_ADDR		0x1ded
244#define MT6363_RG_LDO_VSRAM_CPUM_EN_BIT		0
245#define MT6363_RG_LDO_VSRAM_CPUM_LP_BIT		1
246#define MT6363_LDO_VSRAM_CPUM_HW_LP_MODE	0x1df1
247#define MT6363_LDO_VSRAM_CPUM_OP_EN0		0x1dfa
248#define MT6363_RG_LDO_VSRAM_CPUL_ADDR		0x1e57
249#define MT6363_RG_LDO_VSRAM_CPUL_EN_BIT		0
250#define MT6363_RG_LDO_VSRAM_CPUL_LP_BIT		1
251#define MT6363_LDO_VSRAM_CPUL_HW_LP_MODE	0x1e5b
252#define MT6363_LDO_VSRAM_CPUL_OP_EN0		0x1e64
253#define MT6363_RG_LDO_VSRAM_APU_ADDR		0x1e6d
254#define MT6363_RG_LDO_VSRAM_APU_EN_BIT		0
255#define MT6363_RG_LDO_VSRAM_APU_LP_BIT		1
256#define MT6363_LDO_VSRAM_APU_HW_LP_MODE		0x1e71
257#define MT6363_LDO_VSRAM_APU_OP_EN0		0x1e7a
258#define MT6363_RG_VTREF18_VOCAL_ADDR		0x1ed8
259#define MT6363_RG_VTREF18_VOCAL_MASK		GENMASK(3, 0)
260#define MT6363_RG_VTREF18_VOSEL_ADDR		0x1ed9
261#define MT6363_RG_VTREF18_VOSEL_MASK		GENMASK(3, 0)
262#define MT6363_RG_VAUX18_VOCAL_ADDR		0x1edc
263#define MT6363_RG_VAUX18_VOCAL_MASK		GENMASK(3, 0)
264#define MT6363_RG_VAUX18_VOSEL_ADDR		0x1edd
265#define MT6363_RG_VAUX18_VOSEL_MASK		GENMASK(3, 0)
266#define MT6363_RG_VCN15_VOCAL_ADDR		0x1ee3
267#define MT6363_RG_VCN15_VOCAL_MASK		GENMASK(3, 0)
268#define MT6363_RG_VCN15_VOSEL_ADDR		0x1ee4
269#define MT6363_RG_VCN15_VOSEL_MASK		GENMASK(3, 0)
270#define MT6363_RG_VUFS18_VOCAL_ADDR		0x1ee7
271#define MT6363_RG_VUFS18_VOCAL_MASK		GENMASK(3, 0)
272#define MT6363_RG_VUFS18_VOSEL_ADDR		0x1ee8
273#define MT6363_RG_VUFS18_VOSEL_MASK		GENMASK(3, 0)
274#define MT6363_RG_VIO18_VOCAL_ADDR		0x1eeb
275#define MT6363_RG_VIO18_VOCAL_MASK		GENMASK(3, 0)
276#define MT6363_RG_VIO18_VOSEL_ADDR		0x1eec
277#define MT6363_RG_VIO18_VOSEL_MASK		GENMASK(3, 0)
278#define MT6363_RG_VM18_VOCAL_ADDR		0x1eef
279#define MT6363_RG_VM18_VOCAL_MASK		GENMASK(3, 0)
280#define MT6363_RG_VM18_VOSEL_ADDR		0x1ef0
281#define MT6363_RG_VM18_VOSEL_MASK		GENMASK(3, 0)
282#define MT6363_RG_VA15_VOCAL_ADDR		0x1ef3
283#define MT6363_RG_VA15_VOCAL_MASK		GENMASK(3, 0)
284#define MT6363_RG_VA15_VOSEL_ADDR		0x1ef4
285#define MT6363_RG_VA15_VOSEL_MASK		GENMASK(3, 0)
286#define MT6363_RG_VRF18_VOCAL_ADDR		0x1ef7
287#define MT6363_RG_VRF18_VOCAL_MASK		GENMASK(3, 0)
288#define MT6363_RG_VRF18_VOSEL_ADDR		0x1ef8
289#define MT6363_RG_VRF18_VOSEL_MASK		GENMASK(3, 0)
290#define MT6363_RG_VRFIO18_VOCAL_ADDR		0x1efb
291#define MT6363_RG_VRFIO18_VOCAL_MASK		GENMASK(3, 0)
292#define MT6363_RG_VRFIO18_VOSEL_ADDR		0x1efc
293#define MT6363_RG_VRFIO18_VOSEL_MASK		GENMASK(3, 0)
294#define MT6363_RG_VIO075_VOCFG_ADDR		0x1f01
295#define MT6363_RG_VIO075_VOCAL_ADDR		MT6363_RG_VIO075_VOCFG_ADDR
296#define MT6363_RG_VIO075_VOCAL_MASK		GENMASK(3, 0)
297#define MT6363_RG_VIO075_VOSEL_ADDR		MT6363_RG_VIO075_VOCFG_ADDR
298#define MT6363_RG_VIO075_VOSEL_MASK		GENMASK(6, 4)
299#define MT6363_RG_VCN13_VOCAL_ADDR		0x1f58
300#define MT6363_RG_VCN13_VOCAL_MASK		GENMASK(3, 0)
301#define MT6363_RG_VUFS12_VOCAL_ADDR		0x1f61
302#define MT6363_RG_VUFS12_VOCAL_MASK		GENMASK(3, 0)
303#define MT6363_RG_VUFS12_VOSEL_ADDR		0x1f62
304#define MT6363_RG_VUFS12_VOSEL_MASK		GENMASK(3, 0)
305#define MT6363_RG_VA12_1_VOCAL_ADDR		0x1f65
306#define MT6363_RG_VA12_1_VOCAL_MASK		GENMASK(3, 0)
307#define MT6363_RG_VA12_1_VOSEL_ADDR		0x1f66
308#define MT6363_RG_VA12_1_VOSEL_MASK		GENMASK(3, 0)
309#define MT6363_RG_VA12_2_VOCAL_ADDR		0x1f69
310#define MT6363_RG_VA12_2_VOCAL_MASK		GENMASK(3, 0)
311#define MT6363_RG_VA12_2_VOSEL_ADDR		0x1f6a
312#define MT6363_RG_VA12_2_VOSEL_MASK		GENMASK(3, 0)
313#define MT6363_RG_VRF12_VOCAL_ADDR		0x1f6d
314#define MT6363_RG_VRF12_VOCAL_MASK		GENMASK(3, 0)
315#define MT6363_RG_VRF12_VOSEL_ADDR		0x1f6e
316#define MT6363_RG_VRF12_VOSEL_MASK		GENMASK(3, 0)
317#define MT6363_RG_VRF13_VOCAL_ADDR		0x1f71
318#define MT6363_RG_VRF13_VOCAL_MASK		GENMASK(3, 0)
319#define MT6363_RG_VRF13_VOSEL_ADDR		0x1f72
320#define MT6363_RG_VRF13_VOSEL_MASK		GENMASK(3, 0)
321#define MT6363_RG_VRF09_VOCAL_ADDR		0x1f78
322#define MT6363_RG_VRF09_VOCAL_MASK		GENMASK(3, 0)
323#define MT6363_RG_VRF09_VOSEL_ADDR		0x1f79
324#define MT6363_RG_VRF09_VOSEL_MASK		GENMASK(3, 0)
325#define MT6363_ISINK_EN_CTRL0			0x21db
326#define MT6363_ISINK_CTRL0_MASK			GENMASK(7, 0)
327#define MT6363_ISINK_EN_CTRL1			0x21dc
328#define MT6363_ISINK_CTRL1_MASK			GENMASK(7, 4)
329
330#endif /* __LINUX_REGULATOR_MT6363_H */