common_hsi.h

   1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
   2/* QLogic qed NIC Driver
   3 * Copyright (c) 2015-2016  QLogic Corporation
   4 * Copyright (c) 2019-2021 Marvell International Ltd.
   5 */
   6
   7#ifndef _COMMON_HSI_H
   8#define _COMMON_HSI_H
   9
  10#include <linux/types.h>
  11#include <asm/byteorder.h>
  12#include <linux/bitops.h>
  13#include <linux/slab.h>
  14
  15/* dma_addr_t manip */
  16#define PTR_LO(x)		((u32)(((uintptr_t)(x)) & 0xffffffff))
  17#define PTR_HI(x)		((u32)((((uintptr_t)(x)) >> 16) >> 16))
  18#define DMA_LO_LE(x)		cpu_to_le32(lower_32_bits(x))
  19#define DMA_HI_LE(x)		cpu_to_le32(upper_32_bits(x))
  20#define DMA_REGPAIR_LE(x, val)	do { \
  21					(x).hi = DMA_HI_LE((val)); \
  22					(x).lo = DMA_LO_LE((val)); \
  23				} while (0)
  24
  25#define HILO_GEN(hi, lo, type)		((((type)(hi)) << 32) + (lo))
  26#define HILO_64(hi, lo) \
  27	HILO_GEN(le32_to_cpu(hi), le32_to_cpu(lo), u64)
  28#define HILO_64_REGPAIR(regpair) ({ \
  29	typeof(regpair) __regpair = (regpair); \
  30	HILO_64(__regpair.hi, __regpair.lo); })
  31#define HILO_DMA_REGPAIR(regpair)	((dma_addr_t)HILO_64_REGPAIR(regpair))
  32
  33#ifndef __COMMON_HSI__
  34#define __COMMON_HSI__
  35
  36/********************************/
  37/* PROTOCOL COMMON FW CONSTANTS */
  38/********************************/
  39
  40#define X_FINAL_CLEANUP_AGG_INT			1
  41
  42#define EVENT_RING_PAGE_SIZE_BYTES		4096
  43
  44#define NUM_OF_GLOBAL_QUEUES			128
  45#define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE	64
  46
  47#define ISCSI_CDU_TASK_SEG_TYPE			0
  48#define FCOE_CDU_TASK_SEG_TYPE			0
  49#define RDMA_CDU_TASK_SEG_TYPE			1
  50#define ETH_CDU_TASK_SEG_TYPE			2
  51
  52#define FW_ASSERT_GENERAL_ATTN_IDX		32
  53
  54/* Queue Zone sizes in bytes */
  55#define TSTORM_QZONE_SIZE	8
  56#define MSTORM_QZONE_SIZE	16
  57#define USTORM_QZONE_SIZE	8
  58#define XSTORM_QZONE_SIZE	8
  59#define YSTORM_QZONE_SIZE	0
  60#define PSTORM_QZONE_SIZE	0
  61
  62#define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG		7
  63#define ETH_MAX_RXQ_VF_DEFAULT 16
  64#define ETH_MAX_RXQ_VF_DOUBLE 48
  65#define ETH_MAX_RXQ_VF_QUAD 112
  66
  67#define ETH_RGSRC_CTX_SIZE			6
  68#define ETH_TGSRC_CTX_SIZE			6
  69
  70/********************************/
  71/* CORE (LIGHT L2) FW CONSTANTS */
  72/********************************/
  73
  74#define CORE_LL2_MAX_RAMROD_PER_CON	8
  75#define CORE_LL2_TX_BD_PAGE_SIZE_BYTES	4096
  76#define CORE_LL2_RX_BD_PAGE_SIZE_BYTES	4096
  77#define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES	4096
  78#define CORE_LL2_RX_NUM_NEXT_PAGE_BDS	1
  79
  80#define CORE_LL2_TX_MAX_BDS_PER_PACKET	12
  81
  82#define CORE_SPQE_PAGE_SIZE_BYTES	4096
  83
  84/* Number of LL2 RAM based queues */
  85#define MAX_NUM_LL2_RX_RAM_QUEUES 32
  86
  87/* Number of LL2 context based queues */
  88#define MAX_NUM_LL2_RX_CTX_QUEUES 208
  89#define MAX_NUM_LL2_RX_QUEUES \
  90	(MAX_NUM_LL2_RX_RAM_QUEUES + MAX_NUM_LL2_RX_CTX_QUEUES)
  91
  92#define MAX_NUM_LL2_TX_STATS_COUNTERS  48
  93
  94#define FW_MAJOR_VERSION	8
  95#define FW_MINOR_VERSION	59
  96#define FW_REVISION_VERSION	1
  97#define FW_ENGINEERING_VERSION	0
  98
  99/***********************/
 100/* COMMON HW CONSTANTS */
 101/***********************/
 102
 103/* PCI functions */
 104#define MAX_NUM_PORTS_K2	(4)
 105#define MAX_NUM_PORTS_BB	(2)
 106#define MAX_NUM_PORTS		(MAX_NUM_PORTS_K2)
 107
 108#define MAX_NUM_PFS_K2		(16)
 109#define MAX_NUM_PFS_BB		(8)
 110#define MAX_NUM_PFS		(MAX_NUM_PFS_K2)
 111#define MAX_NUM_OF_PFS_IN_CHIP	(16) /* On both engines */
 112
 113#define MAX_NUM_VFS_K2	(192)
 114#define MAX_NUM_VFS_BB	(120)
 115#define MAX_NUM_VFS	(MAX_NUM_VFS_K2)
 116
 117#define MAX_NUM_FUNCTIONS_BB	(MAX_NUM_PFS_BB + MAX_NUM_VFS_BB)
 118#define MAX_NUM_FUNCTIONS_K2    (MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2)
 119
 120#define MAX_FUNCTION_NUMBER_BB	(MAX_NUM_PFS + MAX_NUM_VFS_BB)
 121#define MAX_FUNCTION_NUMBER_K2  (MAX_NUM_PFS + MAX_NUM_VFS_K2)
 122#define MAX_NUM_FUNCTIONS	(MAX_FUNCTION_NUMBER_K2)
 123
 124#define MAX_NUM_VPORTS_K2	(208)
 125#define MAX_NUM_VPORTS_BB	(160)
 126#define MAX_NUM_VPORTS		(MAX_NUM_VPORTS_K2)
 127
 128#define MAX_NUM_L2_QUEUES_K2	(320)
 129#define MAX_NUM_L2_QUEUES_BB	(256)
 130#define MAX_NUM_L2_QUEUES	(MAX_NUM_L2_QUEUES_K2)
 131
 132/* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */
 133#define NUM_PHYS_TCS_4PORT_K2	(4)
 134#define NUM_OF_PHYS_TCS		(8)
 135#define PURE_LB_TC		NUM_OF_PHYS_TCS
 136#define NUM_TCS_4PORT_K2	(NUM_PHYS_TCS_4PORT_K2 + 1)
 137#define NUM_OF_TCS		(NUM_OF_PHYS_TCS + 1)
 138
 139/* CIDs */
 140#define NUM_OF_CONNECTION_TYPES	(8)
 141#define NUM_OF_LCIDS			(320)
 142#define NUM_OF_LTIDS			(320)
 143
 144/* Global PXP windows (GTT) */
 145#define NUM_OF_GTT		19
 146#define GTT_DWORD_SIZE_BITS	10
 147#define GTT_BYTE_SIZE_BITS	(GTT_DWORD_SIZE_BITS + 2)
 148#define GTT_DWORD_SIZE		BIT(GTT_DWORD_SIZE_BITS)
 149
 150/* Tools Version */
 151#define TOOLS_VERSION 11
 152
 153/*****************/
 154/* CDU CONSTANTS */
 155/*****************/
 156
 157#define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT			(17)
 158#define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK			(0x1ffff)
 159
 160#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT		(12)
 161#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK		(0xfff)
 162
 163#define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT			(0)
 164#define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT	(1)
 165#define CDU_CONTEXT_VALIDATION_CFG_USE_TYPE			(2)
 166#define CDU_CONTEXT_VALIDATION_CFG_USE_REGION			(3)
 167#define CDU_CONTEXT_VALIDATION_CFG_USE_CID			(4)
 168#define CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE			(5)
 169#define CDU_CONTEXT_VALIDATION_DEFAULT_CFG			(0x3d)
 170
 171/*****************/
 172/* DQ CONSTANTS  */
 173/*****************/
 174
 175/* DEMS */
 176#define DQ_DEMS_LEGACY			0
 177#define DQ_DEMS_TOE_MORE_TO_SEND	3
 178#define DQ_DEMS_TOE_LOCAL_ADV_WND	4
 179#define DQ_DEMS_ROCE_CQ_CONS		7
 180
 181/* XCM agg val selection (HW) */
 182#define DQ_XCM_AGG_VAL_SEL_WORD2	0
 183#define DQ_XCM_AGG_VAL_SEL_WORD3	1
 184#define DQ_XCM_AGG_VAL_SEL_WORD4	2
 185#define DQ_XCM_AGG_VAL_SEL_WORD5	3
 186#define DQ_XCM_AGG_VAL_SEL_REG3		4
 187#define DQ_XCM_AGG_VAL_SEL_REG4		5
 188#define DQ_XCM_AGG_VAL_SEL_REG5		6
 189#define DQ_XCM_AGG_VAL_SEL_REG6		7
 190
 191/* XCM agg val selection (FW) */
 192#define	DQ_XCM_CORE_TX_BD_CONS_CMD		DQ_XCM_AGG_VAL_SEL_WORD3
 193#define	DQ_XCM_CORE_TX_BD_PROD_CMD		DQ_XCM_AGG_VAL_SEL_WORD4
 194#define	DQ_XCM_CORE_SPQ_PROD_CMD		DQ_XCM_AGG_VAL_SEL_WORD4
 195#define	DQ_XCM_ETH_EDPM_NUM_BDS_CMD		DQ_XCM_AGG_VAL_SEL_WORD2
 196#define	DQ_XCM_ETH_TX_BD_CONS_CMD		DQ_XCM_AGG_VAL_SEL_WORD3
 197#define	DQ_XCM_ETH_TX_BD_PROD_CMD		DQ_XCM_AGG_VAL_SEL_WORD4
 198#define	DQ_XCM_ETH_GO_TO_BD_CONS_CMD		DQ_XCM_AGG_VAL_SEL_WORD5
 199#define DQ_XCM_FCOE_SQ_CONS_CMD			DQ_XCM_AGG_VAL_SEL_WORD3
 200#define DQ_XCM_FCOE_SQ_PROD_CMD			DQ_XCM_AGG_VAL_SEL_WORD4
 201#define DQ_XCM_FCOE_X_FERQ_PROD_CMD		DQ_XCM_AGG_VAL_SEL_WORD5
 202#define DQ_XCM_ISCSI_SQ_CONS_CMD		DQ_XCM_AGG_VAL_SEL_WORD3
 203#define DQ_XCM_ISCSI_SQ_PROD_CMD		DQ_XCM_AGG_VAL_SEL_WORD4
 204#define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD	DQ_XCM_AGG_VAL_SEL_REG3
 205#define DQ_XCM_ISCSI_EXP_STAT_SN_CMD		DQ_XCM_AGG_VAL_SEL_REG6
 206#define DQ_XCM_ROCE_SQ_PROD_CMD			DQ_XCM_AGG_VAL_SEL_WORD4
 207#define DQ_XCM_TOE_TX_BD_PROD_CMD		DQ_XCM_AGG_VAL_SEL_WORD4
 208#define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD		DQ_XCM_AGG_VAL_SEL_REG3
 209#define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD	DQ_XCM_AGG_VAL_SEL_REG4
 210#define DQ_XCM_ROCE_ACK_EDPM_DORQ_SEQ_CMD	DQ_XCM_AGG_VAL_SEL_WORD5
 211
 212/* UCM agg val selection (HW) */
 213#define	DQ_UCM_AGG_VAL_SEL_WORD0	0
 214#define	DQ_UCM_AGG_VAL_SEL_WORD1	1
 215#define	DQ_UCM_AGG_VAL_SEL_WORD2	2
 216#define	DQ_UCM_AGG_VAL_SEL_WORD3	3
 217#define	DQ_UCM_AGG_VAL_SEL_REG0		4
 218#define	DQ_UCM_AGG_VAL_SEL_REG1		5
 219#define	DQ_UCM_AGG_VAL_SEL_REG2		6
 220#define	DQ_UCM_AGG_VAL_SEL_REG3		7
 221
 222/* UCM agg val selection (FW) */
 223#define DQ_UCM_ETH_PMD_TX_CONS_CMD	DQ_UCM_AGG_VAL_SEL_WORD2
 224#define DQ_UCM_ETH_PMD_RX_CONS_CMD	DQ_UCM_AGG_VAL_SEL_WORD3
 225#define DQ_UCM_ROCE_CQ_CONS_CMD		DQ_UCM_AGG_VAL_SEL_REG0
 226#define DQ_UCM_ROCE_CQ_PROD_CMD		DQ_UCM_AGG_VAL_SEL_REG2
 227
 228/* TCM agg val selection (HW) */
 229#define	DQ_TCM_AGG_VAL_SEL_WORD0	0
 230#define	DQ_TCM_AGG_VAL_SEL_WORD1	1
 231#define	DQ_TCM_AGG_VAL_SEL_WORD2	2
 232#define	DQ_TCM_AGG_VAL_SEL_WORD3	3
 233#define	DQ_TCM_AGG_VAL_SEL_REG1		4
 234#define	DQ_TCM_AGG_VAL_SEL_REG2		5
 235#define	DQ_TCM_AGG_VAL_SEL_REG6		6
 236#define	DQ_TCM_AGG_VAL_SEL_REG9		7
 237
 238/* TCM agg val selection (FW) */
 239#define DQ_TCM_L2B_BD_PROD_CMD \
 240	DQ_TCM_AGG_VAL_SEL_WORD1
 241#define DQ_TCM_ROCE_RQ_PROD_CMD	\
 242	DQ_TCM_AGG_VAL_SEL_WORD0
 243
 244/* XCM agg counter flag selection (HW) */
 245#define	DQ_XCM_AGG_FLG_SHIFT_BIT14	0
 246#define	DQ_XCM_AGG_FLG_SHIFT_BIT15	1
 247#define	DQ_XCM_AGG_FLG_SHIFT_CF12	2
 248#define	DQ_XCM_AGG_FLG_SHIFT_CF13	3
 249#define	DQ_XCM_AGG_FLG_SHIFT_CF18	4
 250#define	DQ_XCM_AGG_FLG_SHIFT_CF19	5
 251#define	DQ_XCM_AGG_FLG_SHIFT_CF22	6
 252#define	DQ_XCM_AGG_FLG_SHIFT_CF23	7
 253
 254/* XCM agg counter flag selection (FW) */
 255#define DQ_XCM_CORE_DQ_CF_CMD			BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
 256#define DQ_XCM_CORE_TERMINATE_CMD		BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
 257#define DQ_XCM_CORE_SLOW_PATH_CMD		BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
 258#define DQ_XCM_ETH_DQ_CF_CMD			BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
 259#define DQ_XCM_ETH_TERMINATE_CMD		BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
 260#define DQ_XCM_ETH_SLOW_PATH_CMD		BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
 261#define DQ_XCM_ETH_TPH_EN_CMD			BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
 262#define DQ_XCM_FCOE_SLOW_PATH_CMD		BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
 263#define DQ_XCM_ISCSI_DQ_FLUSH_CMD		BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
 264#define DQ_XCM_ISCSI_SLOW_PATH_CMD		BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
 265#define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD	BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
 266#define DQ_XCM_TOE_DQ_FLUSH_CMD			BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
 267#define DQ_XCM_TOE_SLOW_PATH_CMD		BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
 268
 269/* UCM agg counter flag selection (HW) */
 270#define	DQ_UCM_AGG_FLG_SHIFT_CF0	0
 271#define	DQ_UCM_AGG_FLG_SHIFT_CF1	1
 272#define	DQ_UCM_AGG_FLG_SHIFT_CF3	2
 273#define	DQ_UCM_AGG_FLG_SHIFT_CF4	3
 274#define	DQ_UCM_AGG_FLG_SHIFT_CF5	4
 275#define	DQ_UCM_AGG_FLG_SHIFT_CF6	5
 276#define	DQ_UCM_AGG_FLG_SHIFT_RULE0EN	6
 277#define	DQ_UCM_AGG_FLG_SHIFT_RULE1EN	7
 278
 279/* UCM agg counter flag selection (FW) */
 280#define DQ_UCM_ETH_PMD_TX_ARM_CMD	BIT(DQ_UCM_AGG_FLG_SHIFT_CF4)
 281#define DQ_UCM_ETH_PMD_RX_ARM_CMD	BIT(DQ_UCM_AGG_FLG_SHIFT_CF5)
 282#define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD	BIT(DQ_UCM_AGG_FLG_SHIFT_CF4)
 283#define DQ_UCM_ROCE_CQ_ARM_CF_CMD	BIT(DQ_UCM_AGG_FLG_SHIFT_CF5)
 284#define DQ_UCM_TOE_TIMER_STOP_ALL_CMD	BIT(DQ_UCM_AGG_FLG_SHIFT_CF3)
 285#define DQ_UCM_TOE_SLOW_PATH_CF_CMD	BIT(DQ_UCM_AGG_FLG_SHIFT_CF4)
 286#define DQ_UCM_TOE_DQ_CF_CMD		BIT(DQ_UCM_AGG_FLG_SHIFT_CF5)
 287
 288/* TCM agg counter flag selection (HW) */
 289#define DQ_TCM_AGG_FLG_SHIFT_CF0	0
 290#define DQ_TCM_AGG_FLG_SHIFT_CF1	1
 291#define DQ_TCM_AGG_FLG_SHIFT_CF2	2
 292#define DQ_TCM_AGG_FLG_SHIFT_CF3	3
 293#define DQ_TCM_AGG_FLG_SHIFT_CF4	4
 294#define DQ_TCM_AGG_FLG_SHIFT_CF5	5
 295#define DQ_TCM_AGG_FLG_SHIFT_CF6	6
 296#define DQ_TCM_AGG_FLG_SHIFT_CF7	7
 297/* TCM agg counter flag selection (FW) */
 298#define DQ_TCM_FCOE_FLUSH_Q0_CMD	BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
 299#define DQ_TCM_FCOE_DUMMY_TIMER_CMD	BIT(DQ_TCM_AGG_FLG_SHIFT_CF2)
 300#define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD	BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
 301#define DQ_TCM_ISCSI_FLUSH_Q0_CMD	BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
 302#define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD	BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
 303#define DQ_TCM_TOE_FLUSH_Q0_CMD		BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
 304#define DQ_TCM_TOE_TIMER_STOP_ALL_CMD	BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
 305#define DQ_TCM_IWARP_POST_RQ_CF_CMD	BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
 306
 307/* PWM address mapping */
 308#define DQ_PWM_OFFSET_DPM_BASE		0x0
 309#define DQ_PWM_OFFSET_DPM_END		0x27
 310#define DQ_PWM_OFFSET_XCM32_24ICID_BASE 0x28
 311#define DQ_PWM_OFFSET_UCM32_24ICID_BASE 0x30
 312#define DQ_PWM_OFFSET_TCM32_24ICID_BASE 0x38
 313#define DQ_PWM_OFFSET_XCM16_BASE	0x40
 314#define DQ_PWM_OFFSET_XCM32_BASE	0x44
 315#define DQ_PWM_OFFSET_UCM16_BASE	0x48
 316#define DQ_PWM_OFFSET_UCM32_BASE	0x4C
 317#define DQ_PWM_OFFSET_UCM16_4		0x50
 318#define DQ_PWM_OFFSET_TCM16_BASE	0x58
 319#define DQ_PWM_OFFSET_TCM32_BASE	0x5C
 320#define DQ_PWM_OFFSET_XCM_FLAGS		0x68
 321#define DQ_PWM_OFFSET_UCM_FLAGS		0x69
 322#define DQ_PWM_OFFSET_TCM_FLAGS		0x6B
 323
 324#define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD		(DQ_PWM_OFFSET_XCM16_BASE + 2)
 325#define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT	(DQ_PWM_OFFSET_UCM32_BASE)
 326#define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT	(DQ_PWM_OFFSET_UCM16_4)
 327#define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT	(DQ_PWM_OFFSET_UCM16_BASE + 2)
 328#define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS	(DQ_PWM_OFFSET_UCM_FLAGS)
 329#define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD		(DQ_PWM_OFFSET_TCM16_BASE + 1)
 330#define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD		(DQ_PWM_OFFSET_TCM16_BASE + 3)
 331
 332/* DQ_DEMS_AGG_VAL_BASE */
 333#define DQ_PWM_OFFSET_TCM_LL2_PROD_UPDATE \
 334	(DQ_PWM_OFFSET_TCM32_BASE + DQ_TCM_AGG_VAL_SEL_REG9 - 4)
 335
 336#define DQ_PWM_OFFSET_XCM_RDMA_24B_ICID_SQ_PROD \
 337	(DQ_PWM_OFFSET_XCM32_24ICID_BASE + 2)
 338#define DQ_PWM_OFFSET_UCM_RDMA_24B_ICID_CQ_CONS_32BIT \
 339	(DQ_PWM_OFFSET_UCM32_24ICID_BASE + 4)
 340#define DQ_PWM_OFFSET_TCM_ROCE_24B_ICID_RQ_PROD \
 341	(DQ_PWM_OFFSET_TCM32_24ICID_BASE + 1)
 342
 343#define	DQ_REGION_SHIFT			(12)
 344
 345/* DPM */
 346#define	DQ_DPM_WQE_BUFF_SIZE		(320)
 347
 348/* Conn type ranges */
 349#define	DQ_CONN_TYPE_RANGE_SHIFT	(4)
 350
 351/*****************/
 352/* QM CONSTANTS  */
 353/*****************/
 354
 355/* Number of TX queues in the QM */
 356#define MAX_QM_TX_QUEUES_K2	512
 357#define MAX_QM_TX_QUEUES_BB	448
 358#define MAX_QM_TX_QUEUES	MAX_QM_TX_QUEUES_K2
 359
 360/* Number of Other queues in the QM */
 361#define MAX_QM_OTHER_QUEUES_BB	64
 362#define MAX_QM_OTHER_QUEUES_K2	128
 363#define MAX_QM_OTHER_QUEUES	MAX_QM_OTHER_QUEUES_K2
 364
 365/* Number of queues in a PF queue group */
 366#define QM_PF_QUEUE_GROUP_SIZE	8
 367
 368/* The size of a single queue element in bytes */
 369#define QM_PQ_ELEMENT_SIZE	4
 370
 371/* Base number of Tx PQs in the CM PQ representation.
 372 * Should be used when storing PQ IDs in CM PQ registers and context.
 373 */
 374#define CM_TX_PQ_BASE		0x200
 375
 376/* Number of global Vport/QCN rate limiters */
 377#define MAX_QM_GLOBAL_RLS	256
 378#define COMMON_MAX_QM_GLOBAL_RLS MAX_QM_GLOBAL_RLS
 379
 380/* QM registers data */
 381#define QM_LINE_CRD_REG_WIDTH		16
 382#define QM_LINE_CRD_REG_SIGN_BIT	BIT((QM_LINE_CRD_REG_WIDTH - 1))
 383#define QM_BYTE_CRD_REG_WIDTH		24
 384#define QM_BYTE_CRD_REG_SIGN_BIT	BIT((QM_BYTE_CRD_REG_WIDTH - 1))
 385#define QM_WFQ_CRD_REG_WIDTH		32
 386#define QM_WFQ_CRD_REG_SIGN_BIT		BIT((QM_WFQ_CRD_REG_WIDTH - 1))
 387#define QM_RL_CRD_REG_WIDTH		32
 388#define QM_RL_CRD_REG_SIGN_BIT		BIT((QM_RL_CRD_REG_WIDTH - 1))
 389
 390/*****************/
 391/* CAU CONSTANTS */
 392/*****************/
 393
 394#define CAU_FSM_ETH_RX  0
 395#define CAU_FSM_ETH_TX  1
 396
 397/* Number of Protocol Indices per Status Block */
 398#define PIS_PER_SB	12
 399#define MAX_PIS_PER_SB	PIS_PER_SB
 400
 401#define CAU_HC_STOPPED_STATE	3
 402#define CAU_HC_DISABLE_STATE	4
 403#define CAU_HC_ENABLE_STATE	0
 404
 405/*****************/
 406/* IGU CONSTANTS */
 407/*****************/
 408
 409#define MAX_SB_PER_PATH_K2	(368)
 410#define MAX_SB_PER_PATH_BB	(288)
 411#define MAX_TOT_SB_PER_PATH \
 412	MAX_SB_PER_PATH_K2
 413
 414#define MAX_SB_PER_PF_MIMD	129
 415#define MAX_SB_PER_PF_SIMD	64
 416#define MAX_SB_PER_VF		64
 417
 418/* Memory addresses on the BAR for the IGU Sub Block */
 419#define IGU_MEM_BASE			0x0000
 420
 421#define IGU_MEM_MSIX_BASE		0x0000
 422#define IGU_MEM_MSIX_UPPER		0x0101
 423#define IGU_MEM_MSIX_RESERVED_UPPER	0x01ff
 424
 425#define IGU_MEM_PBA_MSIX_BASE		0x0200
 426#define IGU_MEM_PBA_MSIX_UPPER		0x0202
 427#define IGU_MEM_PBA_MSIX_RESERVED_UPPER	0x03ff
 428
 429#define IGU_CMD_INT_ACK_BASE		0x0400
 430#define IGU_CMD_INT_ACK_RESERVED_UPPER	0x05ff
 431
 432#define IGU_CMD_ATTN_BIT_UPD_UPPER	0x05f0
 433#define IGU_CMD_ATTN_BIT_SET_UPPER	0x05f1
 434#define IGU_CMD_ATTN_BIT_CLR_UPPER	0x05f2
 435
 436#define IGU_REG_SISR_MDPC_WMASK_UPPER		0x05f3
 437#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER	0x05f4
 438#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER	0x05f5
 439#define IGU_REG_SISR_MDPC_WOMASK_UPPER		0x05f6
 440
 441#define IGU_CMD_PROD_UPD_BASE			0x0600
 442#define IGU_CMD_PROD_UPD_RESERVED_UPPER		0x07ff
 443
 444/*****************/
 445/* PXP CONSTANTS */
 446/*****************/
 447
 448/* Bars for Blocks */
 449#define PXP_BAR_GRC	0
 450#define PXP_BAR_TSDM	0
 451#define PXP_BAR_USDM	0
 452#define PXP_BAR_XSDM	0
 453#define PXP_BAR_MSDM	0
 454#define PXP_BAR_YSDM	0
 455#define PXP_BAR_PSDM	0
 456#define PXP_BAR_IGU	0
 457#define PXP_BAR_DQ	1
 458
 459/* PTT and GTT */
 460#define PXP_PER_PF_ENTRY_SIZE		8
 461#define PXP_NUM_GLOBAL_WINDOWS		243
 462#define PXP_GLOBAL_ENTRY_SIZE		4
 463#define PXP_ADMIN_WINDOW_ALLOWED_LENGTH	4
 464#define PXP_PF_WINDOW_ADMIN_START	0
 465#define PXP_PF_WINDOW_ADMIN_LENGTH	0x1000
 466#define PXP_PF_WINDOW_ADMIN_END		(PXP_PF_WINDOW_ADMIN_START + \
 467					 PXP_PF_WINDOW_ADMIN_LENGTH - 1)
 468#define PXP_PF_WINDOW_ADMIN_PER_PF_START	0
 469#define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH	(PXP_NUM_PF_WINDOWS * \
 470						 PXP_PER_PF_ENTRY_SIZE)
 471#define PXP_PF_WINDOW_ADMIN_PER_PF_END	(PXP_PF_WINDOW_ADMIN_PER_PF_START + \
 472					 PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1)
 473#define PXP_PF_WINDOW_ADMIN_GLOBAL_START	0x200
 474#define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH	(PXP_NUM_GLOBAL_WINDOWS * \
 475						 PXP_GLOBAL_ENTRY_SIZE)
 476#define PXP_PF_WINDOW_ADMIN_GLOBAL_END \
 477		(PXP_PF_WINDOW_ADMIN_GLOBAL_START + \
 478		 PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1)
 479#define PXP_PF_GLOBAL_PRETEND_ADDR	0x1f0
 480#define PXP_PF_ME_OPAQUE_MASK_ADDR	0xf4
 481#define PXP_PF_ME_OPAQUE_ADDR		0x1f8
 482#define PXP_PF_ME_CONCRETE_ADDR		0x1fc
 483
 484#define PXP_NUM_PF_WINDOWS	12
 485#define PXP_EXTERNAL_BAR_PF_WINDOW_START	0x1000
 486#define PXP_EXTERNAL_BAR_PF_WINDOW_NUM		PXP_NUM_PF_WINDOWS
 487#define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE	0x1000
 488#define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \
 489	(PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \
 490	 PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE)
 491#define PXP_EXTERNAL_BAR_PF_WINDOW_END \
 492	(PXP_EXTERNAL_BAR_PF_WINDOW_START + \
 493	 PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1)
 494
 495#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \
 496	(PXP_EXTERNAL_BAR_PF_WINDOW_END + 1)
 497#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM		PXP_NUM_GLOBAL_WINDOWS
 498#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE	0x1000
 499#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \
 500	(PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \
 501	 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE)
 502#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \
 503	(PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \
 504	 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1)
 505
 506/* PF BAR */
 507#define PXP_BAR0_START_GRC		0x0000
 508#define PXP_BAR0_GRC_LENGTH		0x1C00000
 509#define PXP_BAR0_END_GRC		(PXP_BAR0_START_GRC + \
 510					 PXP_BAR0_GRC_LENGTH - 1)
 511
 512#define PXP_BAR0_START_IGU		0x1C00000
 513#define PXP_BAR0_IGU_LENGTH		0x10000
 514#define PXP_BAR0_END_IGU		(PXP_BAR0_START_IGU + \
 515					 PXP_BAR0_IGU_LENGTH - 1)
 516
 517#define PXP_BAR0_START_TSDM		0x1C80000
 518#define PXP_BAR0_SDM_LENGTH		0x40000
 519#define PXP_BAR0_SDM_RESERVED_LENGTH	0x40000
 520#define PXP_BAR0_END_TSDM		(PXP_BAR0_START_TSDM + \
 521					 PXP_BAR0_SDM_LENGTH - 1)
 522
 523#define PXP_BAR0_START_MSDM		0x1D00000
 524#define PXP_BAR0_END_MSDM		(PXP_BAR0_START_MSDM + \
 525					 PXP_BAR0_SDM_LENGTH - 1)
 526
 527#define PXP_BAR0_START_USDM		0x1D80000
 528#define PXP_BAR0_END_USDM		(PXP_BAR0_START_USDM + \
 529					 PXP_BAR0_SDM_LENGTH - 1)
 530
 531#define PXP_BAR0_START_XSDM		0x1E00000
 532#define PXP_BAR0_END_XSDM		(PXP_BAR0_START_XSDM + \
 533					 PXP_BAR0_SDM_LENGTH - 1)
 534
 535#define PXP_BAR0_START_YSDM		0x1E80000
 536#define PXP_BAR0_END_YSDM		(PXP_BAR0_START_YSDM + \
 537					 PXP_BAR0_SDM_LENGTH - 1)
 538
 539#define PXP_BAR0_START_PSDM		0x1F00000
 540#define PXP_BAR0_END_PSDM		(PXP_BAR0_START_PSDM + \
 541					 PXP_BAR0_SDM_LENGTH - 1)
 542
 543#define PXP_BAR0_FIRST_INVALID_ADDRESS	(PXP_BAR0_END_PSDM + 1)
 544
 545/* VF BAR */
 546#define PXP_VF_BAR0			0
 547
 548#define PXP_VF_BAR0_START_IGU		0
 549#define PXP_VF_BAR0_IGU_LENGTH		0x3000
 550#define PXP_VF_BAR0_END_IGU		(PXP_VF_BAR0_START_IGU + \
 551					 PXP_VF_BAR0_IGU_LENGTH - 1)
 552
 553#define PXP_VF_BAR0_START_DQ		0x3000
 554#define PXP_VF_BAR0_DQ_LENGTH		0x200
 555#define PXP_VF_BAR0_DQ_OPAQUE_OFFSET	0
 556#define PXP_VF_BAR0_ME_OPAQUE_ADDRESS	(PXP_VF_BAR0_START_DQ +	\
 557					 PXP_VF_BAR0_DQ_OPAQUE_OFFSET)
 558#define PXP_VF_BAR0_ME_CONCRETE_ADDRESS	(PXP_VF_BAR0_ME_OPAQUE_ADDRESS \
 559					 + 4)
 560#define PXP_VF_BAR0_END_DQ		(PXP_VF_BAR0_START_DQ +	\
 561					 PXP_VF_BAR0_DQ_LENGTH - 1)
 562
 563#define PXP_VF_BAR0_START_TSDM_ZONE_B	0x3200
 564#define PXP_VF_BAR0_SDM_LENGTH_ZONE_B	0x200
 565#define PXP_VF_BAR0_END_TSDM_ZONE_B	(PXP_VF_BAR0_START_TSDM_ZONE_B + \
 566					 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
 567
 568#define PXP_VF_BAR0_START_MSDM_ZONE_B	0x3400
 569#define PXP_VF_BAR0_END_MSDM_ZONE_B	(PXP_VF_BAR0_START_MSDM_ZONE_B + \
 570					 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
 571
 572#define PXP_VF_BAR0_START_USDM_ZONE_B	0x3600
 573#define PXP_VF_BAR0_END_USDM_ZONE_B	(PXP_VF_BAR0_START_USDM_ZONE_B + \
 574					 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
 575
 576#define PXP_VF_BAR0_START_XSDM_ZONE_B	0x3800
 577#define PXP_VF_BAR0_END_XSDM_ZONE_B	(PXP_VF_BAR0_START_XSDM_ZONE_B + \
 578					 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
 579
 580#define PXP_VF_BAR0_START_YSDM_ZONE_B	0x3a00
 581#define PXP_VF_BAR0_END_YSDM_ZONE_B	(PXP_VF_BAR0_START_YSDM_ZONE_B + \
 582					 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
 583
 584#define PXP_VF_BAR0_START_PSDM_ZONE_B	0x3c00
 585#define PXP_VF_BAR0_END_PSDM_ZONE_B	(PXP_VF_BAR0_START_PSDM_ZONE_B + \
 586					 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
 587
 588#define PXP_VF_BAR0_START_GRC		0x3E00
 589#define PXP_VF_BAR0_GRC_LENGTH		0x200
 590#define PXP_VF_BAR0_END_GRC		(PXP_VF_BAR0_START_GRC + \
 591					 PXP_VF_BAR0_GRC_LENGTH - 1)
 592
 593#define PXP_VF_BAR0_START_SDM_ZONE_A	0x4000
 594#define PXP_VF_BAR0_END_SDM_ZONE_A	0x10000
 595
 596#define PXP_VF_BAR0_START_IGU2		0x10000
 597#define PXP_VF_BAR0_IGU2_LENGTH		0xD000
 598#define PXP_VF_BAR0_END_IGU2		(PXP_VF_BAR0_START_IGU2 + \
 599					 PXP_VF_BAR0_IGU2_LENGTH - 1)
 600
 601#define PXP_VF_BAR0_GRC_WINDOW_LENGTH	32
 602
 603#define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN	12
 604#define PXP_ILT_BLOCK_FACTOR_MULTIPLIER	1024
 605
 606/* ILT Records */
 607#define PXP_NUM_ILT_RECORDS_BB 7600
 608#define PXP_NUM_ILT_RECORDS_K2 11000
 609#define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2)
 610
 611/* Host Interface */
 612#define PXP_QUEUES_ZONE_MAX_NUM	320
 613
 614/*****************/
 615/* PRM CONSTANTS */
 616/*****************/
 617#define PRM_DMA_PAD_BYTES_NUM	2
 618
 619/*****************/
 620/* SDMs CONSTANTS  */
 621/*****************/
 622
 623#define SDM_OP_GEN_TRIG_NONE		0
 624#define SDM_OP_GEN_TRIG_WAKE_THREAD	1
 625#define SDM_OP_GEN_TRIG_AGG_INT		2
 626#define SDM_OP_GEN_TRIG_LOADER		4
 627#define SDM_OP_GEN_TRIG_INDICATE_ERROR  6
 628#define SDM_OP_GEN_TRIG_INC_ORDER_CNT   9
 629
 630/********************/
 631/* Completion types */
 632/********************/
 633
 634#define SDM_COMP_TYPE_NONE		0
 635#define SDM_COMP_TYPE_WAKE_THREAD	1
 636#define SDM_COMP_TYPE_AGG_INT		2
 637#define SDM_COMP_TYPE_CM		3
 638#define SDM_COMP_TYPE_LOADER		4
 639#define SDM_COMP_TYPE_PXP		5
 640#define SDM_COMP_TYPE_INDICATE_ERROR	6
 641#define SDM_COMP_TYPE_RELEASE_THREAD	7
 642#define SDM_COMP_TYPE_RAM		8
 643#define SDM_COMP_TYPE_INC_ORDER_CNT	9
 644
 645/*****************/
 646/* PBF CONSTANTS */
 647/*****************/
 648
 649/* Number of PBF command queue lines. Each line is 32B. */
 650#define PBF_MAX_CMD_LINES	3328
 651
 652/* Number of BTB blocks. Each block is 256B. */
 653#define BTB_MAX_BLOCKS_BB 1440
 654#define BTB_MAX_BLOCKS_K2 1840
 655/*****************/
 656/* PRS CONSTANTS */
 657/*****************/
 658
 659#define PRS_GFT_CAM_LINES_NO_MATCH	31
 660
 661/* Interrupt coalescing TimeSet */
 662struct coalescing_timeset {
 663	u8 value;
 664#define	COALESCING_TIMESET_TIMESET_MASK		0x7F
 665#define	COALESCING_TIMESET_TIMESET_SHIFT	0
 666#define	COALESCING_TIMESET_VALID_MASK		0x1
 667#define	COALESCING_TIMESET_VALID_SHIFT		7
 668};
 669
 670struct common_queue_zone {
 671	__le16 ring_drv_data_consumer;
 672	__le16 reserved;
 673};
 674
 675/* ETH Rx producers data */
 676struct eth_rx_prod_data {
 677	__le16 bd_prod;
 678	__le16 cqe_prod;
 679};
 680
 681struct tcp_ulp_connect_done_params {
 682	__le16 mss;
 683	u8 snd_wnd_scale;
 684	u8 flags;
 685#define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_MASK		0x1
 686#define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_SHIFT		0
 687#define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_MASK	0x7F
 688#define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_SHIFT	1
 689};
 690
 691struct iscsi_connect_done_results {
 692	__le16 icid;
 693	__le16 conn_id;
 694	struct tcp_ulp_connect_done_params params;
 695};
 696
 697struct iscsi_eqe_data {
 698	__le16 icid;
 699	__le16 conn_id;
 700	__le16 reserved;
 701	u8 error_code;
 702	u8 error_pdu_opcode_reserved;
 703#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK		0x3F
 704#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT		0
 705#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK	0x1
 706#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT	 6
 707#define ISCSI_EQE_DATA_RESERVED0_MASK			0x1
 708#define ISCSI_EQE_DATA_RESERVED0_SHIFT			7
 709};
 710
 711/* Multi function mode */
 712enum mf_mode {
 713	ERROR_MODE /* Unsupported mode */,
 714	MF_OVLAN,
 715	MF_NPAR,
 716	MAX_MF_MODE
 717};
 718
 719/* Per protocol packet duplication enable bit vector. If set, duplicate
 720 * offloaded traffic to LL2 debug queueu.
 721 */
 722struct offload_pkt_dup_enable {
 723	__le16 enable_vector;
 724};
 725
 726/* Per-protocol connection types */
 727enum protocol_type {
 728	PROTOCOLID_TCP_ULP,
 729	PROTOCOLID_FCOE,
 730	PROTOCOLID_ROCE,
 731	PROTOCOLID_CORE,
 732	PROTOCOLID_ETH,
 733	PROTOCOLID_IWARP,
 734	PROTOCOLID_RESERVED0,
 735	PROTOCOLID_PREROCE,
 736	PROTOCOLID_COMMON,
 737	PROTOCOLID_RESERVED1,
 738	PROTOCOLID_RDMA,
 739	PROTOCOLID_SCSI,
 740	MAX_PROTOCOL_TYPE
 741};
 742
 743/* Pstorm packet duplication config */
 744struct pstorm_pkt_dup_cfg {
 745	struct offload_pkt_dup_enable enable;
 746	__le16 reserved[3];
 747};
 748
 749struct regpair {
 750	__le32 lo;
 751	__le32 hi;
 752};
 753
 754/* RoCE Destroy Event Data */
 755struct rdma_eqe_destroy_qp {
 756	__le32 cid;
 757	u8 reserved[4];
 758};
 759
 760/* RoCE Suspend Event Data */
 761struct rdma_eqe_suspend_qp {
 762	__le32 cid;
 763	u8 reserved[4];
 764};
 765
 766/* RDMA Event Data Union */
 767union rdma_eqe_data {
 768	struct regpair async_handle;
 769	struct rdma_eqe_destroy_qp rdma_destroy_qp_data;
 770	struct rdma_eqe_suspend_qp rdma_suspend_qp_data;
 771};
 772
 773/* Tstorm packet duplication config */
 774struct tstorm_pkt_dup_cfg {
 775	struct offload_pkt_dup_enable enable;
 776	__le16 reserved;
 777	__le32 cid;
 778};
 779
 780struct tstorm_queue_zone {
 781	__le32 reserved[2];
 782};
 783
 784/* Ustorm Queue Zone */
 785struct ustorm_eth_queue_zone {
 786	struct coalescing_timeset int_coalescing_timeset;
 787	u8 reserved[3];
 788};
 789
 790struct ustorm_queue_zone {
 791	struct ustorm_eth_queue_zone eth;
 792	struct common_queue_zone common;
 793};
 794
 795/* Status block structure */
 796struct cau_pi_entry {
 797	__le32 prod;
 798#define CAU_PI_ENTRY_PROD_VAL_MASK	0xFFFF
 799#define CAU_PI_ENTRY_PROD_VAL_SHIFT	0
 800#define CAU_PI_ENTRY_PI_TIMESET_MASK	0x7F
 801#define CAU_PI_ENTRY_PI_TIMESET_SHIFT	16
 802#define CAU_PI_ENTRY_FSM_SEL_MASK	0x1
 803#define CAU_PI_ENTRY_FSM_SEL_SHIFT	23
 804#define CAU_PI_ENTRY_RESERVED_MASK	0xFF
 805#define CAU_PI_ENTRY_RESERVED_SHIFT	24
 806};
 807
 808/* Status block structure */
 809struct cau_sb_entry {
 810	__le32 data;
 811#define CAU_SB_ENTRY_SB_PROD_MASK	0xFFFFFF
 812#define CAU_SB_ENTRY_SB_PROD_SHIFT	0
 813#define CAU_SB_ENTRY_STATE0_MASK	0xF
 814#define CAU_SB_ENTRY_STATE0_SHIFT	24
 815#define CAU_SB_ENTRY_STATE1_MASK	0xF
 816#define CAU_SB_ENTRY_STATE1_SHIFT	28
 817	__le32 params;
 818#define CAU_SB_ENTRY_SB_TIMESET0_MASK	0x7F
 819#define CAU_SB_ENTRY_SB_TIMESET0_SHIFT	0
 820#define CAU_SB_ENTRY_SB_TIMESET1_MASK	0x7F
 821#define CAU_SB_ENTRY_SB_TIMESET1_SHIFT	7
 822#define CAU_SB_ENTRY_TIMER_RES0_MASK	0x3
 823#define CAU_SB_ENTRY_TIMER_RES0_SHIFT	14
 824#define CAU_SB_ENTRY_TIMER_RES1_MASK	0x3
 825#define CAU_SB_ENTRY_TIMER_RES1_SHIFT	16
 826#define CAU_SB_ENTRY_VF_NUMBER_MASK	0xFF
 827#define CAU_SB_ENTRY_VF_NUMBER_SHIFT	18
 828#define CAU_SB_ENTRY_VF_VALID_MASK	0x1
 829#define CAU_SB_ENTRY_VF_VALID_SHIFT	26
 830#define CAU_SB_ENTRY_PF_NUMBER_MASK	0xF
 831#define CAU_SB_ENTRY_PF_NUMBER_SHIFT	27
 832#define CAU_SB_ENTRY_TPH_MASK		0x1
 833#define CAU_SB_ENTRY_TPH_SHIFT		31
 834};
 835
 836/* Igu cleanup bit values to distinguish between clean or producer consumer
 837 * update.
 838 */
 839enum command_type_bit {
 840	IGU_COMMAND_TYPE_NOP = 0,
 841	IGU_COMMAND_TYPE_SET = 1,
 842	MAX_COMMAND_TYPE_BIT
 843};
 844
 845/* Core doorbell data */
 846struct core_db_data {
 847	u8 params;
 848#define CORE_DB_DATA_DEST_MASK		0x3
 849#define CORE_DB_DATA_DEST_SHIFT		0
 850#define CORE_DB_DATA_AGG_CMD_MASK	0x3
 851#define CORE_DB_DATA_AGG_CMD_SHIFT	2
 852#define CORE_DB_DATA_BYPASS_EN_MASK	0x1
 853#define CORE_DB_DATA_BYPASS_EN_SHIFT	4
 854#define CORE_DB_DATA_RESERVED_MASK	0x1
 855#define CORE_DB_DATA_RESERVED_SHIFT	5
 856#define CORE_DB_DATA_AGG_VAL_SEL_MASK	0x3
 857#define CORE_DB_DATA_AGG_VAL_SEL_SHIFT	6
 858	u8 agg_flags;
 859	__le16 spq_prod;
 860};
 861
 862/* Enum of doorbell aggregative command selection */
 863enum db_agg_cmd_sel {
 864	DB_AGG_CMD_NOP,
 865	DB_AGG_CMD_SET,
 866	DB_AGG_CMD_ADD,
 867	DB_AGG_CMD_MAX,
 868	MAX_DB_AGG_CMD_SEL
 869};
 870
 871/* Enum of doorbell destination */
 872enum db_dest {
 873	DB_DEST_XCM,
 874	DB_DEST_UCM,
 875	DB_DEST_TCM,
 876	DB_NUM_DESTINATIONS,
 877	MAX_DB_DEST
 878};
 879
 880/* Enum of doorbell DPM types */
 881enum db_dpm_type {
 882	DPM_LEGACY,
 883	DPM_RDMA,
 884	DPM_L2_INLINE,
 885	DPM_L2_BD,
 886	MAX_DB_DPM_TYPE
 887};
 888
 889/* Structure for doorbell data, in L2 DPM mode, for 1st db in a DPM burst */
 890struct db_l2_dpm_data {
 891	__le16 icid;
 892	__le16 bd_prod;
 893	__le32 params;
 894#define DB_L2_DPM_DATA_SIZE_MASK	0x3F
 895#define DB_L2_DPM_DATA_SIZE_SHIFT	0
 896#define DB_L2_DPM_DATA_DPM_TYPE_MASK	0x3
 897#define DB_L2_DPM_DATA_DPM_TYPE_SHIFT	6
 898#define DB_L2_DPM_DATA_NUM_BDS_MASK	0xFF
 899#define DB_L2_DPM_DATA_NUM_BDS_SHIFT	8
 900#define DB_L2_DPM_DATA_PKT_SIZE_MASK	0x7FF
 901#define DB_L2_DPM_DATA_PKT_SIZE_SHIFT	16
 902#define DB_L2_DPM_DATA_RESERVED0_MASK	0x1
 903#define DB_L2_DPM_DATA_RESERVED0_SHIFT 27
 904#define DB_L2_DPM_DATA_SGE_NUM_MASK	0x7
 905#define DB_L2_DPM_DATA_SGE_NUM_SHIFT	28
 906#define DB_L2_DPM_DATA_TGFS_SRC_EN_MASK  0x1
 907#define DB_L2_DPM_DATA_TGFS_SRC_EN_SHIFT 31
 908};
 909
 910/* Structure for SGE in a DPM doorbell of type DPM_L2_BD */
 911struct db_l2_dpm_sge {
 912	struct regpair addr;
 913	__le16 nbytes;
 914	__le16 bitfields;
 915#define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK		0x1FF
 916#define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT	0
 917#define DB_L2_DPM_SGE_RESERVED0_MASK		0x3
 918#define DB_L2_DPM_SGE_RESERVED0_SHIFT		9
 919#define DB_L2_DPM_SGE_ST_VALID_MASK		0x1
 920#define DB_L2_DPM_SGE_ST_VALID_SHIFT		11
 921#define DB_L2_DPM_SGE_RESERVED1_MASK		0xF
 922#define DB_L2_DPM_SGE_RESERVED1_SHIFT		12
 923	__le32 reserved2;
 924};
 925
 926/* Structure for doorbell address, in legacy mode */
 927struct db_legacy_addr {
 928	__le32 addr;
 929#define DB_LEGACY_ADDR_RESERVED0_MASK	0x3
 930#define DB_LEGACY_ADDR_RESERVED0_SHIFT	0
 931#define DB_LEGACY_ADDR_DEMS_MASK	0x7
 932#define DB_LEGACY_ADDR_DEMS_SHIFT	2
 933#define DB_LEGACY_ADDR_ICID_MASK	0x7FFFFFF
 934#define DB_LEGACY_ADDR_ICID_SHIFT	5
 935};
 936
 937/* Structure for doorbell address, in legacy mode, without DEMS */
 938struct db_legacy_wo_dems_addr {
 939	__le32 addr;
 940#define DB_LEGACY_WO_DEMS_ADDR_RESERVED0_MASK   0x3
 941#define DB_LEGACY_WO_DEMS_ADDR_RESERVED0_SHIFT  0
 942#define DB_LEGACY_WO_DEMS_ADDR_ICID_MASK        0x3FFFFFFF
 943#define DB_LEGACY_WO_DEMS_ADDR_ICID_SHIFT       2
 944};
 945
 946/* Structure for doorbell address, in PWM mode */
 947struct db_pwm_addr {
 948	__le32 addr;
 949#define DB_PWM_ADDR_RESERVED0_MASK	0x7
 950#define DB_PWM_ADDR_RESERVED0_SHIFT	0
 951#define DB_PWM_ADDR_OFFSET_MASK		0x7F
 952#define DB_PWM_ADDR_OFFSET_SHIFT	3
 953#define DB_PWM_ADDR_WID_MASK		0x3
 954#define DB_PWM_ADDR_WID_SHIFT		10
 955#define DB_PWM_ADDR_DPI_MASK		0xFFFF
 956#define DB_PWM_ADDR_DPI_SHIFT		12
 957#define DB_PWM_ADDR_RESERVED1_MASK	0xF
 958#define DB_PWM_ADDR_RESERVED1_SHIFT	28
 959};
 960
 961/* Parameters to RDMA firmware, passed in EDPM doorbell */
 962struct db_rdma_24b_icid_dpm_params {
 963	__le32 params;
 964#define DB_RDMA_24B_ICID_DPM_PARAMS_SIZE_MASK   0x3F
 965#define DB_RDMA_24B_ICID_DPM_PARAMS_SIZE_SHIFT  0
 966#define DB_RDMA_24B_ICID_DPM_PARAMS_DPM_TYPE_MASK       0x3
 967#define DB_RDMA_24B_ICID_DPM_PARAMS_DPM_TYPE_SHIFT      6
 968#define DB_RDMA_24B_ICID_DPM_PARAMS_OPCODE_MASK 0xFF
 969#define DB_RDMA_24B_ICID_DPM_PARAMS_OPCODE_SHIFT        8
 970#define DB_RDMA_24B_ICID_DPM_PARAMS_ICID_EXT_MASK       0xFF
 971#define DB_RDMA_24B_ICID_DPM_PARAMS_ICID_EXT_SHIFT      16
 972#define DB_RDMA_24B_ICID_DPM_PARAMS_INV_BYTE_CNT_MASK   0x7
 973#define DB_RDMA_24B_ICID_DPM_PARAMS_INV_BYTE_CNT_SHIFT  24
 974#define DB_RDMA_24B_ICID_DPM_PARAMS_EXT_ICID_MODE_EN_MASK       0x1
 975#define DB_RDMA_24B_ICID_DPM_PARAMS_EXT_ICID_MODE_EN_SHIFT      27
 976#define DB_RDMA_24B_ICID_DPM_PARAMS_COMPLETION_FLG_MASK 0x1
 977#define DB_RDMA_24B_ICID_DPM_PARAMS_COMPLETION_FLG_SHIFT        28
 978#define DB_RDMA_24B_ICID_DPM_PARAMS_S_FLG_MASK  0x1
 979#define DB_RDMA_24B_ICID_DPM_PARAMS_S_FLG_SHIFT 29
 980#define DB_RDMA_24B_ICID_DPM_PARAMS_RESERVED1_MASK      0x1
 981#define DB_RDMA_24B_ICID_DPM_PARAMS_RESERVED1_SHIFT     30
 982#define DB_RDMA_24B_ICID_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK     0x1
 983#define DB_RDMA_24B_ICID_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT    31
 984};
 985
 986/* Parameters to RDMA firmware, passed in EDPM doorbell */
 987struct db_rdma_dpm_params {
 988	__le32 params;
 989#define DB_RDMA_DPM_PARAMS_SIZE_MASK			0x3F
 990#define DB_RDMA_DPM_PARAMS_SIZE_SHIFT			0
 991#define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK		0x3
 992#define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT		6
 993#define DB_RDMA_DPM_PARAMS_OPCODE_MASK			0xFF
 994#define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT			8
 995#define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK		0x7FF
 996#define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT		16
 997#define DB_RDMA_DPM_PARAMS_RESERVED0_MASK		0x1
 998#define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT		27
 999#define DB_RDMA_DPM_PARAMS_ACK_REQUEST_MASK		0x1
1000#define DB_RDMA_DPM_PARAMS_ACK_REQUEST_SHIFT		28
1001#define DB_RDMA_DPM_PARAMS_S_FLG_MASK			0x1
1002#define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT			29
1003#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK		0x1
1004#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT		30
1005#define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK	0x1
1006#define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT	31
1007};
1008
1009/* Structure for doorbell data, in RDMA DPM mode, for the first doorbell in a
1010 * DPM burst.
1011 */
1012struct db_rdma_dpm_data {
1013	__le16 icid;
1014	__le16 prod_val;
1015	struct db_rdma_dpm_params params;
1016};
1017
1018/* Igu interrupt command */
1019enum igu_int_cmd {
1020	IGU_INT_ENABLE	= 0,
1021	IGU_INT_DISABLE = 1,
1022	IGU_INT_NOP	= 2,
1023	IGU_INT_NOP2	= 3,
1024	MAX_IGU_INT_CMD
1025};
1026
1027/* IGU producer or consumer update command */
1028struct igu_prod_cons_update {
1029	__le32 sb_id_and_flags;
1030#define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK		0xFFFFFF
1031#define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT		0
1032#define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK		0x1
1033#define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT		24
1034#define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK		0x3
1035#define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT		25
1036#define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK	0x1
1037#define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT	27
1038#define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK		0x1
1039#define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT		28
1040#define IGU_PROD_CONS_UPDATE_RESERVED0_MASK		0x3
1041#define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT		29
1042#define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK		0x1
1043#define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT		31
1044	__le32 reserved1;
1045};
1046
1047/* Igu segments access for default status block only */
1048enum igu_seg_access {
1049	IGU_SEG_ACCESS_REG	= 0,
1050	IGU_SEG_ACCESS_ATTN	= 1,
1051	MAX_IGU_SEG_ACCESS
1052};
1053
1054/* Enumeration for L3 type field of parsing_and_err_flags.
1055 * L3Type: 0 - unknown (not ip), 1 - Ipv4, 2 - Ipv6
1056 * (This field can be filled according to the last-ethertype)
1057 */
1058enum l3_type {
1059	e_l3_type_unknown,
1060	e_l3_type_ipv4,
1061	e_l3_type_ipv6,
1062	MAX_L3_TYPE
1063};
1064
1065/* Enumeration for l4Protocol field of parsing_and_err_flags.
1066 * L4-protocol: 0 - none, 1 - TCP, 2 - UDP.
1067 * If the packet is IPv4 fragment, and its not the first fragment, the
1068 * protocol-type should be set to none.
1069 */
1070enum l4_protocol {
1071	e_l4_protocol_none,
1072	e_l4_protocol_tcp,
1073	e_l4_protocol_udp,
1074	MAX_L4_PROTOCOL
1075};
1076
1077/* Parsing and error flags field */
1078struct parsing_and_err_flags {
1079	__le16 flags;
1080#define PARSING_AND_ERR_FLAGS_L3TYPE_MASK			0x3
1081#define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT			0
1082#define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK			0x3
1083#define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT			2
1084#define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK			0x1
1085#define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT			4
1086#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK		0x1
1087#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT		5
1088#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK		0x1
1089#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT	6
1090#define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK			0x1
1091#define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT			7
1092#define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK		0x1
1093#define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT		8
1094#define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK			0x1
1095#define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT			9
1096#define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK			0x1
1097#define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT		10
1098#define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK			0x1
1099#define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT			11
1100#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK		0x1
1101#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT		12
1102#define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK		0x1
1103#define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT		13
1104#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK	0x1
1105#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT	14
1106#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK		0x1
1107#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT		15
1108};
1109
1110/* Parsing error flags bitmap */
1111struct parsing_err_flags {
1112	__le16 flags;
1113#define PARSING_ERR_FLAGS_MAC_ERROR_MASK				0x1
1114#define PARSING_ERR_FLAGS_MAC_ERROR_SHIFT				0
1115#define PARSING_ERR_FLAGS_TRUNC_ERROR_MASK				0x1
1116#define PARSING_ERR_FLAGS_TRUNC_ERROR_SHIFT				1
1117#define PARSING_ERR_FLAGS_PKT_TOO_SMALL_MASK				0x1
1118#define PARSING_ERR_FLAGS_PKT_TOO_SMALL_SHIFT				2
1119#define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_MASK			0x1
1120#define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_SHIFT			3
1121#define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_MASK			0x1
1122#define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_SHIFT			4
1123#define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_MASK		0x1
1124#define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_SHIFT		5
1125#define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_MASK			0x1
1126#define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_SHIFT		6
1127#define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_MASK			0x1
1128#define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_SHIFT			7
1129#define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_MASK		0x1
1130#define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_SHIFT		8
1131#define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_MASK			0x1
1132#define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_SHIFT			9
1133#define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_MASK			0x1
1134#define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_SHIFT			10
1135#define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_MASK		0x1
1136#define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_SHIFT		11
1137#define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_MASK	0x1
1138#define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_SHIFT	12
1139#define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_MASK			0x1
1140#define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_SHIFT			13
1141#define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_MASK			0x1
1142#define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_SHIFT		14
1143#define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_MASK			0x1
1144#define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT			15
1145};
1146
1147/* Pb context */
1148struct pb_context {
1149	__le32 crc[4];
1150};
1151
1152/* Concrete Function ID */
1153struct pxp_concrete_fid {
1154	__le16 fid;
1155#define PXP_CONCRETE_FID_PFID_MASK	0xF
1156#define PXP_CONCRETE_FID_PFID_SHIFT	0
1157#define PXP_CONCRETE_FID_PORT_MASK	0x3
1158#define PXP_CONCRETE_FID_PORT_SHIFT	4
1159#define PXP_CONCRETE_FID_PATH_MASK	0x1
1160#define PXP_CONCRETE_FID_PATH_SHIFT	6
1161#define PXP_CONCRETE_FID_VFVALID_MASK	0x1
1162#define PXP_CONCRETE_FID_VFVALID_SHIFT	7
1163#define PXP_CONCRETE_FID_VFID_MASK	0xFF
1164#define PXP_CONCRETE_FID_VFID_SHIFT	8
1165};
1166
1167/* Concrete Function ID */
1168struct pxp_pretend_concrete_fid {
1169	__le16 fid;
1170#define PXP_PRETEND_CONCRETE_FID_PFID_MASK	0xF
1171#define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT	0
1172#define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK	0x7
1173#define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT	4
1174#define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK	0x1
1175#define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT	7
1176#define PXP_PRETEND_CONCRETE_FID_VFID_MASK	0xFF
1177#define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT	8
1178};
1179
1180/* Function ID */
1181union pxp_pretend_fid {
1182	struct pxp_pretend_concrete_fid concrete_fid;
1183	__le16 opaque_fid;
1184};
1185
1186/* Pxp Pretend Command Register */
1187struct pxp_pretend_cmd {
1188	union pxp_pretend_fid fid;
1189	__le16 control;
1190#define PXP_PRETEND_CMD_PATH_MASK		0x1
1191#define PXP_PRETEND_CMD_PATH_SHIFT		0
1192#define PXP_PRETEND_CMD_USE_PORT_MASK		0x1
1193#define PXP_PRETEND_CMD_USE_PORT_SHIFT		1
1194#define PXP_PRETEND_CMD_PORT_MASK		0x3
1195#define PXP_PRETEND_CMD_PORT_SHIFT		2
1196#define PXP_PRETEND_CMD_RESERVED0_MASK		0xF
1197#define PXP_PRETEND_CMD_RESERVED0_SHIFT		4
1198#define PXP_PRETEND_CMD_RESERVED1_MASK		0xF
1199#define PXP_PRETEND_CMD_RESERVED1_SHIFT		8
1200#define PXP_PRETEND_CMD_PRETEND_PATH_MASK	0x1
1201#define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT	12
1202#define PXP_PRETEND_CMD_PRETEND_PORT_MASK	0x1
1203#define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT	13
1204#define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK	0x1
1205#define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT	14
1206#define PXP_PRETEND_CMD_IS_CONCRETE_MASK	0x1
1207#define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT	15
1208};
1209
1210/* PTT Record in PXP Admin Window */
1211struct pxp_ptt_entry {
1212	__le32 offset;
1213#define PXP_PTT_ENTRY_OFFSET_MASK	0x7FFFFF
1214#define PXP_PTT_ENTRY_OFFSET_SHIFT	0
1215#define PXP_PTT_ENTRY_RESERVED0_MASK	0x1FF
1216#define PXP_PTT_ENTRY_RESERVED0_SHIFT	23
1217	struct pxp_pretend_cmd pretend;
1218};
1219
1220/* VF Zone A Permission Register */
1221struct pxp_vf_zone_a_permission {
1222	__le32 control;
1223#define PXP_VF_ZONE_A_PERMISSION_VFID_MASK		0xFF
1224#define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT		0
1225#define PXP_VF_ZONE_A_PERMISSION_VALID_MASK		0x1
1226#define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT		8
1227#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK		0x7F
1228#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT	9
1229#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK		0xFFFF
1230#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT	16
1231};
1232
1233/* Rdif context */
1234struct rdif_task_context {
1235	__le32 initial_ref_tag;
1236	__le16 app_tag_value;
1237	__le16 app_tag_mask;
1238	u8 flags0;
1239#define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK		0x1
1240#define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT		0
1241#define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK	0x1
1242#define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT	1
1243#define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK		0x1
1244#define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT		2
1245#define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK	0x1
1246#define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT	3
1247#define RDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK		0x3
1248#define RDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT		4
1249#define RDIF_TASK_CONTEXT_CRC_SEED_MASK			0x1
1250#define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT		6
1251#define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK	0x1
1252#define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT	7
1253	u8 partial_dif_data[7];
1254	__le16 partial_crc_value;
1255	__le16 partial_checksum_value;
1256	__le32 offset_in_io;
1257	__le16 flags1;
1258#define RDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK			0x1
1259#define RDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT			0
1260#define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK			0x1
1261#define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT		1
1262#define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK			0x1
1263#define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT		2
1264#define RDIF_TASK_CONTEXT_FORWARD_GUARD_MASK			0x1
1265#define RDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT			3
1266#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK			0x1
1267#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT			4
1268#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK			0x1
1269#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT			5
1270#define RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK			0x7
1271#define RDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT			6
1272#define RDIF_TASK_CONTEXT_HOST_INTERFACE_MASK			0x3
1273#define RDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT			9
1274#define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK			0x1
1275#define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT			11
1276#define RDIF_TASK_CONTEXT_RESERVED0_MASK			0x1
1277#define RDIF_TASK_CONTEXT_RESERVED0_SHIFT			12
1278#define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK		0x1
1279#define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT		13
1280#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK	0x1
1281#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT	14
1282#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK	0x1
1283#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT	15
1284	__le16 state;
1285#define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_MASK		0xF
1286#define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_SHIFT		0
1287#define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_MASK	0xF
1288#define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_SHIFT	4
1289#define RDIF_TASK_CONTEXT_ERROR_IN_IO_MASK			0x1
1290#define RDIF_TASK_CONTEXT_ERROR_IN_IO_SHIFT			8
1291#define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_MASK		0x1
1292#define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_SHIFT		9
1293#define RDIF_TASK_CONTEXT_REF_TAG_MASK_MASK			0xF
1294#define RDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT			10
1295#define RDIF_TASK_CONTEXT_RESERVED1_MASK			0x3
1296#define RDIF_TASK_CONTEXT_RESERVED1_SHIFT			14
1297	__le32 reserved2;
1298};
1299
1300/* Searcher Table struct */
1301struct src_entry_header {
1302	__le32 flags;
1303#define SRC_ENTRY_HEADER_NEXT_PTR_TYPE_MASK     0x1
1304#define SRC_ENTRY_HEADER_NEXT_PTR_TYPE_SHIFT    0
1305#define SRC_ENTRY_HEADER_EMPTY_MASK     0x1
1306#define SRC_ENTRY_HEADER_EMPTY_SHIFT    1
1307#define SRC_ENTRY_HEADER_RESERVED_MASK  0x3FFFFFFF
1308#define SRC_ENTRY_HEADER_RESERVED_SHIFT 2
1309	__le32 magic_number;
1310	struct regpair next_ptr;
1311};
1312
1313/* Enumeration for address type */
1314enum src_header_next_ptr_type_enum {
1315	e_physical_addr,
1316	e_logical_addr,
1317	MAX_SRC_HEADER_NEXT_PTR_TYPE_ENUM
1318};
1319
1320/* Status block structure */
1321struct status_block {
1322	__le16	pi_array[PIS_PER_SB];
1323	__le32	sb_num;
1324#define STATUS_BLOCK_SB_NUM_MASK	0x1FF
1325#define STATUS_BLOCK_SB_NUM_SHIFT	0
1326#define STATUS_BLOCK_ZERO_PAD_MASK	0x7F
1327#define STATUS_BLOCK_ZERO_PAD_SHIFT	9
1328#define STATUS_BLOCK_ZERO_PAD2_MASK	0xFFFF
1329#define STATUS_BLOCK_ZERO_PAD2_SHIFT	16
1330	__le32 prod_index;
1331#define STATUS_BLOCK_PROD_INDEX_MASK		0xFFFFFF
1332#define STATUS_BLOCK_PROD_INDEX_SHIFT	0
1333#define STATUS_BLOCK_ZERO_PAD3_MASK		0xFF
1334#define STATUS_BLOCK_ZERO_PAD3_SHIFT		24
1335};
1336
1337/* Tdif context */
1338struct tdif_task_context {
1339	__le32 initial_ref_tag;
1340	__le16 app_tag_value;
1341	__le16 app_tag_mask;
1342	__le16 partial_crc_value_b;
1343	__le16 partial_checksum_value_b;
1344	__le16 stateB;
1345#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_MASK	0xF
1346#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_SHIFT	0
1347#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_MASK	0xF
1348#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_SHIFT	4
1349#define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_MASK			0x1
1350#define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_SHIFT			8
1351#define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_MASK			0x1
1352#define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_SHIFT		9
1353#define TDIF_TASK_CONTEXT_RESERVED0_MASK			0x3F
1354#define TDIF_TASK_CONTEXT_RESERVED0_SHIFT			10
1355	u8 reserved1;
1356	u8 flags0;
1357#define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK			0x1
1358#define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT			0
1359#define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK		0x1
1360#define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT		1
1361#define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK			0x1
1362#define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT			2
1363#define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK		0x1
1364#define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT		3
1365#define TDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK			0x3
1366#define TDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT			4
1367#define TDIF_TASK_CONTEXT_CRC_SEED_MASK				0x1
1368#define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT			6
1369#define TDIF_TASK_CONTEXT_RESERVED2_MASK			0x1
1370#define TDIF_TASK_CONTEXT_RESERVED2_SHIFT			7
1371	__le32 flags1;
1372#define TDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK			0x1
1373#define TDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT			0
1374#define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK			0x1
1375#define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT		1
1376#define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK			0x1
1377#define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT		2
1378#define TDIF_TASK_CONTEXT_FORWARD_GUARD_MASK			0x1
1379#define TDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT			3
1380#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK			0x1
1381#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT			4
1382#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK			0x1
1383#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT			5
1384#define TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK			0x7
1385#define TDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT			6
1386#define TDIF_TASK_CONTEXT_HOST_INTERFACE_MASK			0x3
1387#define TDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT			9
1388#define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK			0x1
1389#define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT			11
1390#define TDIF_TASK_CONTEXT_RESERVED3_MASK			0x1
1391#define TDIF_TASK_CONTEXT_RESERVED3_SHIFT			12
1392#define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK		0x1
1393#define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT		13
1394#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_MASK	0xF
1395#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_SHIFT	14
1396#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_MASK	0xF
1397#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_SHIFT	18
1398#define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_MASK			0x1
1399#define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_SHIFT			22
1400#define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_MASK		0x1
1401#define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_SHIFT		23
1402#define TDIF_TASK_CONTEXT_REF_TAG_MASK_MASK			0xF
1403#define TDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT			24
1404#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK	0x1
1405#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT	28
1406#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK	0x1
1407#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT	29
1408#define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK		0x1
1409#define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT		30
1410#define TDIF_TASK_CONTEXT_RESERVED4_MASK			0x1
1411#define TDIF_TASK_CONTEXT_RESERVED4_SHIFT			31
1412	__le32 offset_in_io_b;
1413	__le16 partial_crc_value_a;
1414	__le16 partial_checksum_value_a;
1415	__le32 offset_in_io_a;
1416	u8 partial_dif_data_a[8];
1417	u8 partial_dif_data_b[8];
1418};
1419
1420/* Timers context */
1421struct timers_context {
1422	__le32 logical_client_0;
1423#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK	0x7FFFFFF
1424#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT	0
1425#define TIMERS_CONTEXT_RESERVED0_MASK		0x1
1426#define TIMERS_CONTEXT_RESERVED0_SHIFT		27
1427#define TIMERS_CONTEXT_VALIDLC0_MASK		0x1
1428#define TIMERS_CONTEXT_VALIDLC0_SHIFT		28
1429#define TIMERS_CONTEXT_ACTIVELC0_MASK		0x1
1430#define TIMERS_CONTEXT_ACTIVELC0_SHIFT		29
1431#define TIMERS_CONTEXT_RESERVED1_MASK		0x3
1432#define TIMERS_CONTEXT_RESERVED1_SHIFT		30
1433	__le32 logical_client_1;
1434#define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK	0x7FFFFFF
1435#define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT	0
1436#define TIMERS_CONTEXT_RESERVED2_MASK		0x1
1437#define TIMERS_CONTEXT_RESERVED2_SHIFT		27
1438#define TIMERS_CONTEXT_VALIDLC1_MASK		0x1
1439#define TIMERS_CONTEXT_VALIDLC1_SHIFT		28
1440#define TIMERS_CONTEXT_ACTIVELC1_MASK		0x1
1441#define TIMERS_CONTEXT_ACTIVELC1_SHIFT		29
1442#define TIMERS_CONTEXT_RESERVED3_MASK		0x3
1443#define TIMERS_CONTEXT_RESERVED3_SHIFT		30
1444	__le32 logical_client_2;
1445#define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK	0x7FFFFFF
1446#define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT	0
1447#define TIMERS_CONTEXT_RESERVED4_MASK		0x1
1448#define TIMERS_CONTEXT_RESERVED4_SHIFT		27
1449#define TIMERS_CONTEXT_VALIDLC2_MASK		0x1
1450#define TIMERS_CONTEXT_VALIDLC2_SHIFT		28
1451#define TIMERS_CONTEXT_ACTIVELC2_MASK		0x1
1452#define TIMERS_CONTEXT_ACTIVELC2_SHIFT		29
1453#define TIMERS_CONTEXT_RESERVED5_MASK		0x3
1454#define TIMERS_CONTEXT_RESERVED5_SHIFT		30
1455	__le32 host_expiration_fields;
1456#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK	0x7FFFFFF
1457#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT	0
1458#define TIMERS_CONTEXT_RESERVED6_MASK			0x1
1459#define TIMERS_CONTEXT_RESERVED6_SHIFT			27
1460#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK	0x1
1461#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT	 28
1462#define TIMERS_CONTEXT_RESERVED7_MASK			0x7
1463#define TIMERS_CONTEXT_RESERVED7_SHIFT			29
1464};
1465
1466/* Enum for next_protocol field of tunnel_parsing_flags / tunnelTypeDesc */
1467enum tunnel_next_protocol {
1468	e_unknown = 0,
1469	e_l2 = 1,
1470	e_ipv4 = 2,
1471	e_ipv6 = 3,
1472	MAX_TUNNEL_NEXT_PROTOCOL
1473};
1474
1475#endif /* __COMMON_HSI__ */
1476#endif