pse.h

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3// Copyright (c) 2022 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
  4 */
  5#ifndef _LINUX_PSE_CONTROLLER_H
  6#define _LINUX_PSE_CONTROLLER_H
  7
  8#include <linux/list.h>
  9#include <linux/netlink.h>
 10#include <linux/kfifo.h>
 11#include <uapi/linux/ethtool.h>
 12#include <uapi/linux/ethtool_netlink_generated.h>
 13#include <linux/regulator/driver.h>
 14
 15/* Maximum current in uA according to IEEE 802.3-2022 Table 145-1 */
 16#define MAX_PI_CURRENT 1920000
 17/* Maximum power in mW according to IEEE 802.3-2022 Table 145-16 */
 18#define MAX_PI_PW 99900
 19
 20struct net_device;
 21struct phy_device;
 22struct pse_controller_dev;
 23struct netlink_ext_ack;
 24
 25/* C33 PSE extended state and substate. */
 26struct ethtool_c33_pse_ext_state_info {
 27	enum ethtool_c33_pse_ext_state c33_pse_ext_state;
 28	union {
 29		enum ethtool_c33_pse_ext_substate_error_condition error_condition;
 30		enum ethtool_c33_pse_ext_substate_mr_pse_enable mr_pse_enable;
 31		enum ethtool_c33_pse_ext_substate_option_detect_ted option_detect_ted;
 32		enum ethtool_c33_pse_ext_substate_option_vport_lim option_vport_lim;
 33		enum ethtool_c33_pse_ext_substate_ovld_detected ovld_detected;
 34		enum ethtool_c33_pse_ext_substate_power_not_available power_not_available;
 35		enum ethtool_c33_pse_ext_substate_short_detected short_detected;
 36		u32 __c33_pse_ext_substate;
 37	};
 38};
 39
 40struct ethtool_c33_pse_pw_limit_range {
 41	u32 min;
 42	u32 max;
 43};
 44
 45/**
 46 * struct pse_irq_desc - notification sender description for IRQ based events.
 47 *
 48 * @name: the visible name for the IRQ
 49 * @map_event: driver callback to map IRQ status into PSE devices with events.
 50 */
 51struct pse_irq_desc {
 52	const char *name;
 53	int (*map_event)(int irq, struct pse_controller_dev *pcdev,
 54			 unsigned long *notifs,
 55			 unsigned long *notifs_mask);
 56};
 57
 58/**
 59 * struct pse_control_config - PSE control/channel configuration.
 60 *
 61 * @podl_admin_control: set PoDL PSE admin control as described in
 62 *	IEEE 802.3-2018 30.15.1.2.1 acPoDLPSEAdminControl
 63 * @c33_admin_control: set PSE admin control as described in
 64 *	IEEE 802.3-2022 30.9.1.2.1 acPSEAdminControl
 65 */
 66struct pse_control_config {
 67	enum ethtool_podl_pse_admin_state podl_admin_control;
 68	enum ethtool_c33_pse_admin_state c33_admin_control;
 69};
 70
 71/**
 72 * struct pse_admin_state - PSE operational state
 73 *
 74 * @podl_admin_state: operational state of the PoDL PSE
 75 *	functions. IEEE 802.3-2018 30.15.1.1.2 aPoDLPSEAdminState
 76 * @c33_admin_state: operational state of the PSE
 77 *	functions. IEEE 802.3-2022 30.9.1.1.2 aPSEAdminState
 78 */
 79struct pse_admin_state {
 80	enum ethtool_podl_pse_admin_state podl_admin_state;
 81	enum ethtool_c33_pse_admin_state c33_admin_state;
 82};
 83
 84/**
 85 * struct pse_pw_status - PSE power detection status
 86 *
 87 * @podl_pw_status: power detection status of the PoDL PSE.
 88 *	IEEE 802.3-2018 30.15.1.1.3 aPoDLPSEPowerDetectionStatus:
 89 * @c33_pw_status: power detection status of the PSE.
 90 *	IEEE 802.3-2022 30.9.1.1.5 aPSEPowerDetectionStatus:
 91 */
 92struct pse_pw_status {
 93	enum ethtool_podl_pse_pw_d_status podl_pw_status;
 94	enum ethtool_c33_pse_pw_d_status c33_pw_status;
 95};
 96
 97/**
 98 * struct pse_ext_state_info - PSE extended state information
 99 *
100 * @c33_ext_state_info: extended state information of the PSE
101 */
102struct pse_ext_state_info {
103	struct ethtool_c33_pse_ext_state_info c33_ext_state_info;
104};
105
106/**
107 * struct pse_pw_limit_ranges - PSE power limit configuration range
108 *
109 * @c33_pw_limit_ranges: supported power limit configuration range. The driver
110 *			 is in charge of the memory allocation.
111 */
112struct pse_pw_limit_ranges {
113	struct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges;
114};
115
116/**
117 * struct ethtool_pse_control_status - PSE control/channel status.
118 *
119 * @pw_d_id: PSE power domain index.
120 * @podl_admin_state: operational state of the PoDL PSE
121 *	functions. IEEE 802.3-2018 30.15.1.1.2 aPoDLPSEAdminState
122 * @podl_pw_status: power detection status of the PoDL PSE.
123 *	IEEE 802.3-2018 30.15.1.1.3 aPoDLPSEPowerDetectionStatus:
124 * @c33_admin_state: operational state of the PSE
125 *	functions. IEEE 802.3-2022 30.9.1.1.2 aPSEAdminState
126 * @c33_pw_status: power detection status of the PSE.
127 *	IEEE 802.3-2022 30.9.1.1.5 aPSEPowerDetectionStatus:
128 * @c33_pw_class: detected class of a powered PD
129 *	IEEE 802.3-2022 30.9.1.1.8 aPSEPowerClassification
130 * @c33_actual_pw: power currently delivered by the PSE in mW
131 *	IEEE 802.3-2022 30.9.1.1.23 aPSEActualPower
132 * @c33_ext_state_info: extended state information of the PSE
133 * @c33_avail_pw_limit: available power limit of the PSE in mW
134 *	IEEE 802.3-2022 145.2.5.4 pse_avail_pwr
135 * @c33_pw_limit_ranges: supported power limit configuration range. The driver
136 *	is in charge of the memory allocation
137 * @c33_pw_limit_nb_ranges: number of supported power limit configuration
138 *	ranges
139 * @prio_max: max priority allowed for the c33_prio variable value.
140 * @prio: priority of the PSE. Managed by PSE core in case of static budget
141 *	evaluation strategy.
142 */
143struct ethtool_pse_control_status {
144	u32 pw_d_id;
145	enum ethtool_podl_pse_admin_state podl_admin_state;
146	enum ethtool_podl_pse_pw_d_status podl_pw_status;
147	enum ethtool_c33_pse_admin_state c33_admin_state;
148	enum ethtool_c33_pse_pw_d_status c33_pw_status;
149	u32 c33_pw_class;
150	u32 c33_actual_pw;
151	struct ethtool_c33_pse_ext_state_info c33_ext_state_info;
152	u32 c33_avail_pw_limit;
153	struct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges;
154	u32 c33_pw_limit_nb_ranges;
155	u32 prio_max;
156	u32 prio;
157};
158
159/**
160 * struct pse_controller_ops - PSE controller driver callbacks
161 *
162 * @setup_pi_matrix: Setup PI matrix of the PSE controller.
163 *		     The PSE PIs devicetree nodes have already been parsed by
164 *		     of_load_pse_pis() and the pcdev->pi[x]->pairset[y].np
165 *		     populated. This callback should establish the
166 *		     relationship between the PSE controller hardware ports
167 *		     and the PSE Power Interfaces, either through software
168 *		     mapping or hardware configuration.
169 * @pi_get_admin_state: Get the operational state of the PSE PI. This ops
170 *			is mandatory.
171 * @pi_get_pw_status: Get the power detection status of the PSE PI. This
172 *		      ops is mandatory.
173 * @pi_get_ext_state: Get the extended state of the PSE PI.
174 * @pi_get_pw_class: Get the power class of the PSE PI.
175 * @pi_get_actual_pw: Get actual power of the PSE PI in mW.
176 * @pi_enable: Configure the PSE PI as enabled.
177 * @pi_disable: Configure the PSE PI as disabled.
178 * @pi_get_voltage: Return voltage similarly to get_voltage regulator
179 *		    callback in uV.
180 * @pi_get_pw_limit: Get the configured power limit of the PSE PI in mW.
181 * @pi_set_pw_limit: Configure the power limit of the PSE PI in mW.
182 * @pi_get_pw_limit_ranges: Get the supported power limit configuration
183 *			    range. The driver is in charge of the memory
184 *			    allocation and should return the number of
185 *			    ranges.
186 * @pi_get_prio: Get the PSE PI priority.
187 * @pi_set_prio: Configure the PSE PI priority.
188 * @pi_get_pw_req: Get the power requested by a PD before enabling the PSE PI.
189 *		   This is only relevant when an interrupt is registered using
190 *		   devm_pse_irq_helper helper.
191 */
192struct pse_controller_ops {
193	int (*setup_pi_matrix)(struct pse_controller_dev *pcdev);
194	int (*pi_get_admin_state)(struct pse_controller_dev *pcdev, int id,
195				  struct pse_admin_state *admin_state);
196	int (*pi_get_pw_status)(struct pse_controller_dev *pcdev, int id,
197				struct pse_pw_status *pw_status);
198	int (*pi_get_ext_state)(struct pse_controller_dev *pcdev, int id,
199				struct pse_ext_state_info *ext_state_info);
200	int (*pi_get_pw_class)(struct pse_controller_dev *pcdev, int id);
201	int (*pi_get_actual_pw)(struct pse_controller_dev *pcdev, int id);
202	int (*pi_enable)(struct pse_controller_dev *pcdev, int id);
203	int (*pi_disable)(struct pse_controller_dev *pcdev, int id);
204	int (*pi_get_voltage)(struct pse_controller_dev *pcdev, int id);
205	int (*pi_get_pw_limit)(struct pse_controller_dev *pcdev,
206			       int id);
207	int (*pi_set_pw_limit)(struct pse_controller_dev *pcdev,
208			       int id, int max_mW);
209	int (*pi_get_pw_limit_ranges)(struct pse_controller_dev *pcdev, int id,
210				      struct pse_pw_limit_ranges *pw_limit_ranges);
211	int (*pi_get_prio)(struct pse_controller_dev *pcdev, int id);
212	int (*pi_set_prio)(struct pse_controller_dev *pcdev, int id,
213			   unsigned int prio);
214	int (*pi_get_pw_req)(struct pse_controller_dev *pcdev, int id);
215};
216
217struct module;
218struct device_node;
219struct of_phandle_args;
220struct pse_control;
221struct ethtool_pse_control_status;
222
223/* PSE PI pairset pinout can either be Alternative A or Alternative B */
224enum pse_pi_pairset_pinout {
225	ALTERNATIVE_A,
226	ALTERNATIVE_B,
227};
228
229/**
230 * struct pse_pi_pairset - PSE PI pairset entity describing the pinout
231 *			   alternative ant its phandle
232 *
233 * @pinout: description of the pinout alternative
234 * @np: device node pointer describing the pairset phandle
235 */
236struct pse_pi_pairset {
237	enum pse_pi_pairset_pinout pinout;
238	struct device_node *np;
239};
240
241/**
242 * struct pse_pi - PSE PI (Power Interface) entity as described in
243 *		   IEEE 802.3-2022 145.2.4
244 *
245 * @pairset: table of the PSE PI pinout alternative for the two pairset
246 * @np: device node pointer of the PSE PI node
247 * @rdev: regulator represented by the PSE PI
248 * @admin_state_enabled: PI enabled state
249 * @pw_d: Power domain of the PSE PI
250 * @prio: Priority of the PSE PI. Used in static budget evaluation strategy
251 * @isr_pd_detected: PSE PI detection status managed by the interruption
252 *		     handler. This variable is relevant when the power enabled
253 *		     management is managed in software like the static
254 *		     budget evaluation strategy.
255 * @pw_allocated_mW: Power allocated to a PSE PI to manage power budget in
256 *		     static budget evaluation strategy.
257 */
258struct pse_pi {
259	struct pse_pi_pairset pairset[2];
260	struct device_node *np;
261	struct regulator_dev *rdev;
262	bool admin_state_enabled;
263	struct pse_power_domain *pw_d;
264	int prio;
265	bool isr_pd_detected;
266	int pw_allocated_mW;
267};
268
269/**
270 * struct pse_ntf - PSE notification element
271 *
272 * @id: ID of the PSE control
273 * @notifs: PSE notifications to be reported
274 */
275struct pse_ntf {
276	int id;
277	unsigned long notifs;
278};
279
280/**
281 * struct pse_controller_dev - PSE controller entity that might
282 *                             provide multiple PSE controls
283 * @ops: a pointer to device specific struct pse_controller_ops
284 * @owner: kernel module of the PSE controller driver
285 * @list: internal list of PSE controller devices
286 * @pse_control_head: head of internal list of requested PSE controls
287 * @dev: corresponding driver model device struct
288 * @of_pse_n_cells: number of cells in PSE line specifiers
289 * @nr_lines: number of PSE controls in this controller device
290 * @lock: Mutex for serialization access to the PSE controller
291 * @types: types of the PSE controller
292 * @pi: table of PSE PIs described in this controller device
293 * @no_of_pse_pi: flag set if the pse_pis devicetree node is not used
294 * @irq: PSE interrupt
295 * @pis_prio_max: Maximum value allowed for the PSE PIs priority
296 * @supp_budget_eval_strategies: budget evaluation strategies supported
297 *				 by the PSE
298 * @ntf_work: workqueue for PSE notification management
299 * @ntf_fifo: PSE notifications FIFO
300 * @ntf_fifo_lock: protect @ntf_fifo writer
301 */
302struct pse_controller_dev {
303	const struct pse_controller_ops *ops;
304	struct module *owner;
305	struct list_head list;
306	struct list_head pse_control_head;
307	struct device *dev;
308	int of_pse_n_cells;
309	unsigned int nr_lines;
310	struct mutex lock;
311	enum ethtool_pse_types types;
312	struct pse_pi *pi;
313	bool no_of_pse_pi;
314	int irq;
315	unsigned int pis_prio_max;
316	u32 supp_budget_eval_strategies;
317	struct work_struct ntf_work;
318	DECLARE_KFIFO_PTR(ntf_fifo, struct pse_ntf);
319	spinlock_t ntf_fifo_lock; /* Protect @ntf_fifo writer */
320};
321
322/**
323 * enum pse_budget_eval_strategies - PSE budget evaluation strategies.
324 * @PSE_BUDGET_EVAL_STRAT_DISABLED: Budget evaluation strategy disabled.
325 * @PSE_BUDGET_EVAL_STRAT_STATIC: PSE static budget evaluation strategy.
326 *	Budget evaluation strategy based on the power requested during PD
327 *	classification. This strategy is managed by the PSE core.
328 * @PSE_BUDGET_EVAL_STRAT_DYNAMIC: PSE dynamic budget evaluation
329 *	strategy. Budget evaluation strategy based on the current consumption
330 *	per ports compared to the total	power budget. This mode is managed by
331 *	the PSE controller.
332 */
333
334enum pse_budget_eval_strategies {
335	PSE_BUDGET_EVAL_STRAT_DISABLED	= 1 << 0,
336	PSE_BUDGET_EVAL_STRAT_STATIC	= 1 << 1,
337	PSE_BUDGET_EVAL_STRAT_DYNAMIC	= 1 << 2,
338};
339
340#if IS_ENABLED(CONFIG_PSE_CONTROLLER)
341int pse_controller_register(struct pse_controller_dev *pcdev);
342void pse_controller_unregister(struct pse_controller_dev *pcdev);
343struct device;
344int devm_pse_controller_register(struct device *dev,
345				 struct pse_controller_dev *pcdev);
346int devm_pse_irq_helper(struct pse_controller_dev *pcdev, int irq,
347			int irq_flags, const struct pse_irq_desc *d);
348
349struct pse_control *of_pse_control_get(struct device_node *node,
350				       struct phy_device *phydev);
351void pse_control_put(struct pse_control *psec);
352
353int pse_ethtool_get_status(struct pse_control *psec,
354			   struct netlink_ext_ack *extack,
355			   struct ethtool_pse_control_status *status);
356int pse_ethtool_set_config(struct pse_control *psec,
357			   struct netlink_ext_ack *extack,
358			   const struct pse_control_config *config);
359int pse_ethtool_set_pw_limit(struct pse_control *psec,
360			     struct netlink_ext_ack *extack,
361			     const unsigned int pw_limit);
362int pse_ethtool_set_prio(struct pse_control *psec,
363			 struct netlink_ext_ack *extack,
364			 unsigned int prio);
365
366bool pse_has_podl(struct pse_control *psec);
367bool pse_has_c33(struct pse_control *psec);
368
369#else
370
371static inline struct pse_control *of_pse_control_get(struct device_node *node,
372						     struct phy_device *phydev)
373{
374	return ERR_PTR(-ENOENT);
375}
376
377static inline void pse_control_put(struct pse_control *psec)
378{
379}
380
381static inline int pse_ethtool_get_status(struct pse_control *psec,
382					 struct netlink_ext_ack *extack,
383					 struct ethtool_pse_control_status *status)
384{
385	return -EOPNOTSUPP;
386}
387
388static inline int pse_ethtool_set_config(struct pse_control *psec,
389					 struct netlink_ext_ack *extack,
390					 const struct pse_control_config *config)
391{
392	return -EOPNOTSUPP;
393}
394
395static inline int pse_ethtool_set_pw_limit(struct pse_control *psec,
396					   struct netlink_ext_ack *extack,
397					   const unsigned int pw_limit)
398{
399	return -EOPNOTSUPP;
400}
401
402static inline int pse_ethtool_set_prio(struct pse_control *psec,
403				       struct netlink_ext_ack *extack,
404				       unsigned int prio)
405{
406	return -EOPNOTSUPP;
407}
408
409static inline bool pse_has_podl(struct pse_control *psec)
410{
411	return false;
412}
413
414static inline bool pse_has_c33(struct pse_control *psec)
415{
416	return false;
417}
418
419#endif
420
421#endif