video-pxafb.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 *  Support for the xscale frame buffer.
  4 *
  5 *  Author:     Jean-Frederic Clere
  6 *  Created:    Sep 22, 2003
  7 *  Copyright:  jfclere@sinix.net
  8 */
  9
 10#include <linux/fb.h>
 11
 12/*
 13 * Supported LCD connections
 14 *
 15 * bits 0 - 3: for LCD panel type:
 16 *
 17 *   STN  - for passive matrix
 18 *   DSTN - for dual scan passive matrix
 19 *   TFT  - for active matrix
 20 *
 21 * bits 4 - 9 : for bus width
 22 * bits 10-17 : for AC Bias Pin Frequency
 23 * bit     18 : for output enable polarity
 24 * bit     19 : for pixel clock edge
 25 * bit     20 : for output pixel format when base is RGBT16
 26 */
 27#define LCD_CONN_TYPE(_x)	((_x) & 0x0f)
 28#define LCD_CONN_WIDTH(_x)	(((_x) >> 4) & 0x1f)
 29
 30#define LCD_TYPE_MASK		0xf
 31#define LCD_TYPE_UNKNOWN	0
 32#define LCD_TYPE_MONO_STN	1
 33#define LCD_TYPE_MONO_DSTN	2
 34#define LCD_TYPE_COLOR_STN	3
 35#define LCD_TYPE_COLOR_DSTN	4
 36#define LCD_TYPE_COLOR_TFT	5
 37#define LCD_TYPE_SMART_PANEL	6
 38#define LCD_TYPE_MAX		7
 39
 40#define LCD_MONO_STN_4BPP	((4  << 4) | LCD_TYPE_MONO_STN)
 41#define LCD_MONO_STN_8BPP	((8  << 4) | LCD_TYPE_MONO_STN)
 42#define LCD_MONO_DSTN_8BPP	((8  << 4) | LCD_TYPE_MONO_DSTN)
 43#define LCD_COLOR_STN_8BPP	((8  << 4) | LCD_TYPE_COLOR_STN)
 44#define LCD_COLOR_DSTN_16BPP	((16 << 4) | LCD_TYPE_COLOR_DSTN)
 45#define LCD_COLOR_TFT_8BPP	((8  << 4) | LCD_TYPE_COLOR_TFT)
 46#define LCD_COLOR_TFT_16BPP	((16 << 4) | LCD_TYPE_COLOR_TFT)
 47#define LCD_COLOR_TFT_18BPP	((18 << 4) | LCD_TYPE_COLOR_TFT)
 48#define LCD_SMART_PANEL_8BPP	((8  << 4) | LCD_TYPE_SMART_PANEL)
 49#define LCD_SMART_PANEL_16BPP	((16 << 4) | LCD_TYPE_SMART_PANEL)
 50#define LCD_SMART_PANEL_18BPP	((18 << 4) | LCD_TYPE_SMART_PANEL)
 51
 52#define LCD_AC_BIAS_FREQ(x)	(((x) & 0xff) << 10)
 53#define LCD_BIAS_ACTIVE_HIGH	(0 << 18)
 54#define LCD_BIAS_ACTIVE_LOW	(1 << 18)
 55#define LCD_PCLK_EDGE_RISE	(0 << 19)
 56#define LCD_PCLK_EDGE_FALL	(1 << 19)
 57#define LCD_ALTERNATE_MAPPING	(1 << 20)
 58
 59/*
 60 * This structure describes the machine which we are running on.
 61 * It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine
 62 * of linux/drivers/video/pxafb.c
 63 */
 64struct pxafb_mode_info {
 65	u_long		pixclock;
 66
 67	u_short		xres;
 68	u_short		yres;
 69
 70	u_char		bpp;
 71	u_int		cmap_greyscale:1,
 72			depth:8,
 73			transparency:1,
 74			unused:22;
 75
 76	/* Parallel Mode Timing */
 77	u_char		hsync_len;
 78	u_char		left_margin;
 79	u_char		right_margin;
 80
 81	u_char		vsync_len;
 82	u_char		upper_margin;
 83	u_char		lower_margin;
 84	u_char		sync;
 85
 86	/* Smart Panel Mode Timing - see PXA27x DM 7.4.15.0.3 for details
 87	 * Note:
 88	 * 1. all parameters in nanosecond (ns)
 89	 * 2. a0cs{rd,wr}_set_hld are controlled by the same register bits
 90	 *    in pxa27x and pxa3xx, initialize them to the same value or
 91	 *    the larger one will be used
 92	 * 3. same to {rd,wr}_pulse_width
 93	 *
 94	 * 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity
 95	 * 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0
 96	 * 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD
 97	 */
 98	unsigned	a0csrd_set_hld;	/* A0 and CS Setup/Hold Time before/after L_FCLK_RD */
 99	unsigned	a0cswr_set_hld;	/* A0 and CS Setup/Hold Time before/after L_PCLK_WR */
100	unsigned	wr_pulse_width;	/* L_PCLK_WR pulse width */
101	unsigned	rd_pulse_width;	/* L_FCLK_RD pulse width */
102	unsigned	cmd_inh_time;	/* Command Inhibit time between two writes */
103	unsigned	op_hold_time;	/* Output Hold time from L_FCLK_RD negation */
104};
105
106struct pxafb_mach_info {
107	struct pxafb_mode_info *modes;
108	unsigned int num_modes;
109
110	unsigned int	lcd_conn;
111	unsigned long	video_mem_size;
112
113	u_int		fixed_modes:1,
114			cmap_inverse:1,
115			cmap_static:1,
116			acceleration_enabled:1,
117			unused:28;
118
119	/* The following should be defined in LCCR0
120	 *      LCCR0_Act or LCCR0_Pas          Active or Passive
121	 *      LCCR0_Sngl or LCCR0_Dual        Single/Dual panel
122	 *      LCCR0_Mono or LCCR0_Color       Mono/Color
123	 *      LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode)
124	 *      LCCR0_DMADel(Tcpu) (optional)   DMA request delay
125	 *
126	 * The following should not be defined in LCCR0:
127	 *      LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM
128	 *      LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB
129	 */
130	u_int		lccr0;
131	/* The following should be defined in LCCR3
132	 *      LCCR3_OutEnH or LCCR3_OutEnL    Output enable polarity
133	 *      LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type
134	 *      LCCR3_Acb(X)                    AB Bias pin frequency
135	 *      LCCR3_DPC (optional)            Double Pixel Clock mode (untested)
136	 *
137	 * The following should not be defined in LCCR3
138	 *      LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp
139	 */
140	u_int		lccr3;
141	/* The following should be defined in LCCR4
142	 *	LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2
143	 *
144	 * All other bits in LCCR4 should be left alone.
145	 */
146	u_int		lccr4;
147	void (*pxafb_backlight_power)(int);
148	void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
149	void (*smart_update)(struct fb_info *);
150};
151
152void pxa_set_fb_info(struct device *, struct pxafb_mach_info *);
153
154/* smartpanel related */
155#define SMART_CMD_A0			 (0x1 << 8)
156#define SMART_CMD_READ_STATUS_REG	 (0x0 << 9)
157#define SMART_CMD_READ_FRAME_BUFFER	((0x0 << 9) | SMART_CMD_A0)
158#define SMART_CMD_WRITE_COMMAND		 (0x1 << 9)
159#define SMART_CMD_WRITE_DATA		((0x1 << 9) | SMART_CMD_A0)
160#define SMART_CMD_WRITE_FRAME		((0x2 << 9) | SMART_CMD_A0)
161#define SMART_CMD_WAIT_FOR_VSYNC	 (0x3 << 9)
162#define SMART_CMD_NOOP			 (0x4 << 9)
163#define SMART_CMD_INTERRUPT		 (0x5 << 9)
164
165#define SMART_CMD(x)	(SMART_CMD_WRITE_COMMAND | ((x) & 0xff))
166#define SMART_DAT(x)	(SMART_CMD_WRITE_DATA | ((x) & 0xff))
167
168/* SMART_DELAY() is introduced for software controlled delay primitive which
169 * can be inserted between command sequences, unused command 0x6 is used here
170 * and delay ranges from 0ms ~ 255ms
171 */
172#define SMART_CMD_DELAY		(0x6 << 9)
173#define SMART_DELAY(ms)		(SMART_CMD_DELAY | ((ms) & 0xff))
174
175#ifdef CONFIG_FB_PXA_SMARTPANEL
176extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int);
177extern int pxafb_smart_flush(struct fb_info *info);
178#else
179static inline int pxafb_smart_queue(struct fb_info *info,
180				    uint16_t *cmds, int n)
181{
182	return 0;
183}
184
185static inline int pxafb_smart_flush(struct fb_info *info)
186{
187	return 0;
188}
189#endif