arm_pmu.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 *  linux/arch/arm/include/asm/pmu.h
  4 *
  5 *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
  6 */
  7
  8#ifndef __ARM_PMU_H__
  9#define __ARM_PMU_H__
 10
 11#include <linux/interrupt.h>
 12#include <linux/perf_event.h>
 13#include <linux/platform_device.h>
 14#include <linux/sysfs.h>
 15#include <asm/cputype.h>
 16
 17#ifdef CONFIG_ARM_PMU
 18
 19/*
 20 * The Armv7 and Armv8.8 or less CPU PMU supports up to 32 event counters.
 21 * The Armv8.9/9.4 CPU PMU supports up to 33 event counters.
 22 */
 23#ifdef CONFIG_ARM
 24#define ARMPMU_MAX_HWEVENTS		32
 25#else
 26#define ARMPMU_MAX_HWEVENTS		33
 27#endif
 28/*
 29 * ARM PMU hw_event flags
 30 */
 31#define ARMPMU_EVT_64BIT		0x00001 /* Event uses a 64bit counter */
 32#define ARMPMU_EVT_47BIT		0x00002 /* Event uses a 47bit counter */
 33#define ARMPMU_EVT_63BIT		0x00004 /* Event uses a 63bit counter */
 34
 35static_assert((PERF_EVENT_FLAG_ARCH & ARMPMU_EVT_64BIT) == ARMPMU_EVT_64BIT);
 36static_assert((PERF_EVENT_FLAG_ARCH & ARMPMU_EVT_47BIT) == ARMPMU_EVT_47BIT);
 37static_assert((PERF_EVENT_FLAG_ARCH & ARMPMU_EVT_63BIT) == ARMPMU_EVT_63BIT);
 38
 39#define HW_OP_UNSUPPORTED		0xFFFF
 40#define C(_x)				PERF_COUNT_HW_CACHE_##_x
 41#define CACHE_OP_UNSUPPORTED		0xFFFF
 42
 43#define PERF_MAP_ALL_UNSUPPORTED					\
 44	[0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
 45
 46#define PERF_CACHE_MAP_ALL_UNSUPPORTED					\
 47[0 ... C(MAX) - 1] = {							\
 48	[0 ... C(OP_MAX) - 1] = {					\
 49		[0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED,	\
 50	},								\
 51}
 52
 53/* The events for a given PMU register set. */
 54struct pmu_hw_events {
 55	/*
 56	 * The events that are active on the PMU for the given index.
 57	 */
 58	struct perf_event	*events[ARMPMU_MAX_HWEVENTS];
 59
 60	/*
 61	 * A 1 bit for an index indicates that the counter is being used for
 62	 * an event. A 0 means that the counter can be used.
 63	 */
 64	DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS);
 65
 66	/*
 67	 * When using percpu IRQs, we need a percpu dev_id. Place it here as we
 68	 * already have to allocate this struct per cpu.
 69	 */
 70	struct arm_pmu		*percpu_pmu;
 71
 72	int irq;
 73
 74	struct perf_branch_stack	*branch_stack;
 75
 76	/* Active events requesting branch records */
 77	unsigned int		branch_users;
 78};
 79
 80enum armpmu_attr_groups {
 81	ARMPMU_ATTR_GROUP_COMMON,
 82	ARMPMU_ATTR_GROUP_EVENTS,
 83	ARMPMU_ATTR_GROUP_FORMATS,
 84	ARMPMU_ATTR_GROUP_CAPS,
 85	ARMPMU_NR_ATTR_GROUPS
 86};
 87
 88struct arm_pmu {
 89	struct pmu	pmu;
 90	cpumask_t	supported_cpus;
 91	char		*name;
 92	irqreturn_t	(*handle_irq)(struct arm_pmu *pmu);
 93	void		(*enable)(struct perf_event *event);
 94	void		(*disable)(struct perf_event *event);
 95	int		(*get_event_idx)(struct pmu_hw_events *hw_events,
 96					 struct perf_event *event);
 97	void		(*clear_event_idx)(struct pmu_hw_events *hw_events,
 98					 struct perf_event *event);
 99	int		(*set_event_filter)(struct hw_perf_event *evt,
100					    struct perf_event_attr *attr);
101	u64		(*read_counter)(struct perf_event *event);
102	void		(*write_counter)(struct perf_event *event, u64 val);
103	void		(*start)(struct arm_pmu *);
104	void		(*stop)(struct arm_pmu *);
105	void		(*reset)(void *);
106	int		(*map_event)(struct perf_event *event);
107	/*
108	 * Called by KVM to map the PMUv3 event space onto non-PMUv3 hardware.
109	 */
110	int		(*map_pmuv3_event)(unsigned int eventsel);
111	DECLARE_BITMAP(cntr_mask, ARMPMU_MAX_HWEVENTS);
112	bool		secure_access; /* 32-bit ARM only */
113	struct platform_device	*plat_device;
114	struct pmu_hw_events	__percpu *hw_events;
115	struct hlist_node	node;
116	struct notifier_block	cpu_pm_nb;
117	/* the attr_groups array must be NULL-terminated */
118	const struct attribute_group *attr_groups[ARMPMU_NR_ATTR_GROUPS + 1];
119
120	/* PMUv3 only */
121	int		pmuver;
122	bool		has_smt;
123	u64		reg_pmmir;
124	u64		reg_brbidr;
125#define ARMV8_PMUV3_MAX_COMMON_EVENTS		0x40
126	DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
127#define ARMV8_PMUV3_EXT_COMMON_EVENT_BASE	0x4000
128	DECLARE_BITMAP(pmceid_ext_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
129
130	/* Only to be used by ACPI probing code */
131	unsigned long acpi_cpuid;
132};
133
134#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
135
136u64 armpmu_event_update(struct perf_event *event);
137
138int armpmu_event_set_period(struct perf_event *event);
139
140int armpmu_map_event(struct perf_event *event,
141		     const unsigned (*event_map)[PERF_COUNT_HW_MAX],
142		     const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
143						[PERF_COUNT_HW_CACHE_OP_MAX]
144						[PERF_COUNT_HW_CACHE_RESULT_MAX],
145		     u32 raw_event_mask);
146
147typedef int (*armpmu_init_fn)(struct arm_pmu *);
148
149struct pmu_probe_info {
150	unsigned int cpuid;
151	unsigned int mask;
152	armpmu_init_fn init;
153};
154
155#define PMU_PROBE(_cpuid, _mask, _fn)	\
156{					\
157	.cpuid = (_cpuid),		\
158	.mask = (_mask),		\
159	.init = (_fn),			\
160}
161
162#define ARM_PMU_PROBE(_cpuid, _fn) \
163	PMU_PROBE(_cpuid, ARM_CPU_PART_MASK, _fn)
164
165#define ARM_PMU_XSCALE_MASK	((0xff << 24) | ARM_CPU_XSCALE_ARCH_MASK)
166
167#define XSCALE_PMU_PROBE(_version, _fn) \
168	PMU_PROBE(ARM_CPU_IMP_INTEL << 24 | _version, ARM_PMU_XSCALE_MASK, _fn)
169
170int arm_pmu_device_probe(struct platform_device *pdev,
171			 const struct of_device_id *of_table,
172			 const struct pmu_probe_info *probe_table);
173
174#ifdef CONFIG_ACPI
175int arm_pmu_acpi_probe(armpmu_init_fn init_fn);
176#else
177static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; }
178#endif
179
180#ifdef CONFIG_KVM
181void kvm_host_pmu_init(struct arm_pmu *pmu);
182#else
183#define kvm_host_pmu_init(x)	do { } while(0)
184#endif
185
186bool arm_pmu_irq_is_nmi(void);
187
188/* Internal functions only for core arm_pmu code */
189struct arm_pmu *armpmu_alloc(void);
190void armpmu_free(struct arm_pmu *pmu);
191int armpmu_register(struct arm_pmu *pmu);
192int armpmu_request_irq(struct arm_pmu * __percpu *armpmu, int irq, int cpu);
193void armpmu_free_irq(struct arm_pmu * __percpu *armpmu, int irq, int cpu);
194
195#define ARMV8_PMU_PDEV_NAME "armv8-pmu"
196
197#endif /* CONFIG_ARM_PMU */
198
199#define ARMV8_SPE_PDEV_NAME "arm,spe-v1"
200#define ARMV8_TRBE_PDEV_NAME "arm,trbe"
201
202/* Why does everything I do descend into this? */
203#define __GEN_PMU_FORMAT_ATTR(cfg, lo, hi)				\
204	(lo) == (hi) ? #cfg ":" #lo "\n" : #cfg ":" #lo "-" #hi
205
206#define _GEN_PMU_FORMAT_ATTR(cfg, lo, hi)				\
207	__GEN_PMU_FORMAT_ATTR(cfg, lo, hi)
208
209#define GEN_PMU_FORMAT_ATTR(name)					\
210	PMU_FORMAT_ATTR(name,						\
211	_GEN_PMU_FORMAT_ATTR(ATTR_CFG_FLD_##name##_CFG,			\
212			     ATTR_CFG_FLD_##name##_LO,			\
213			     ATTR_CFG_FLD_##name##_HI))
214
215#define _ATTR_CFG_GET_FLD(attr, cfg, lo, hi)				\
216	((((attr)->cfg) >> lo) & GENMASK_ULL(hi - lo, 0))
217
218#define ATTR_CFG_GET_FLD(attr, name)					\
219	_ATTR_CFG_GET_FLD(attr,						\
220			  ATTR_CFG_FLD_##name##_CFG,			\
221			  ATTR_CFG_FLD_##name##_LO,			\
222			  ATTR_CFG_FLD_##name##_HI)
223
224#endif /* __ARM_PMU_H__ */