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pci.h
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linux-6.19.14/include/linux/pci.h
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz> 8 * 9 * PCI Express ASPM defines and function prototypes 10 * Copyright (c) 2007 Intel Corp. 11 * Zhang Yanmin (yanmin.zhang@intel.com) 12 * Shaohua Li (shaohua.li@intel.com) 13 * 14 * For more information, please consult the following manuals (look at 15 * http://www.pcisig.com/ for how to get them): 16 * 17 * PCI BIOS Specification 18 * PCI Local Bus Specification 19 * PCI to PCI Bridge Specification 20 * PCI Express Specification 21 * PCI System Design Guide 22 */ 23#ifndef LINUX_PCI_H 24#define LINUX_PCI_H 25 26#include <linux/args.h> 27#include <linux/mod_devicetable.h> 28 29#include <linux/types.h> 30#include <linux/init.h> 31#include <linux/ioport.h> 32#include <linux/list.h> 33#include <linux/compiler.h> 34#include <linux/errno.h> 35#include <linux/kobject.h> 36#include <linux/atomic.h> 37#include <linux/device.h> 38#include <linux/interrupt.h> 39#include <linux/io.h> 40#include <linux/resource_ext.h> 41#include <linux/msi_api.h> 42#include <uapi/linux/pci.h> 43 44#include <linux/pci_ids.h> 45 46#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 47 PCI_STATUS_SIG_SYSTEM_ERROR | \ 48 PCI_STATUS_REC_MASTER_ABORT | \ 49 PCI_STATUS_REC_TARGET_ABORT | \ 50 PCI_STATUS_SIG_TARGET_ABORT | \ 51 PCI_STATUS_PARITY) 52 53/* Number of reset methods used in pci_reset_fn_methods array in pci.c */ 54#define PCI_NUM_RESET_METHODS 8 55 56#define PCI_RESET_PROBE true 57#define PCI_RESET_DO_RESET false 58 59/* 60 * The PCI interface treats multi-function devices as independent 61 * devices. The slot/function address of each device is encoded 62 * in a single byte as follows: 63 * 64 * 7:3 = slot 65 * 2:0 = function 66 * 67 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 68 * In the interest of not exposing interfaces to user-space unnecessarily, 69 * the following kernel-only defines are being added here. 70 */ 71#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 72/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 73#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 74 75/* pci_slot represents a physical slot */ 76struct pci_slot { 77 struct pci_bus *bus; /* Bus this slot is on */ 78 struct list_head list; /* Node in list of slots */ 79 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 81 struct kobject kobj; 82}; 83 84static inline const char *pci_slot_name(const struct pci_slot *slot) 85{ 86 return kobject_name(&slot->kobj); 87} 88 89/* File state for mmap()s on /proc/bus/pci/X/Y */ 90enum pci_mmap_state { 91 pci_mmap_io, 92 pci_mmap_mem 93}; 94 95/* For PCI devices, the region numbers are assigned this way: */ 96enum { 97 /* #0-5: standard PCI resources */ 98 PCI_STD_RESOURCES, 99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1, 100 101 /* #6: expansion ROM resource */ 102 PCI_ROM_RESOURCE, 103 104 /* Device-specific resources */ 105#ifdef CONFIG_PCI_IOV 106 PCI_IOV_RESOURCES, 107 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 108#endif 109 110/* PCI-to-PCI (P2P) bridge windows */ 111#define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0) 112#define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1) 113#define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2) 114 115/* CardBus bridge windows */ 116#define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0) 117#define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1) 118#define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2) 119#define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3) 120 121/* Total number of bridge resources for P2P and CardBus */ 122#define PCI_P2P_BRIDGE_RESOURCE_NUM 3 123#define PCI_BRIDGE_RESOURCE_NUM 4 124 125 /* Resources assigned to buses behind the bridge */ 126 PCI_BRIDGE_RESOURCES, 127 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 128 PCI_BRIDGE_RESOURCE_NUM - 1, 129 130 /* Total resources associated with a PCI device */ 131 PCI_NUM_RESOURCES, 132 133 /* Preserve this for compatibility */ 134 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 135}; 136 137/** 138 * enum pci_interrupt_pin - PCI INTx interrupt values 139 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 140 * @PCI_INTERRUPT_INTA: PCI INTA pin 141 * @PCI_INTERRUPT_INTB: PCI INTB pin 142 * @PCI_INTERRUPT_INTC: PCI INTC pin 143 * @PCI_INTERRUPT_INTD: PCI INTD pin 144 * 145 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 146 * PCI_INTERRUPT_PIN register. 147 */ 148enum pci_interrupt_pin { 149 PCI_INTERRUPT_UNKNOWN, 150 PCI_INTERRUPT_INTA, 151 PCI_INTERRUPT_INTB, 152 PCI_INTERRUPT_INTC, 153 PCI_INTERRUPT_INTD, 154}; 155 156/* The number of legacy PCI INTx interrupts */ 157#define PCI_NUM_INTX 4 158 159/* 160 * Reading from a device that doesn't respond typically returns ~0. A 161 * successful read from a device may also return ~0, so you need additional 162 * information to reliably identify errors. 163 */ 164#define PCI_ERROR_RESPONSE (~0ULL) 165#define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) 166#define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) 167 168/* 169 * pci_power_t values must match the bits in the Capabilities PME_Support 170 * and Control/Status PowerState fields in the Power Management capability. 171 */ 172typedef int __bitwise pci_power_t; 173 174#define PCI_D0 ((pci_power_t __force) 0) 175#define PCI_D1 ((pci_power_t __force) 1) 176#define PCI_D2 ((pci_power_t __force) 2) 177#define PCI_D3hot ((pci_power_t __force) 3) 178#define PCI_D3cold ((pci_power_t __force) 4) 179#define PCI_UNKNOWN ((pci_power_t __force) 5) 180#define PCI_POWER_ERROR ((pci_power_t __force) -1) 181 182/* Remember to update this when the list above changes! */ 183extern const char *pci_power_names[]; 184 185static inline const char *pci_power_name(pci_power_t state) 186{ 187 return pci_power_names[1 + (__force int) state]; 188} 189 190/** 191 * typedef pci_channel_state_t 192 * 193 * The pci_channel state describes connectivity between the CPU and 194 * the PCI device. If some PCI bus between here and the PCI device 195 * has crashed or locked up, this info is reflected here. 196 */ 197typedef unsigned int __bitwise pci_channel_state_t; 198 199enum { 200 /* I/O channel is in normal state */ 201 pci_channel_io_normal = (__force pci_channel_state_t) 1, 202 203 /* I/O to channel is blocked */ 204 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 205 206 /* PCI card is dead */ 207 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 208}; 209 210typedef unsigned int __bitwise pcie_reset_state_t; 211 212enum pcie_reset_state { 213 /* Reset is NOT asserted (Use to deassert reset) */ 214 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 215 216 /* Use #PERST to reset PCIe device */ 217 pcie_warm_reset = (__force pcie_reset_state_t) 2, 218 219 /* Use PCIe Hot Reset to reset device */ 220 pcie_hot_reset = (__force pcie_reset_state_t) 3 221}; 222 223typedef unsigned short __bitwise pci_dev_flags_t; 224enum pci_dev_flags { 225 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 226 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 227 /* Device configuration is irrevocably lost if disabled into D3 */ 228 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 229 /* Provide indication device is assigned by a Virtual Machine Manager */ 230 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 231 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 232 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 233 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 234 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 235 /* Do not use bus resets for device */ 236 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 237 /* Do not use PM reset even if device advertises NoSoftRst- */ 238 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 239 /* Get VPD from function 0 VPD */ 240 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 241 /* A non-root bridge where translation occurs, stop alias search here */ 242 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 243 /* Do not use FLR even if device advertises PCI_AF_CAP */ 244 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 245 /* Don't use Relaxed Ordering for TLPs directed at this device */ 246 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 247 /* Device does honor MSI masking despite saying otherwise */ 248 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12), 249 /* Device requires write to PCI_MSIX_ENTRY_DATA before any MSIX reads */ 250 PCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = (__force pci_dev_flags_t) (1 << 13), 251}; 252 253enum pci_irq_reroute_variant { 254 INTEL_IRQ_REROUTE_VARIANT = 1, 255 MAX_IRQ_REROUTE_VARIANTS = 3 256}; 257 258typedef unsigned short __bitwise pci_bus_flags_t; 259enum pci_bus_flags { 260 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 261 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 262 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 263 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 264}; 265 266/* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 267enum pcie_link_width { 268 PCIE_LNK_WIDTH_RESRV = 0x00, 269 PCIE_LNK_X1 = 0x01, 270 PCIE_LNK_X2 = 0x02, 271 PCIE_LNK_X4 = 0x04, 272 PCIE_LNK_X8 = 0x08, 273 PCIE_LNK_X12 = 0x0c, 274 PCIE_LNK_X16 = 0x10, 275 PCIE_LNK_X32 = 0x20, 276 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 277}; 278 279/* See matching string table in pci_speed_string() */ 280enum pci_bus_speed { 281 PCI_SPEED_33MHz = 0x00, 282 PCI_SPEED_66MHz = 0x01, 283 PCI_SPEED_66MHz_PCIX = 0x02, 284 PCI_SPEED_100MHz_PCIX = 0x03, 285 PCI_SPEED_133MHz_PCIX = 0x04, 286 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 287 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 288 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 289 PCI_SPEED_66MHz_PCIX_266 = 0x09, 290 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 291 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 292 AGP_UNKNOWN = 0x0c, 293 AGP_1X = 0x0d, 294 AGP_2X = 0x0e, 295 AGP_4X = 0x0f, 296 AGP_8X = 0x10, 297 PCI_SPEED_66MHz_PCIX_533 = 0x11, 298 PCI_SPEED_100MHz_PCIX_533 = 0x12, 299 PCI_SPEED_133MHz_PCIX_533 = 0x13, 300 PCIE_SPEED_2_5GT = 0x14, 301 PCIE_SPEED_5_0GT = 0x15, 302 PCIE_SPEED_8_0GT = 0x16, 303 PCIE_SPEED_16_0GT = 0x17, 304 PCIE_SPEED_32_0GT = 0x18, 305 PCIE_SPEED_64_0GT = 0x19, 306 PCI_SPEED_UNKNOWN = 0xff, 307}; 308 309enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 310enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 311 312struct pci_vpd { 313 struct mutex lock; 314 unsigned int len; 315 u8 cap; 316}; 317 318struct irq_affinity; 319struct pcie_bwctrl_data; 320struct pcie_link_state; 321struct pci_sriov; 322struct pci_p2pdma; 323struct rcec_ea; 324 325/* struct pci_dev - describes a PCI device 326 * 327 * @supported_speeds: PCIe Supported Link Speeds Vector (+ reserved 0 at 328 * LSB). 0 when the supported speeds cannot be 329 * determined (e.g., for Root Complex Integrated 330 * Endpoints without the relevant Capability 331 * Registers). 332 * @is_hotplug_bridge: Hotplug bridge of any kind (e.g. PCIe Hot-Plug Capable, 333 * Conventional PCI Hot-Plug, ACPI slot). 334 * Such bridges are allocated additional MMIO and bus 335 * number resources to allow for hierarchy expansion. 336 * @is_pciehp: PCIe Hot-Plug Capable bridge. 337 */ 338struct pci_dev { 339 struct list_head bus_list; /* Node in per-bus list */ 340 struct pci_bus *bus; /* Bus this device is on */ 341 struct pci_bus *subordinate; /* Bus this device bridges to */ 342 343 void *sysdata; /* Hook for sys-specific extension */ 344 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 345 struct pci_slot *slot; /* Physical slot this device is in */ 346 347 unsigned int devfn; /* Encoded device & function index */ 348 unsigned short vendor; 349 unsigned short device; 350 unsigned short subsystem_vendor; 351 unsigned short subsystem_device; 352 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 353 u8 revision; /* PCI revision, low byte of class word */ 354 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 355#ifdef CONFIG_PCIEAER 356 u16 aer_cap; /* AER capability offset */ 357 struct aer_info *aer_info; /* AER info for this device */ 358#endif 359#ifdef CONFIG_PCIEPORTBUS 360 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */ 361 struct pci_dev *rcec; /* Associated RCEC device */ 362#endif 363 u32 devcap; /* PCIe Device Capabilities */ 364 u16 rebar_cap; /* Resizable BAR capability offset */ 365 u8 pcie_cap; /* PCIe capability offset */ 366 u8 msi_cap; /* MSI capability offset */ 367 u8 msix_cap; /* MSI-X capability offset */ 368 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 369 u8 rom_base_reg; /* Config register controlling ROM */ 370 u8 pin; /* Interrupt pin this device uses */ 371 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 372 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 373 374 struct pci_driver *driver; /* Driver bound to this device */ 375 u64 dma_mask; /* Mask of the bits of bus address this 376 device implements. Normally this is 377 0xffffffff. You only need to change 378 this if your device has broken DMA 379 or supports 64-bit transfers. */ 380 381 struct device_dma_parameters dma_parms; 382 383 pci_power_t current_state; /* Current operating state. In ACPI, 384 this is D0-D3, D0 being fully 385 functional, and D3 being off. */ 386 u8 pm_cap; /* PM capability offset */ 387 unsigned int pme_support:5; /* Bitmask of states from which PME# 388 can be generated */ 389 unsigned int pme_poll:1; /* Poll device's PME status bit */ 390 unsigned int pinned:1; /* Whether this dev is pinned */ 391 unsigned int config_rrs_sv:1; /* Config RRS software visibility */ 392 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 393 unsigned int d1_support:1; /* Low power state D1 is supported */ 394 unsigned int d2_support:1; /* Low power state D2 is supported */ 395 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 396 unsigned int no_d3cold:1; /* D3cold is forbidden */ 397 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 398 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 399 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 400 decoding during BAR sizing */ 401 unsigned int wakeup_prepared:1; 402 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ 403 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 404 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 405 controlled exclusively by 406 user sysfs */ 407 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link 408 bit manually */ 409 unsigned int no_bw_notif:1; /* BW notifications may cause issues */ 410 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */ 411 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 412 413 u16 l1ss; /* L1SS Capability pointer */ 414#ifdef CONFIG_PCIEASPM 415 struct pcie_link_state *link_state; /* ASPM link state */ 416 unsigned int aspm_l0s_support:1; /* ASPM L0s support */ 417 unsigned int aspm_l1_support:1; /* ASPM L1 support */ 418 unsigned int ltr_path:1; /* Latency Tolerance Reporting 419 supported from root to here */ 420#endif 421 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */ 422 unsigned int eetlp_prefix_max:3; /* Max # of End-End TLP Prefixes, 0=not supported */ 423 424 pci_channel_state_t error_state; /* Current connectivity state */ 425 struct device dev; /* Generic device interface */ 426 427 int cfg_size; /* Size of config space */ 428 429 /* 430 * Instead of touching interrupt line and base address registers 431 * directly, use the values stored here. They might be different! 432 */ 433 unsigned int irq; 434 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 435 struct resource driver_exclusive_resource; /* driver exclusive resource ranges */ 436 437 unsigned int transparent:1; /* Subtractive decode bridge */ 438 unsigned int io_window:1; /* Bridge has I/O window */ 439 unsigned int pref_window:1; /* Bridge has pref mem window */ 440 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ 441 unsigned int multifunction:1; /* Multi-function device */ 442 443 unsigned int is_busmaster:1; /* Is busmaster */ 444 unsigned int no_msi:1; /* May not use MSI */ 445 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 446 unsigned int block_cfg_access:1; /* Config space access blocked */ 447 unsigned int broken_parity_status:1; /* Generates false positive parity */ 448 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 449 unsigned int msi_enabled:1; 450 unsigned int msix_enabled:1; 451 unsigned int ari_enabled:1; /* ARI forwarding */ 452 unsigned int ats_enabled:1; /* Address Translation Svc */ 453 unsigned int pasid_enabled:1; /* Process Address Space ID */ 454 unsigned int pri_enabled:1; /* Page Request Interface */ 455 unsigned int tph_enabled:1; /* TLP Processing Hints */ 456 unsigned int fm_enabled:1; /* Flit Mode (segment captured) */ 457 unsigned int is_managed:1; /* Managed via devres */ 458 unsigned int is_msi_managed:1; /* MSI release via devres installed */ 459 unsigned int needs_freset:1; /* Requires fundamental reset */ 460 unsigned int state_saved:1; 461 unsigned int is_physfn:1; 462 unsigned int is_virtfn:1; 463 unsigned int is_hotplug_bridge:1; 464 unsigned int is_pciehp:1; 465 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 466 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 467 /* 468 * Devices marked being untrusted are the ones that can potentially 469 * execute DMA attacks and similar. They are typically connected 470 * through external ports such as Thunderbolt but not limited to 471 * that. When an IOMMU is enabled they should be getting full 472 * mappings to make sure they cannot access arbitrary memory. 473 */ 474 unsigned int untrusted:1; 475 /* 476 * Info from the platform, e.g., ACPI or device tree, may mark a 477 * device as "external-facing". An external-facing device is 478 * itself internal but devices downstream from it are external. 479 */ 480 unsigned int external_facing:1; 481 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 482 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 483 unsigned int irq_managed:1; 484 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 485 unsigned int is_probed:1; /* Device probing in progress */ 486 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 487 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 488 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */ 489 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */ 490 unsigned int rom_attr_enabled:1; /* Display of ROM attribute enabled? */ 491 unsigned int non_mappable_bars:1; /* BARs can't be mapped to user-space */ 492 pci_dev_flags_t dev_flags; 493 atomic_t enable_cnt; /* pci_enable_device has been called */ 494 495 spinlock_t pcie_cap_lock; /* Protects RMW ops in capability accessors */ 496 u32 saved_config_space[16]; /* Config space saved at suspend time */ 497 struct hlist_head saved_cap_space; 498 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 499 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 500 501#ifdef CONFIG_HOTPLUG_PCI_PCIE 502 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 503#endif 504#ifdef CONFIG_PCIE_PTM 505 u16 ptm_cap; /* PTM Capability */ 506 unsigned int ptm_root:1; 507 unsigned int ptm_responder:1; 508 unsigned int ptm_requester:1; 509 unsigned int ptm_enabled:1; 510 u8 ptm_granularity; 511#endif 512#ifdef CONFIG_PCI_MSI 513 void __iomem *msix_base; 514 raw_spinlock_t msi_lock; 515#endif 516 struct pci_vpd vpd; 517#ifdef CONFIG_PCIE_DPC 518 u16 dpc_cap; 519 unsigned int dpc_rp_extensions:1; 520 u8 dpc_rp_log_size; 521#endif 522 struct pcie_bwctrl_data *link_bwctrl; 523#ifdef CONFIG_PCI_ATS 524 union { 525 struct pci_sriov *sriov; /* PF: SR-IOV info */ 526 struct pci_dev *physfn; /* VF: related PF */ 527 }; 528 u16 ats_cap; /* ATS Capability offset */ 529 u8 ats_stu; /* ATS Smallest Translation Unit */ 530#endif 531#ifdef CONFIG_PCI_PRI 532 u16 pri_cap; /* PRI Capability offset */ 533 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 534 unsigned int pasid_required:1; /* PRG Response PASID Required */ 535#endif 536#ifdef CONFIG_PCI_PASID 537 u16 pasid_cap; /* PASID Capability offset */ 538 u16 pasid_features; 539#endif 540#ifdef CONFIG_PCI_P2PDMA 541 struct pci_p2pdma __rcu *p2pdma; 542#endif 543#ifdef CONFIG_PCI_DOE 544 struct xarray doe_mbs; /* Data Object Exchange mailboxes */ 545#endif 546#ifdef CONFIG_PCI_NPEM 547 struct npem *npem; /* Native PCIe Enclosure Management */ 548#endif 549#ifdef CONFIG_PCI_IDE 550 u16 ide_cap; /* Link Integrity & Data Encryption */ 551 u8 nr_ide_mem; /* Address association resources for streams */ 552 u8 nr_link_ide; /* Link Stream count (Selective Stream offset) */ 553 u16 nr_sel_ide; /* Selective Stream count (register block allocator) */ 554 struct ida ide_stream_ida; 555 unsigned int ide_cfg:1; /* Config cycles over IDE */ 556 unsigned int ide_tee_limit:1; /* Disallow T=0 traffic over IDE */ 557#endif 558#ifdef CONFIG_PCI_TSM 559 struct pci_tsm *tsm; /* TSM operation state */ 560#endif 561 u16 acs_cap; /* ACS Capability offset */ 562 u8 supported_speeds; /* Supported Link Speeds Vector */ 563 phys_addr_t rom; /* Physical address if not from BAR */ 564 size_t romlen; /* Length if not from BAR */ 565 /* 566 * Driver name to force a match. Do not set directly, because core 567 * frees it. Use driver_set_override() to set or clear it. 568 */ 569 const char *driver_override; 570 571 unsigned long priv_flags; /* Private flags for the PCI driver */ 572 573 /* These methods index pci_reset_fn_methods[] */ 574 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */ 575 576#ifdef CONFIG_PCIE_TPH 577 u16 tph_cap; /* TPH capability offset */ 578 u8 tph_mode; /* TPH mode */ 579 u8 tph_req_type; /* TPH requester type */ 580#endif 581}; 582 583static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 584{ 585#ifdef CONFIG_PCI_IOV 586 if (dev->is_virtfn) 587 dev = dev->physfn; 588#endif 589 return dev; 590} 591 592struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 593 594#define to_pci_dev(n) container_of(n, struct pci_dev, dev) 595#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 596#define for_each_pci_dev_reverse(d) \ 597 while ((d = pci_get_device_reverse(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 598 599static inline int pci_channel_offline(struct pci_dev *pdev) 600{ 601 return (pdev->error_state != pci_channel_io_normal); 602} 603 604/* 605 * Currently in ACPI spec, for each PCI host bridge, PCI Segment 606 * Group number is limited to a 16-bit value, therefore (int)-1 is 607 * not a valid PCI domain number, and can be used as a sentinel 608 * value indicating ->domain_nr is not set by the driver (and 609 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with 610 * pci_bus_find_domain_nr()). 611 */ 612#define PCI_DOMAIN_NR_NOT_SET (-1) 613 614struct pci_host_bridge { 615 struct device dev; 616 struct pci_bus *bus; /* Root bus */ 617 struct pci_ops *ops; 618 struct pci_ops *child_ops; 619 void *sysdata; 620 int busnr; 621 int domain_nr; 622 struct list_head windows; /* resource_entry */ 623 struct list_head dma_ranges; /* dma ranges resource list */ 624#ifdef CONFIG_PCI_IDE 625 u16 nr_ide_streams; /* Max streams possibly active in @ide_stream_ida */ 626 struct ida ide_stream_ida; 627 struct ida ide_stream_ids_ida; /* track unique ids per domain */ 628#endif 629 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 630 int (*map_irq)(const struct pci_dev *, u8, u8); 631 void (*release_fn)(struct pci_host_bridge *); 632 int (*enable_device)(struct pci_host_bridge *bridge, struct pci_dev *dev); 633 void (*disable_device)(struct pci_host_bridge *bridge, struct pci_dev *dev); 634 void *release_data; 635 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 636 unsigned int no_ext_tags:1; /* No Extended Tags */ 637 unsigned int no_inc_mrrs:1; /* No Increase MRRS */ 638 unsigned int native_aer:1; /* OS may use PCIe AER */ 639 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 640 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 641 unsigned int native_pme:1; /* OS may use PCIe PME */ 642 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 643 unsigned int native_dpc:1; /* OS may use PCIe DPC */ 644 unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */ 645 unsigned int preserve_config:1; /* Preserve FW resource setup */ 646 unsigned int size_windows:1; /* Enable root bus sizing */ 647 unsigned int msi_domain:1; /* Bridge wants MSI domain */ 648 649 /* Resource alignment requirements */ 650 resource_size_t (*align_resource)(struct pci_dev *dev, 651 const struct resource *res, 652 resource_size_t start, 653 resource_size_t size, 654 resource_size_t align); 655 unsigned long private[] ____cacheline_aligned; 656}; 657 658#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 659 660static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 661{ 662 return (void *)bridge->private; 663} 664 665static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 666{ 667 return container_of(priv, struct pci_host_bridge, private); 668} 669 670struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 671struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 672 size_t priv); 673void pci_free_host_bridge(struct pci_host_bridge *bridge); 674struct device *pci_get_host_bridge_device(struct pci_dev *dev); 675struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 676 677void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 678 void (*release_fn)(struct pci_host_bridge *), 679 void *release_data); 680 681int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 682 683#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 684 685struct pci_bus { 686 struct list_head node; /* Node in list of buses */ 687 struct pci_bus *parent; /* Parent bus this bridge is on */ 688 struct list_head children; /* List of child buses */ 689 struct list_head devices; /* List of devices on this bus */ 690 struct pci_dev *self; /* Bridge device as seen by parent */ 691 struct list_head slots; /* List of slots on this bus; 692 protected by pci_slot_mutex */ 693 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 694 struct list_head resources; /* Address space routed to this bus */ 695 struct resource busn_res; /* Bus numbers routed to this bus */ 696 697 struct pci_ops *ops; /* Configuration access functions */ 698 void *sysdata; /* Hook for sys-specific extension */ 699 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 700 701 unsigned char number; /* Bus number */ 702 unsigned char primary; /* Number of primary bridge */ 703 unsigned char max_bus_speed; /* enum pci_bus_speed */ 704 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 705#ifdef CONFIG_PCI_DOMAINS_GENERIC 706 int domain_nr; 707#endif 708 709 char name[48]; 710 711 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 712 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 713 struct device *bridge; 714 struct device dev; 715 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 716 struct bin_attribute *legacy_mem; /* Legacy mem */ 717 unsigned int is_added:1; 718 unsigned int unsafe_warn:1; /* warned about RW1C config write */ 719 unsigned int flit_mode:1; /* Link in Flit mode */ 720}; 721 722#define to_pci_bus(n) container_of(n, struct pci_bus, dev) 723 724static inline u16 pci_dev_id(struct pci_dev *dev) 725{ 726 return PCI_DEVID(dev->bus->number, dev->devfn); 727} 728 729/* 730 * Returns true if the PCI bus is root (behind host-PCI bridge), 731 * false otherwise 732 * 733 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 734 * This is incorrect because "virtual" buses added for SR-IOV (via 735 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 736 */ 737static inline bool pci_is_root_bus(struct pci_bus *pbus) 738{ 739 return !(pbus->parent); 740} 741 742/** 743 * pci_is_bridge - check if the PCI device is a bridge 744 * @dev: PCI device 745 * 746 * Return true if the PCI device is bridge whether it has subordinate 747 * or not. 748 */ 749static inline bool pci_is_bridge(struct pci_dev *dev) 750{ 751 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 752 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 753} 754 755/** 756 * pci_is_vga - check if the PCI device is a VGA device 757 * @pdev: PCI device 758 * 759 * The PCI Code and ID Assignment spec, r1.15, secs 1.4 and 1.1, define 760 * VGA Base Class and Sub-Classes: 761 * 762 * 03 00 PCI_CLASS_DISPLAY_VGA VGA-compatible or 8514-compatible 763 * 00 01 PCI_CLASS_NOT_DEFINED_VGA VGA-compatible (before Class Code) 764 * 765 * Return true if the PCI device is a VGA device and uses the legacy VGA 766 * resources ([mem 0xa0000-0xbffff], [io 0x3b0-0x3bb], [io 0x3c0-0x3df] and 767 * aliases). 768 */ 769static inline bool pci_is_vga(struct pci_dev *pdev) 770{ 771 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) 772 return true; 773 774 if ((pdev->class >> 8) == PCI_CLASS_NOT_DEFINED_VGA) 775 return true; 776 777 return false; 778} 779 780/** 781 * pci_is_display - check if the PCI device is a display controller 782 * @pdev: PCI device 783 * 784 * Determine whether the given PCI device corresponds to a display 785 * controller. Display controllers are typically used for graphical output 786 * and are identified based on their class code. 787 * 788 * Return: true if the PCI device is a display controller, false otherwise. 789 */ 790static inline bool pci_is_display(struct pci_dev *pdev) 791{ 792 return (pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY; 793} 794 795#define for_each_pci_bridge(dev, bus) \ 796 list_for_each_entry(dev, &bus->devices, bus_list) \ 797 if (!pci_is_bridge(dev)) {} else 798 799static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 800{ 801 dev = pci_physfn(dev); 802 if (pci_is_root_bus(dev->bus)) 803 return NULL; 804 805 return dev->bus->self; 806} 807 808#ifdef CONFIG_PCI_MSI 809static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 810{ 811 return pci_dev->msi_enabled || pci_dev->msix_enabled; 812} 813#else 814static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 815#endif 816 817/* Error values that may be returned by PCI functions */ 818#define PCIBIOS_SUCCESSFUL 0x00 819#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 820#define PCIBIOS_BAD_VENDOR_ID 0x83 821#define PCIBIOS_DEVICE_NOT_FOUND 0x86 822#define PCIBIOS_BAD_REGISTER_NUMBER 0x87 823#define PCIBIOS_SET_FAILED 0x88 824#define PCIBIOS_BUFFER_TOO_SMALL 0x89 825 826/* Translate above to generic errno for passing back through non-PCI code */ 827static inline int pcibios_err_to_errno(int err) 828{ 829 if (err <= PCIBIOS_SUCCESSFUL) 830 return err; /* Assume already errno */ 831 832 switch (err) { 833 case PCIBIOS_FUNC_NOT_SUPPORTED: 834 return -ENOENT; 835 case PCIBIOS_BAD_VENDOR_ID: 836 return -ENOTTY; 837 case PCIBIOS_DEVICE_NOT_FOUND: 838 return -ENODEV; 839 case PCIBIOS_BAD_REGISTER_NUMBER: 840 return -EFAULT; 841 case PCIBIOS_SET_FAILED: 842 return -EIO; 843 case PCIBIOS_BUFFER_TOO_SMALL: 844 return -ENOSPC; 845 } 846 847 return -ERANGE; 848} 849 850/* Low-level architecture-dependent routines */ 851 852struct pci_ops { 853 int (*add_bus)(struct pci_bus *bus); 854 void (*remove_bus)(struct pci_bus *bus); 855 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 856 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 857 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 858 int (*assert_perst)(struct pci_bus *bus, bool assert); 859}; 860 861/* 862 * ACPI needs to be able to access PCI config space before we've done a 863 * PCI bus scan and created pci_bus structures. 864 */ 865int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 866 int reg, int len, u32 *val); 867int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 868 int reg, int len, u32 val); 869 870#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 871typedef u64 pci_bus_addr_t; 872#else 873typedef u32 pci_bus_addr_t; 874#endif 875 876struct pci_bus_region { 877 pci_bus_addr_t start; 878 pci_bus_addr_t end; 879}; 880 881static inline pci_bus_addr_t pci_bus_region_size(const struct pci_bus_region *region) 882{ 883 return region->end - region->start + 1; 884} 885 886struct pci_dynids { 887 spinlock_t lock; /* Protects list, index */ 888 struct list_head list; /* For IDs added at runtime */ 889}; 890 891 892/* 893 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 894 * a set of callbacks in struct pci_error_handlers, that device driver 895 * will be notified of PCI bus errors, and will be driven to recovery 896 * when an error occurs. 897 */ 898 899typedef unsigned int __bitwise pci_ers_result_t; 900 901enum pci_ers_result { 902 /* No result/none/not supported in device driver */ 903 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 904 905 /* Device driver can recover without slot reset */ 906 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 907 908 /* Device driver wants slot to be reset */ 909 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 910 911 /* Device has completely failed, is unrecoverable */ 912 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 913 914 /* Device driver is fully recovered and operational */ 915 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 916 917 /* No AER capabilities registered for the driver */ 918 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 919}; 920 921/* PCI bus error event callbacks */ 922struct pci_error_handlers { 923 /* PCI bus error detected on this device */ 924 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 925 pci_channel_state_t error); 926 927 /* MMIO has been re-enabled, but not DMA */ 928 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 929 930 /* PCI slot has been reset */ 931 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 932 933 /* PCI function reset prepare or completed */ 934 void (*reset_prepare)(struct pci_dev *dev); 935 void (*reset_done)(struct pci_dev *dev); 936 937 /* Device driver may resume normal operations */ 938 void (*resume)(struct pci_dev *dev); 939 940 /* Allow device driver to record more details of a correctable error */ 941 void (*cor_error_detected)(struct pci_dev *dev); 942}; 943 944 945struct module; 946 947/** 948 * struct pci_driver - PCI driver structure 949 * @name: Driver name. 950 * @id_table: Pointer to table of device IDs the driver is 951 * interested in. Most drivers should export this 952 * table using MODULE_DEVICE_TABLE(pci,...). 953 * @probe: This probing function gets called (during execution 954 * of pci_register_driver() for already existing 955 * devices or later if a new device gets inserted) for 956 * all PCI devices which match the ID table and are not 957 * "owned" by the other drivers yet. This function gets 958 * passed a "struct pci_dev \*" for each device whose 959 * entry in the ID table matches the device. The probe 960 * function returns zero when the driver chooses to 961 * take "ownership" of the device or an error code 962 * (negative number) otherwise. 963 * The probe function always gets called from process 964 * context, so it can sleep. 965 * @remove: The remove() function gets called whenever a device 966 * being handled by this driver is removed (either during 967 * deregistration of the driver or when it's manually 968 * pulled out of a hot-pluggable slot). 969 * The remove function always gets called from process 970 * context, so it can sleep. 971 * @suspend: Put device into low power state. 972 * @resume: Wake device from low power state. 973 * (Please see Documentation/power/pci.rst for descriptions 974 * of PCI Power Management and the related functions.) 975 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). 976 * Intended to stop any idling DMA operations. 977 * Useful for enabling wake-on-lan (NIC) or changing 978 * the power state of a device before reboot. 979 * e.g. drivers/net/e100.c. 980 * @sriov_configure: Optional driver callback to allow configuration of 981 * number of VFs to enable via sysfs "sriov_numvfs" file. 982 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X 983 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count". 984 * This will change MSI-X Table Size in the VF Message Control 985 * registers. 986 * @sriov_get_vf_total_msix: PF driver callback to get the total number of 987 * MSI-X vectors available for distribution to the VFs. 988 * @err_handler: See Documentation/PCI/pci-error-recovery.rst 989 * @groups: Sysfs attribute groups. 990 * @dev_groups: Attributes attached to the device that will be 991 * created once it is bound to the driver. 992 * @driver: Driver model structure. 993 * @dynids: List of dynamically added device IDs. 994 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA. 995 * For most device drivers, no need to care about this flag 996 * as long as all DMAs are handled through the kernel DMA API. 997 * For some special ones, for example VFIO drivers, they know 998 * how to manage the DMA themselves and set this flag so that 999 * the IOMMU layer will allow them to setup and manage their 1000 * own I/O address space. 1001 */ 1002struct pci_driver { 1003 const char *name; 1004 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 1005 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 1006 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 1007 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 1008 int (*resume)(struct pci_dev *dev); /* Device woken up */ 1009 void (*shutdown)(struct pci_dev *dev); 1010 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 1011 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */ 1012 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf); 1013 const struct pci_error_handlers *err_handler; 1014 const struct attribute_group **groups; 1015 const struct attribute_group **dev_groups; 1016 struct device_driver driver; 1017 struct pci_dynids dynids; 1018 bool driver_managed_dma; 1019}; 1020 1021#define to_pci_driver(__drv) \ 1022 ( __drv ? container_of_const(__drv, struct pci_driver, driver) : NULL ) 1023 1024/** 1025 * PCI_DEVICE - macro used to describe a specific PCI device 1026 * @vend: the 16 bit PCI Vendor ID 1027 * @dev: the 16 bit PCI Device ID 1028 * 1029 * This macro is used to create a struct pci_device_id that matches a 1030 * specific device. The subvendor and subdevice fields will be set to 1031 * PCI_ANY_ID. 1032 */ 1033#define PCI_DEVICE(vend,dev) \ 1034 .vendor = (vend), .device = (dev), \ 1035 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1036 1037/** 1038 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with 1039 * override_only flags. 1040 * @vend: the 16 bit PCI Vendor ID 1041 * @dev: the 16 bit PCI Device ID 1042 * @driver_override: the 32 bit PCI Device override_only 1043 * 1044 * This macro is used to create a struct pci_device_id that matches only a 1045 * driver_override device. The subvendor and subdevice fields will be set to 1046 * PCI_ANY_ID. 1047 */ 1048#define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \ 1049 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \ 1050 .subdevice = PCI_ANY_ID, .override_only = (driver_override) 1051 1052/** 1053 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO 1054 * "driver_override" PCI device. 1055 * @vend: the 16 bit PCI Vendor ID 1056 * @dev: the 16 bit PCI Device ID 1057 * 1058 * This macro is used to create a struct pci_device_id that matches a 1059 * specific device. The subvendor and subdevice fields will be set to 1060 * PCI_ANY_ID and the driver_override will be set to 1061 * PCI_ID_F_VFIO_DRIVER_OVERRIDE. 1062 */ 1063#define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \ 1064 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE) 1065 1066/** 1067 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 1068 * @vend: the 16 bit PCI Vendor ID 1069 * @dev: the 16 bit PCI Device ID 1070 * @subvend: the 16 bit PCI Subvendor ID 1071 * @subdev: the 16 bit PCI Subdevice ID 1072 * 1073 * This macro is used to create a struct pci_device_id that matches a 1074 * specific device with subsystem information. 1075 */ 1076#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 1077 .vendor = (vend), .device = (dev), \ 1078 .subvendor = (subvend), .subdevice = (subdev) 1079 1080/** 1081 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 1082 * @dev_class: the class, subclass, prog-if triple for this device 1083 * @dev_class_mask: the class mask for this device 1084 * 1085 * This macro is used to create a struct pci_device_id that matches a 1086 * specific PCI class. The vendor, device, subvendor, and subdevice 1087 * fields will be set to PCI_ANY_ID. 1088 */ 1089#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 1090 .class = (dev_class), .class_mask = (dev_class_mask), \ 1091 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 1092 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1093 1094/** 1095 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 1096 * @vend: the vendor name 1097 * @dev: the 16 bit PCI Device ID 1098 * 1099 * This macro is used to create a struct pci_device_id that matches a 1100 * specific PCI device. The subvendor, and subdevice fields will be set 1101 * to PCI_ANY_ID. The macro allows the next field to follow as the device 1102 * private data. 1103 */ 1104#define PCI_VDEVICE(vend, dev) \ 1105 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1106 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 1107 1108/** 1109 * PCI_VDEVICE_SUB - describe a specific PCI device/subdevice in a short form 1110 * @vend: the vendor name 1111 * @dev: the 16 bit PCI Device ID 1112 * @subvend: the 16 bit PCI Subvendor ID 1113 * @subdev: the 16 bit PCI Subdevice ID 1114 * 1115 * Generate the pci_device_id struct layout for the specific PCI 1116 * device/subdevice. Private data may follow the output. 1117 */ 1118#define PCI_VDEVICE_SUB(vend, dev, subvend, subdev) \ 1119 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1120 .subvendor = (subvend), .subdevice = (subdev), 0, 0 1121 1122/** 1123 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 1124 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 1125 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 1126 * @data: the driver data to be filled 1127 * 1128 * This macro is used to create a struct pci_device_id that matches a 1129 * specific PCI device. The subvendor, and subdevice fields will be set 1130 * to PCI_ANY_ID. 1131 */ 1132#define PCI_DEVICE_DATA(vend, dev, data) \ 1133 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 1134 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 1135 .driver_data = (kernel_ulong_t)(data) 1136 1137enum { 1138 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 1139 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 1140 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 1141 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 1142 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 1143 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 1144 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 1145}; 1146 1147#define PCI_IRQ_INTX (1 << 0) /* Allow INTx interrupts */ 1148#define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 1149#define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 1150#define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 1151 1152/* These external functions are only available when PCI support is enabled */ 1153#ifdef CONFIG_PCI 1154 1155extern unsigned int pci_flags; 1156 1157static inline void pci_set_flags(int flags) { pci_flags = flags; } 1158static inline void pci_add_flags(int flags) { pci_flags |= flags; } 1159static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 1160static inline int pci_has_flag(int flag) { return pci_flags & flag; } 1161 1162void pcie_bus_configure_settings(struct pci_bus *bus); 1163 1164enum pcie_bus_config_types { 1165 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 1166 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 1167 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 1168 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 1169 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 1170}; 1171 1172extern enum pcie_bus_config_types pcie_bus_config; 1173 1174extern const struct bus_type pci_bus_type; 1175 1176/* Do NOT directly access these two variables, unless you are arch-specific PCI 1177 * code, or PCI core code. */ 1178extern struct list_head pci_root_buses; /* List of all known PCI buses */ 1179/* Some device drivers need know if PCI is initiated */ 1180int no_pci_devices(void); 1181 1182void pcibios_resource_survey_bus(struct pci_bus *bus); 1183void pcibios_bus_add_device(struct pci_dev *pdev); 1184void pcibios_add_bus(struct pci_bus *bus); 1185void pcibios_remove_bus(struct pci_bus *bus); 1186void pcibios_fixup_bus(struct pci_bus *); 1187int __must_check pcibios_enable_device(struct pci_dev *, int mask); 1188/* Architecture-specific versions may override this (weak) */ 1189char *pcibios_setup(char *str); 1190 1191/* Used only when drivers/pci/setup.c is used */ 1192resource_size_t pcibios_align_resource(void *, const struct resource *, 1193 resource_size_t, 1194 resource_size_t); 1195 1196/* Generic PCI functions used internally */ 1197 1198void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 1199 struct resource *res); 1200void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 1201 struct pci_bus_region *region); 1202void pcibios_scan_specific_bus(int busn); 1203struct pci_bus *pci_find_bus(int domain, int busnr); 1204void pci_bus_add_devices(const struct pci_bus *bus); 1205struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 1206struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 1207 struct pci_ops *ops, void *sysdata, 1208 struct list_head *resources); 1209int pci_host_probe(struct pci_host_bridge *bridge); 1210int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 1211int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 1212void pci_bus_release_busn_res(struct pci_bus *b); 1213struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 1214 struct pci_ops *ops, void *sysdata, 1215 struct list_head *resources); 1216int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 1217struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1218 int busnr); 1219struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 1220 const char *name, 1221 struct hotplug_slot *hotplug); 1222void pci_destroy_slot(struct pci_slot *slot); 1223#ifdef CONFIG_SYSFS 1224void pci_dev_assign_slot(struct pci_dev *dev); 1225#else 1226static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 1227#endif 1228int pci_scan_slot(struct pci_bus *bus, int devfn); 1229struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 1230void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 1231unsigned int pci_scan_child_bus(struct pci_bus *bus); 1232void pci_bus_add_device(struct pci_dev *dev); 1233void pci_read_bridge_bases(struct pci_bus *child); 1234struct resource *pci_find_parent_resource(const struct pci_dev *dev, 1235 struct resource *res); 1236u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 1237int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 1238u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 1239struct pci_dev *pci_dev_get(struct pci_dev *dev); 1240void pci_dev_put(struct pci_dev *dev); 1241DEFINE_FREE(pci_dev_put, struct pci_dev *, if (_T) pci_dev_put(_T)) 1242void pci_remove_bus(struct pci_bus *b); 1243void pci_stop_and_remove_bus_device(struct pci_dev *dev); 1244void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 1245void pci_stop_root_bus(struct pci_bus *bus); 1246void pci_remove_root_bus(struct pci_bus *bus); 1247void pci_setup_cardbus(struct pci_bus *bus); 1248void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 1249void pci_sort_breadthfirst(void); 1250#define dev_is_pci(d) ((d)->bus == &pci_bus_type) 1251#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 1252 1253/* Generic PCI functions exported to card drivers */ 1254 1255u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1256u8 pci_find_capability(struct pci_dev *dev, int cap); 1257u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 1258u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 1259u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap); 1260u16 pci_find_ext_capability(struct pci_dev *dev, int cap); 1261u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap); 1262struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 1263u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap); 1264u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec); 1265 1266u64 pci_get_dsn(struct pci_dev *dev); 1267 1268struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 1269 struct pci_dev *from); 1270struct pci_dev *pci_get_device_reverse(unsigned int vendor, unsigned int device, 1271 struct pci_dev *from); 1272struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 1273 unsigned int ss_vendor, unsigned int ss_device, 1274 struct pci_dev *from); 1275struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 1276struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 1277 unsigned int devfn); 1278struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 1279struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from); 1280 1281int pci_dev_present(const struct pci_device_id *ids); 1282 1283int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1284 int where, u8 *val); 1285int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1286 int where, u16 *val); 1287int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1288 int where, u32 *val); 1289int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1290 int where, u8 val); 1291int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1292 int where, u16 val); 1293int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1294 int where, u32 val); 1295 1296int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1297 int where, int size, u32 *val); 1298int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1299 int where, int size, u32 val); 1300int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1301 int where, int size, u32 *val); 1302int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1303 int where, int size, u32 val); 1304 1305struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1306 1307int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1308int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1309int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1310int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1311int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1312int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1313void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos, 1314 u32 clear, u32 set); 1315 1316int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1317int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1318int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1319int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1320int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos, 1321 u16 clear, u16 set); 1322int pcie_capability_clear_and_set_word_locked(struct pci_dev *dev, int pos, 1323 u16 clear, u16 set); 1324int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1325 u32 clear, u32 set); 1326 1327/** 1328 * pcie_capability_clear_and_set_word - RMW accessor for PCI Express Capability Registers 1329 * @dev: PCI device structure of the PCI Express device 1330 * @pos: PCI Express Capability Register 1331 * @clear: Clear bitmask 1332 * @set: Set bitmask 1333 * 1334 * Perform a Read-Modify-Write (RMW) operation using @clear and @set 1335 * bitmasks on PCI Express Capability Register at @pos. Certain PCI Express 1336 * Capability Registers are accessed concurrently in RMW fashion, hence 1337 * require locking which is handled transparently to the caller. 1338 */ 1339static inline int pcie_capability_clear_and_set_word(struct pci_dev *dev, 1340 int pos, 1341 u16 clear, u16 set) 1342{ 1343 switch (pos) { 1344 case PCI_EXP_LNKCTL: 1345 case PCI_EXP_LNKCTL2: 1346 case PCI_EXP_RTCTL: 1347 return pcie_capability_clear_and_set_word_locked(dev, pos, 1348 clear, set); 1349 default: 1350 return pcie_capability_clear_and_set_word_unlocked(dev, pos, 1351 clear, set); 1352 } 1353} 1354 1355static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1356 u16 set) 1357{ 1358 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1359} 1360 1361static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1362 u32 set) 1363{ 1364 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1365} 1366 1367static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1368 u16 clear) 1369{ 1370 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1371} 1372 1373static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1374 u32 clear) 1375{ 1376 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1377} 1378 1379/* User-space driven config access */ 1380int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1381int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1382int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1383int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1384int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1385int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1386 1387int __must_check pci_enable_device(struct pci_dev *dev); 1388int __must_check pci_enable_device_mem(struct pci_dev *dev); 1389int __must_check pci_reenable_device(struct pci_dev *); 1390int __must_check pcim_enable_device(struct pci_dev *pdev); 1391void pcim_pin_device(struct pci_dev *pdev); 1392 1393static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1394{ 1395 /* 1396 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1397 * writable and no quirk has marked the feature broken. 1398 */ 1399 return !pdev->broken_intx_masking; 1400} 1401 1402static inline int pci_is_enabled(struct pci_dev *pdev) 1403{ 1404 return (atomic_read(&pdev->enable_cnt) > 0); 1405} 1406 1407static inline int pci_is_managed(struct pci_dev *pdev) 1408{ 1409 return pdev->is_managed; 1410} 1411 1412void pci_disable_device(struct pci_dev *dev); 1413 1414extern unsigned int pcibios_max_latency; 1415void pci_set_master(struct pci_dev *dev); 1416void pci_clear_master(struct pci_dev *dev); 1417 1418int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1419int pci_set_cacheline_size(struct pci_dev *dev); 1420int __must_check pci_set_mwi(struct pci_dev *dev); 1421int __must_check pcim_set_mwi(struct pci_dev *dev); 1422int pci_try_set_mwi(struct pci_dev *dev); 1423void pci_clear_mwi(struct pci_dev *dev); 1424void pci_disable_parity(struct pci_dev *dev); 1425void pci_intx(struct pci_dev *dev, int enable); 1426bool pci_check_and_mask_intx(struct pci_dev *dev); 1427bool pci_check_and_unmask_intx(struct pci_dev *dev); 1428int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1429int pci_wait_for_pending_transaction(struct pci_dev *dev); 1430int pcix_get_max_mmrbc(struct pci_dev *dev); 1431int pcix_get_mmrbc(struct pci_dev *dev); 1432int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1433int pcie_get_readrq(struct pci_dev *dev); 1434int pcie_set_readrq(struct pci_dev *dev, int rq); 1435int pcie_get_mps(struct pci_dev *dev); 1436int pcie_set_mps(struct pci_dev *dev, int mps); 1437u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1438 enum pci_bus_speed *speed, 1439 enum pcie_link_width *width); 1440int pcie_link_speed_mbps(struct pci_dev *pdev); 1441void pcie_print_link_status(struct pci_dev *dev); 1442int pcie_reset_flr(struct pci_dev *dev, bool probe); 1443int pcie_flr(struct pci_dev *dev); 1444int __pci_reset_function_locked(struct pci_dev *dev); 1445int pci_reset_function(struct pci_dev *dev); 1446int pci_reset_function_locked(struct pci_dev *dev); 1447int pci_try_reset_function(struct pci_dev *dev); 1448int pci_probe_reset_slot(struct pci_slot *slot); 1449int pci_probe_reset_bus(struct pci_bus *bus); 1450int pci_reset_bus(struct pci_dev *dev); 1451void pci_reset_secondary_bus(struct pci_dev *dev); 1452void pcibios_reset_secondary_bus(struct pci_dev *dev); 1453void pci_update_resource(struct pci_dev *dev, int resno); 1454int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1455int pci_release_resource(struct pci_dev *dev, int resno); 1456 1457/* Resizable BAR related routines */ 1458int pci_rebar_bytes_to_size(u64 bytes); 1459resource_size_t pci_rebar_size_to_bytes(int size); 1460u64 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); 1461bool pci_rebar_size_supported(struct pci_dev *pdev, int bar, int size); 1462int pci_rebar_get_max_size(struct pci_dev *pdev, int bar); 1463int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size, 1464 int exclude_bars); 1465 1466int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1467bool pci_device_is_present(struct pci_dev *pdev); 1468void pci_ignore_hotplug(struct pci_dev *dev); 1469struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); 1470int pci_status_get_and_clear_errors(struct pci_dev *pdev); 1471 1472int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1473 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1474 const char *fmt, ...); 1475void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1476 1477/* ROM control related routines */ 1478int pci_enable_rom(struct pci_dev *pdev); 1479void pci_disable_rom(struct pci_dev *pdev); 1480void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1481void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1482 1483/* Power management related routines */ 1484int pci_save_state(struct pci_dev *dev); 1485void pci_restore_state(struct pci_dev *dev); 1486struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1487int pci_load_saved_state(struct pci_dev *dev, 1488 struct pci_saved_state *state); 1489int pci_load_and_free_saved_state(struct pci_dev *dev, 1490 struct pci_saved_state **state); 1491int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state); 1492int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1493int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state); 1494pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1495bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1496void pci_pme_active(struct pci_dev *dev, bool enable); 1497int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1498int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1499int pci_prepare_to_sleep(struct pci_dev *dev); 1500int pci_back_from_sleep(struct pci_dev *dev); 1501bool pci_dev_run_wake(struct pci_dev *dev); 1502void pci_d3cold_enable(struct pci_dev *dev); 1503void pci_d3cold_disable(struct pci_dev *dev); 1504bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1505void pci_resume_bus(struct pci_bus *bus); 1506void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1507 1508/* For use by arch with custom probe code */ 1509void set_pcie_port_type(struct pci_dev *pdev); 1510void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1511 1512/* Functions for PCI Hotplug drivers to use */ 1513unsigned int pci_rescan_bus(struct pci_bus *bus); 1514void pci_lock_rescan_remove(void); 1515void pci_unlock_rescan_remove(void); 1516 1517/* Vital Product Data routines */ 1518ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1519ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1520ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1521ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1522 1523/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1524resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1525void pci_bus_assign_resources(const struct pci_bus *bus); 1526void pci_bus_claim_resources(struct pci_bus *bus); 1527void pci_bus_size_bridges(struct pci_bus *bus); 1528int pci_claim_resource(struct pci_dev *, int); 1529int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1530void pci_assign_unassigned_resources(void); 1531void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1532void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1533void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1534int pci_enable_resources(struct pci_dev *, int mask); 1535void pci_assign_irq(struct pci_dev *dev); 1536struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1537#define HAVE_PCI_REQ_REGIONS 2 1538int __must_check pci_request_regions(struct pci_dev *, const char *); 1539int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1540void pci_release_regions(struct pci_dev *); 1541int __must_check pci_request_region(struct pci_dev *, int, const char *); 1542void pci_release_region(struct pci_dev *, int); 1543int pci_request_selected_regions(struct pci_dev *, int, const char *); 1544int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1545void pci_release_selected_regions(struct pci_dev *, int); 1546 1547static inline __must_check struct resource * 1548pci_request_config_region_exclusive(struct pci_dev *pdev, unsigned int offset, 1549 unsigned int len, const char *name) 1550{ 1551 return __request_region(&pdev->driver_exclusive_resource, offset, len, 1552 name, IORESOURCE_EXCLUSIVE); 1553} 1554 1555static inline void pci_release_config_region(struct pci_dev *pdev, 1556 unsigned int offset, 1557 unsigned int len) 1558{ 1559 __release_region(&pdev->driver_exclusive_resource, offset, len); 1560} 1561 1562/* drivers/pci/bus.c */ 1563void pci_add_resource(struct list_head *resources, struct resource *res); 1564void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1565 resource_size_t offset); 1566void pci_free_resource_list(struct list_head *resources); 1567void pci_bus_add_resource(struct pci_bus *bus, struct resource *res); 1568struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1569void pci_bus_remove_resources(struct pci_bus *bus); 1570void pci_bus_remove_resource(struct pci_bus *bus, struct resource *res); 1571int devm_request_pci_bus_resources(struct device *dev, 1572 struct list_head *resources); 1573 1574/* Temporary until new and working PCI SBR API in place */ 1575int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1576 1577#define __pci_bus_for_each_res0(bus, res, ...) \ 1578 for (unsigned int __b = 0; \ 1579 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \ 1580 __b++) 1581 1582#define __pci_bus_for_each_res1(bus, res, __b) \ 1583 for (__b = 0; \ 1584 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \ 1585 __b++) 1586 1587/** 1588 * pci_bus_for_each_resource - iterate over PCI bus resources 1589 * @bus: the PCI bus 1590 * @res: pointer to the current resource 1591 * @...: optional index of the current resource 1592 * 1593 * Iterate over PCI bus resources. The first part is to go over PCI bus 1594 * resource array, which has at most the %PCI_BRIDGE_RESOURCE_NUM entries. 1595 * After that continue with the separate list of the additional resources, 1596 * if not empty. That's why the Logical OR is being used. 1597 * 1598 * Possible usage: 1599 * 1600 * struct pci_bus *bus = ...; 1601 * struct resource *res; 1602 * unsigned int i; 1603 * 1604 * // With optional index 1605 * pci_bus_for_each_resource(bus, res, i) 1606 * pr_info("PCI bus resource[%u]: %pR\n", i, res); 1607 * 1608 * // Without index 1609 * pci_bus_for_each_resource(bus, res) 1610 * _do_something_(res); 1611 */ 1612#define pci_bus_for_each_resource(bus, res, ...) \ 1613 CONCATENATE(__pci_bus_for_each_res, COUNT_ARGS(__VA_ARGS__)) \ 1614 (bus, res, __VA_ARGS__) 1615 1616int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1617 struct resource *res, resource_size_t size, 1618 resource_size_t align, resource_size_t min, 1619 unsigned long type_mask, 1620 resource_alignf alignf, 1621 void *alignf_data); 1622 1623 1624int pci_register_io_range(const struct fwnode_handle *fwnode, phys_addr_t addr, 1625 resource_size_t size); 1626unsigned long pci_address_to_pio(phys_addr_t addr); 1627phys_addr_t pci_pio_to_address(unsigned long pio); 1628int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1629int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1630 phys_addr_t phys_addr); 1631void pci_unmap_iospace(struct resource *res); 1632void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1633 resource_size_t offset, 1634 resource_size_t size); 1635void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1636 struct resource *res); 1637 1638static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1639{ 1640 struct pci_bus_region region; 1641 1642 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1643 return region.start; 1644} 1645 1646/* Proper probing supporting hot-pluggable devices */ 1647int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1648 const char *mod_name); 1649 1650/* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1651#define pci_register_driver(driver) \ 1652 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1653 1654void pci_unregister_driver(struct pci_driver *dev); 1655 1656/** 1657 * module_pci_driver() - Helper macro for registering a PCI driver 1658 * @__pci_driver: pci_driver struct 1659 * 1660 * Helper macro for PCI drivers which do not do anything special in module 1661 * init/exit. This eliminates a lot of boilerplate. Each module may only 1662 * use this macro once, and calling it replaces module_init() and module_exit() 1663 */ 1664#define module_pci_driver(__pci_driver) \ 1665 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1666 1667/** 1668 * builtin_pci_driver() - Helper macro for registering a PCI driver 1669 * @__pci_driver: pci_driver struct 1670 * 1671 * Helper macro for PCI drivers which do not do anything special in their 1672 * init code. This eliminates a lot of boilerplate. Each driver may only 1673 * use this macro once, and calling it replaces device_initcall(...) 1674 */ 1675#define builtin_pci_driver(__pci_driver) \ 1676 builtin_driver(__pci_driver, pci_register_driver) 1677 1678struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1679int pci_add_dynid(struct pci_driver *drv, 1680 unsigned int vendor, unsigned int device, 1681 unsigned int subvendor, unsigned int subdevice, 1682 unsigned int class, unsigned int class_mask, 1683 unsigned long driver_data); 1684const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1685 struct pci_dev *dev); 1686int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1687 int pass); 1688 1689void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1690 void *userdata); 1691void pci_walk_bus_reverse(struct pci_bus *top, 1692 int (*cb)(struct pci_dev *, void *), void *userdata); 1693int pci_cfg_space_size(struct pci_dev *dev); 1694unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1695resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1696 unsigned long type); 1697 1698#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1699#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1700 1701int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1702 unsigned int command_bits, u32 flags); 1703 1704/* 1705 * Virtual interrupts allow for more interrupts to be allocated 1706 * than the device has interrupts for. These are not programmed 1707 * into the device's MSI-X table and must be handled by some 1708 * other driver means. 1709 */ 1710#define PCI_IRQ_VIRTUAL (1 << 4) 1711 1712#define PCI_IRQ_ALL_TYPES (PCI_IRQ_INTX | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1713 1714#include <linux/dmapool.h> 1715 1716struct msix_entry { 1717 u32 vector; /* Kernel uses to write allocated vector */ 1718 u16 entry; /* Driver uses to specify entry, OS writes */ 1719}; 1720 1721#ifdef CONFIG_PCI_MSI 1722int pci_msi_vec_count(struct pci_dev *dev); 1723void pci_disable_msi(struct pci_dev *dev); 1724int pci_msix_vec_count(struct pci_dev *dev); 1725void pci_disable_msix(struct pci_dev *dev); 1726void pci_restore_msi_state(struct pci_dev *dev); 1727bool pci_msi_enabled(void); 1728int pci_enable_msi(struct pci_dev *dev); 1729int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1730 int minvec, int maxvec); 1731static inline int pci_enable_msix_exact(struct pci_dev *dev, 1732 struct msix_entry *entries, int nvec) 1733{ 1734 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1735 if (rc < 0) 1736 return rc; 1737 return 0; 1738} 1739int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1740 unsigned int max_vecs, unsigned int flags); 1741int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1742 unsigned int max_vecs, unsigned int flags, 1743 struct irq_affinity *affd); 1744 1745bool pci_msix_can_alloc_dyn(struct pci_dev *dev); 1746struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, 1747 const struct irq_affinity_desc *affdesc); 1748void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map); 1749 1750void pci_free_irq_vectors(struct pci_dev *dev); 1751int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1752const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1753 1754#else 1755static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1756static inline void pci_disable_msi(struct pci_dev *dev) { } 1757static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1758static inline void pci_disable_msix(struct pci_dev *dev) { } 1759static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1760static inline bool pci_msi_enabled(void) { return false; } 1761static inline int pci_enable_msi(struct pci_dev *dev) 1762{ return -ENOSYS; } 1763static inline int pci_enable_msix_range(struct pci_dev *dev, 1764 struct msix_entry *entries, int minvec, int maxvec) 1765{ return -ENOSYS; } 1766static inline int pci_enable_msix_exact(struct pci_dev *dev, 1767 struct msix_entry *entries, int nvec) 1768{ return -ENOSYS; } 1769 1770static inline int 1771pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1772 unsigned int max_vecs, unsigned int flags, 1773 struct irq_affinity *aff_desc) 1774{ 1775 if ((flags & PCI_IRQ_INTX) && min_vecs == 1 && dev->irq) 1776 return 1; 1777 return -ENOSPC; 1778} 1779static inline int 1780pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1781 unsigned int max_vecs, unsigned int flags) 1782{ 1783 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, 1784 flags, NULL); 1785} 1786 1787static inline bool pci_msix_can_alloc_dyn(struct pci_dev *dev) 1788{ return false; } 1789static inline struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, 1790 const struct irq_affinity_desc *affdesc) 1791{ 1792 struct msi_map map = { .index = -ENOSYS, }; 1793 1794 return map; 1795} 1796 1797static inline void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map) 1798{ 1799} 1800 1801static inline void pci_free_irq_vectors(struct pci_dev *dev) 1802{ 1803} 1804 1805static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1806{ 1807 if (WARN_ON_ONCE(nr > 0)) 1808 return -EINVAL; 1809 return dev->irq; 1810} 1811static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1812 int vec) 1813{ 1814 return cpu_possible_mask; 1815} 1816#endif 1817 1818/** 1819 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1820 * @d: the INTx IRQ domain 1821 * @node: the DT node for the device whose interrupt we're translating 1822 * @intspec: the interrupt specifier data from the DT 1823 * @intsize: the number of entries in @intspec 1824 * @out_hwirq: pointer at which to write the hwirq number 1825 * @out_type: pointer at which to write the interrupt type 1826 * 1827 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1828 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1829 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1830 * INTx value to obtain the hwirq number. 1831 * 1832 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1833 */ 1834static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1835 struct device_node *node, 1836 const u32 *intspec, 1837 unsigned int intsize, 1838 unsigned long *out_hwirq, 1839 unsigned int *out_type) 1840{ 1841 const u32 intx = intspec[0]; 1842 1843 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1844 return -EINVAL; 1845 1846 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1847 return 0; 1848} 1849 1850#ifdef CONFIG_PCIEPORTBUS 1851extern bool pcie_ports_disabled; 1852extern bool pcie_ports_native; 1853 1854int pcie_set_target_speed(struct pci_dev *port, enum pci_bus_speed speed_req, 1855 bool use_lt); 1856#else 1857#define pcie_ports_disabled true 1858#define pcie_ports_native false 1859 1860static inline int pcie_set_target_speed(struct pci_dev *port, 1861 enum pci_bus_speed speed_req, 1862 bool use_lt) 1863{ 1864 return -EOPNOTSUPP; 1865} 1866#endif 1867 1868#define PCIE_LINK_STATE_L0S (BIT(0) | BIT(1)) /* Upstr/dwnstr L0s */ 1869#define PCIE_LINK_STATE_L1 BIT(2) /* L1 state */ 1870#define PCIE_LINK_STATE_L1_1 BIT(3) /* ASPM L1.1 state */ 1871#define PCIE_LINK_STATE_L1_2 BIT(4) /* ASPM L1.2 state */ 1872#define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) /* PCI-PM L1.1 state */ 1873#define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) /* PCI-PM L1.2 state */ 1874#define PCIE_LINK_STATE_ASPM_ALL (PCIE_LINK_STATE_L0S |\ 1875 PCIE_LINK_STATE_L1 |\ 1876 PCIE_LINK_STATE_L1_1 |\ 1877 PCIE_LINK_STATE_L1_2 |\ 1878 PCIE_LINK_STATE_L1_1_PCIPM |\ 1879 PCIE_LINK_STATE_L1_2_PCIPM) 1880#define PCIE_LINK_STATE_CLKPM BIT(7) 1881#define PCIE_LINK_STATE_ALL (PCIE_LINK_STATE_ASPM_ALL |\ 1882 PCIE_LINK_STATE_CLKPM) 1883 1884#ifdef CONFIG_PCIEASPM 1885int pci_disable_link_state(struct pci_dev *pdev, int state); 1886int pci_disable_link_state_locked(struct pci_dev *pdev, int state); 1887int pci_enable_link_state(struct pci_dev *pdev, int state); 1888int pci_enable_link_state_locked(struct pci_dev *pdev, int state); 1889void pcie_no_aspm(void); 1890bool pcie_aspm_support_enabled(void); 1891bool pcie_aspm_enabled(struct pci_dev *pdev); 1892#else 1893static inline int pci_disable_link_state(struct pci_dev *pdev, int state) 1894{ return 0; } 1895static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state) 1896{ return 0; } 1897static inline int pci_enable_link_state(struct pci_dev *pdev, int state) 1898{ return 0; } 1899static inline int pci_enable_link_state_locked(struct pci_dev *pdev, int state) 1900{ return 0; } 1901static inline void pcie_no_aspm(void) { } 1902static inline bool pcie_aspm_support_enabled(void) { return false; } 1903static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } 1904#endif 1905 1906#ifdef CONFIG_HOTPLUG_PCI 1907void pci_hp_ignore_link_change(struct pci_dev *pdev); 1908void pci_hp_unignore_link_change(struct pci_dev *pdev); 1909#else 1910static inline void pci_hp_ignore_link_change(struct pci_dev *pdev) { } 1911static inline void pci_hp_unignore_link_change(struct pci_dev *pdev) { } 1912#endif 1913 1914#ifdef CONFIG_PCIEAER 1915bool pci_aer_available(void); 1916#else 1917static inline bool pci_aer_available(void) { return false; } 1918#endif 1919 1920bool pci_ats_disabled(void); 1921 1922#define PCIE_PTM_CONTEXT_UPDATE_AUTO 0 1923#define PCIE_PTM_CONTEXT_UPDATE_MANUAL 1 1924 1925struct pcie_ptm_ops { 1926 int (*check_capability)(void *drvdata); 1927 int (*context_update_write)(void *drvdata, u8 mode); 1928 int (*context_update_read)(void *drvdata, u8 *mode); 1929 int (*context_valid_write)(void *drvdata, bool valid); 1930 int (*context_valid_read)(void *drvdata, bool *valid); 1931 int (*local_clock_read)(void *drvdata, u64 *clock); 1932 int (*master_clock_read)(void *drvdata, u64 *clock); 1933 int (*t1_read)(void *drvdata, u64 *clock); 1934 int (*t2_read)(void *drvdata, u64 *clock); 1935 int (*t3_read)(void *drvdata, u64 *clock); 1936 int (*t4_read)(void *drvdata, u64 *clock); 1937 1938 bool (*context_update_visible)(void *drvdata); 1939 bool (*context_valid_visible)(void *drvdata); 1940 bool (*local_clock_visible)(void *drvdata); 1941 bool (*master_clock_visible)(void *drvdata); 1942 bool (*t1_visible)(void *drvdata); 1943 bool (*t2_visible)(void *drvdata); 1944 bool (*t3_visible)(void *drvdata); 1945 bool (*t4_visible)(void *drvdata); 1946}; 1947 1948struct pci_ptm_debugfs { 1949 struct dentry *debugfs; 1950 const struct pcie_ptm_ops *ops; 1951 struct mutex lock; 1952 void *pdata; 1953}; 1954 1955#ifdef CONFIG_PCIE_PTM 1956int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1957void pci_disable_ptm(struct pci_dev *dev); 1958bool pcie_ptm_enabled(struct pci_dev *dev); 1959#else 1960static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1961{ return -EINVAL; } 1962static inline void pci_disable_ptm(struct pci_dev *dev) { } 1963static inline bool pcie_ptm_enabled(struct pci_dev *dev) 1964{ return false; } 1965#endif 1966 1967#if IS_ENABLED(CONFIG_DEBUG_FS) && IS_ENABLED(CONFIG_PCIE_PTM) 1968struct pci_ptm_debugfs *pcie_ptm_create_debugfs(struct device *dev, void *pdata, 1969 const struct pcie_ptm_ops *ops); 1970void pcie_ptm_destroy_debugfs(struct pci_ptm_debugfs *ptm_debugfs); 1971#else 1972static inline struct pci_ptm_debugfs 1973*pcie_ptm_create_debugfs(struct device *dev, void *pdata, 1974 const struct pcie_ptm_ops *ops) { return NULL; } 1975static inline void 1976pcie_ptm_destroy_debugfs(struct pci_ptm_debugfs *ptm_debugfs) { } 1977#endif 1978 1979void pci_cfg_access_lock(struct pci_dev *dev); 1980bool pci_cfg_access_trylock(struct pci_dev *dev); 1981void pci_cfg_access_unlock(struct pci_dev *dev); 1982 1983void pci_dev_lock(struct pci_dev *dev); 1984int pci_dev_trylock(struct pci_dev *dev); 1985void pci_dev_unlock(struct pci_dev *dev); 1986DEFINE_GUARD(pci_dev, struct pci_dev *, pci_dev_lock(_T), pci_dev_unlock(_T)) 1987 1988/* 1989 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1990 * a PCI domain is defined to be a set of PCI buses which share 1991 * configuration space. 1992 */ 1993#ifdef CONFIG_PCI_DOMAINS 1994extern int pci_domains_supported; 1995int pci_bus_find_emul_domain_nr(u32 hint, u32 min, u32 max); 1996void pci_bus_release_emul_domain_nr(int domain_nr); 1997#else 1998enum { pci_domains_supported = 0 }; 1999static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 2000static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 2001static inline int pci_bus_find_emul_domain_nr(u32 hint, u32 min, u32 max) 2002{ 2003 return 0; 2004} 2005static inline void pci_bus_release_emul_domain_nr(int domain_nr) { } 2006#endif /* CONFIG_PCI_DOMAINS */ 2007 2008/* 2009 * Generic implementation for PCI domain support. If your 2010 * architecture does not need custom management of PCI 2011 * domains then this implementation will be used 2012 */ 2013#ifdef CONFIG_PCI_DOMAINS_GENERIC 2014static inline int pci_domain_nr(struct pci_bus *bus) 2015{ 2016 return bus->domain_nr; 2017} 2018#ifdef CONFIG_ACPI 2019int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 2020#else 2021static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 2022{ return 0; } 2023#endif 2024int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 2025void pci_bus_release_domain_nr(struct device *parent, int domain_nr); 2026#endif 2027 2028/* Some architectures require additional setup to direct VGA traffic */ 2029typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 2030 unsigned int command_bits, u32 flags); 2031void pci_register_set_vga_state(arch_set_vga_state_t func); 2032 2033static inline int 2034pci_request_io_regions(struct pci_dev *pdev, const char *name) 2035{ 2036 return pci_request_selected_regions(pdev, 2037 pci_select_bars(pdev, IORESOURCE_IO), name); 2038} 2039 2040static inline void 2041pci_release_io_regions(struct pci_dev *pdev) 2042{ 2043 return pci_release_selected_regions(pdev, 2044 pci_select_bars(pdev, IORESOURCE_IO)); 2045} 2046 2047static inline int 2048pci_request_mem_regions(struct pci_dev *pdev, const char *name) 2049{ 2050 return pci_request_selected_regions(pdev, 2051 pci_select_bars(pdev, IORESOURCE_MEM), name); 2052} 2053 2054static inline void 2055pci_release_mem_regions(struct pci_dev *pdev) 2056{ 2057 return pci_release_selected_regions(pdev, 2058 pci_select_bars(pdev, IORESOURCE_MEM)); 2059} 2060 2061#else /* CONFIG_PCI is not enabled */ 2062 2063static inline void pci_set_flags(int flags) { } 2064static inline void pci_add_flags(int flags) { } 2065static inline void pci_clear_flags(int flags) { } 2066static inline int pci_has_flag(int flag) { return 0; } 2067 2068/* 2069 * If the system does not have PCI, clearly these return errors. Define 2070 * these as simple inline functions to avoid hair in drivers. 2071 */ 2072#define _PCI_NOP(o, s, t) \ 2073 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 2074 int where, t val) \ 2075 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 2076 2077#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 2078 _PCI_NOP(o, word, u16 x) \ 2079 _PCI_NOP(o, dword, u32 x) 2080_PCI_NOP_ALL(read, *) 2081_PCI_NOP_ALL(write,) 2082 2083static inline struct pci_dev *pci_get_device(unsigned int vendor, 2084 unsigned int device, 2085 struct pci_dev *from) 2086{ return NULL; } 2087 2088static inline struct pci_dev *pci_get_device_reverse(unsigned int vendor, 2089 unsigned int device, 2090 struct pci_dev *from) 2091{ return NULL; } 2092 2093static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 2094 unsigned int device, 2095 unsigned int ss_vendor, 2096 unsigned int ss_device, 2097 struct pci_dev *from) 2098{ return NULL; } 2099 2100static inline struct pci_dev *pci_get_class(unsigned int class, 2101 struct pci_dev *from) 2102{ return NULL; } 2103 2104static inline struct pci_dev *pci_get_base_class(unsigned int class, 2105 struct pci_dev *from) 2106{ return NULL; } 2107 2108static inline int pci_dev_present(const struct pci_device_id *ids) 2109{ return 0; } 2110 2111#define no_pci_devices() (1) 2112#define pci_dev_put(dev) do { } while (0) 2113 2114static inline void pci_set_master(struct pci_dev *dev) { } 2115static inline void pci_clear_master(struct pci_dev *dev) { } 2116static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 2117static inline void pci_disable_device(struct pci_dev *dev) { } 2118static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; } 2119static inline int pci_assign_resource(struct pci_dev *dev, int i) 2120{ return -EBUSY; } 2121static inline int __must_check __pci_register_driver(struct pci_driver *drv, 2122 struct module *owner, 2123 const char *mod_name) 2124{ return 0; } 2125static inline int pci_register_driver(struct pci_driver *drv) 2126{ return 0; } 2127static inline void pci_unregister_driver(struct pci_driver *drv) { } 2128static inline u8 pci_find_capability(struct pci_dev *dev, int cap) 2129{ return 0; } 2130static inline u8 pci_find_next_capability(struct pci_dev *dev, u8 post, int cap) 2131{ return 0; } 2132static inline u16 pci_find_ext_capability(struct pci_dev *dev, int cap) 2133{ return 0; } 2134 2135static inline u64 pci_get_dsn(struct pci_dev *dev) 2136{ return 0; } 2137 2138/* Power management related routines */ 2139static inline int pci_save_state(struct pci_dev *dev) { return 0; } 2140static inline void pci_restore_state(struct pci_dev *dev) { } 2141static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 2142{ return 0; } 2143static inline int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state) 2144{ return 0; } 2145static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 2146{ return 0; } 2147static inline pci_power_t pci_choose_state(struct pci_dev *dev, 2148 pm_message_t state) 2149{ return PCI_D0; } 2150static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 2151 int enable) 2152{ return 0; } 2153 2154static inline struct resource *pci_find_resource(struct pci_dev *dev, 2155 struct resource *res) 2156{ return NULL; } 2157static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 2158{ return -EIO; } 2159static inline void pci_release_regions(struct pci_dev *dev) { } 2160 2161static inline int pci_register_io_range(const struct fwnode_handle *fwnode, 2162 phys_addr_t addr, resource_size_t size) 2163{ return -EINVAL; } 2164 2165static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 2166 2167static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 2168{ return NULL; } 2169static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 2170 unsigned int devfn) 2171{ return NULL; } 2172static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 2173 unsigned int bus, unsigned int devfn) 2174{ return NULL; } 2175 2176static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 2177static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 2178 2179#define dev_is_pci(d) (false) 2180#define dev_is_pf(d) (false) 2181static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 2182{ return false; } 2183static inline int pci_irqd_intx_xlate(struct irq_domain *d, 2184 struct device_node *node, 2185 const u32 *intspec, 2186 unsigned int intsize, 2187 unsigned long *out_hwirq, 2188 unsigned int *out_type) 2189{ return -EINVAL; } 2190 2191static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 2192 struct pci_dev *dev) 2193{ return NULL; } 2194static inline bool pci_ats_disabled(void) { return true; } 2195 2196static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 2197{ 2198 return -EINVAL; 2199} 2200 2201static inline int 2202pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 2203 unsigned int max_vecs, unsigned int flags, 2204 struct irq_affinity *aff_desc) 2205{ 2206 return -ENOSPC; 2207} 2208static inline int 2209pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 2210 unsigned int max_vecs, unsigned int flags) 2211{ 2212 return -ENOSPC; 2213} 2214 2215static inline void pci_free_irq_vectors(struct pci_dev *dev) 2216{ 2217} 2218#endif /* CONFIG_PCI */ 2219 2220/* Include architecture-dependent settings and functions */ 2221 2222#include <asm/pci.h> 2223 2224/* 2225 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 2226 * is expected to be an offset within that region. 2227 * 2228 */ 2229int pci_mmap_resource_range(struct pci_dev *dev, int bar, 2230 struct vm_area_struct *vma, 2231 enum pci_mmap_state mmap_state, int write_combine); 2232 2233#ifndef arch_can_pci_mmap_wc 2234#define arch_can_pci_mmap_wc() 0 2235#endif 2236 2237#ifndef arch_can_pci_mmap_io 2238#define arch_can_pci_mmap_io() 0 2239#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 2240#else 2241int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 2242#endif 2243 2244#ifndef pci_root_bus_fwnode 2245#define pci_root_bus_fwnode(bus) NULL 2246#endif 2247 2248/* 2249 * These helpers provide future and backwards compatibility 2250 * for accessing popular PCI BAR info 2251 */ 2252#define pci_resource_n(dev, bar) (&(dev)->resource[(bar)]) 2253#define pci_resource_start(dev, bar) (pci_resource_n(dev, bar)->start) 2254#define pci_resource_end(dev, bar) (pci_resource_n(dev, bar)->end) 2255#define pci_resource_flags(dev, bar) (pci_resource_n(dev, bar)->flags) 2256#define pci_resource_len(dev,bar) \ 2257 (pci_resource_end((dev), (bar)) ? \ 2258 resource_size(pci_resource_n((dev), (bar))) : 0) 2259 2260#define __pci_dev_for_each_res0(dev, res, ...) \ 2261 for (unsigned int __b = 0; \ 2262 __b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \ 2263 __b++) 2264 2265#define __pci_dev_for_each_res1(dev, res, __b) \ 2266 for (__b = 0; \ 2267 __b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \ 2268 __b++) 2269 2270#define pci_dev_for_each_resource(dev, res, ...) \ 2271 CONCATENATE(__pci_dev_for_each_res, COUNT_ARGS(__VA_ARGS__)) \ 2272 (dev, res, __VA_ARGS__) 2273 2274/* 2275 * Similar to the helpers above, these manipulate per-pci_dev 2276 * driver-specific data. They are really just a wrapper around 2277 * the generic device structure functions of these calls. 2278 */ 2279static inline void *pci_get_drvdata(struct pci_dev *pdev) 2280{ 2281 return dev_get_drvdata(&pdev->dev); 2282} 2283 2284static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 2285{ 2286 dev_set_drvdata(&pdev->dev, data); 2287} 2288 2289static inline const char *pci_name(const struct pci_dev *pdev) 2290{ 2291 return dev_name(&pdev->dev); 2292} 2293 2294void pci_resource_to_user(const struct pci_dev *dev, int bar, 2295 const struct resource *rsrc, 2296 resource_size_t *start, resource_size_t *end); 2297 2298/* 2299 * The world is not perfect and supplies us with broken PCI devices. 2300 * For at least a part of these bugs we need a work-around, so both 2301 * generic (drivers/pci/quirks.c) and per-architecture code can define 2302 * fixup hooks to be called for particular buggy devices. 2303 */ 2304 2305struct pci_fixup { 2306 u16 vendor; /* Or PCI_ANY_ID */ 2307 u16 device; /* Or PCI_ANY_ID */ 2308 u32 class; /* Or PCI_ANY_ID */ 2309 unsigned int class_shift; /* should be 0, 8, 16 */ 2310#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 2311 int hook_offset; 2312#else 2313 void (*hook)(struct pci_dev *dev); 2314#endif 2315}; 2316 2317enum pci_fixup_pass { 2318 pci_fixup_early, /* Before probing BARs */ 2319 pci_fixup_header, /* After reading configuration header */ 2320 pci_fixup_final, /* Final phase of device fixups */ 2321 pci_fixup_enable, /* pci_enable_device() time */ 2322 pci_fixup_resume, /* pci_device_resume() */ 2323 pci_fixup_suspend, /* pci_device_suspend() */ 2324 pci_fixup_resume_early, /* pci_device_resume_early() */ 2325 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 2326}; 2327 2328#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 2329#define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2330 class_shift, hook) \ 2331 __ADDRESSABLE(hook) \ 2332 asm(".section " #sec ", \"a\" \n" \ 2333 ".balign 16 \n" \ 2334 ".short " #vendor ", " #device " \n" \ 2335 ".long " #class ", " #class_shift " \n" \ 2336 ".long " #hook " - . \n" \ 2337 ".previous \n"); 2338 2339/* 2340 * Clang's LTO may rename static functions in C, but has no way to 2341 * handle such renamings when referenced from inline asm. To work 2342 * around this, create global C stubs for these cases. 2343 */ 2344#ifdef CONFIG_LTO_CLANG 2345#define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2346 class_shift, hook, stub) \ 2347 void stub(struct pci_dev *dev); \ 2348 void stub(struct pci_dev *dev) \ 2349 { \ 2350 hook(dev); \ 2351 } \ 2352 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2353 class_shift, stub) 2354#else 2355#define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2356 class_shift, hook, stub) \ 2357 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2358 class_shift, hook) 2359#endif 2360 2361#define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2362 class_shift, hook) \ 2363 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2364 class_shift, hook, __UNIQUE_ID(hook)) 2365#else 2366/* Anonymous variables would be nice... */ 2367#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 2368 class_shift, hook) \ 2369 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 2370 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 2371 = { vendor, device, class, class_shift, hook }; 2372#endif 2373 2374#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 2375 class_shift, hook) \ 2376 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2377 hook, vendor, device, class, class_shift, hook) 2378#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 2379 class_shift, hook) \ 2380 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2381 hook, vendor, device, class, class_shift, hook) 2382#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 2383 class_shift, hook) \ 2384 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2385 hook, vendor, device, class, class_shift, hook) 2386#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 2387 class_shift, hook) \ 2388 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2389 hook, vendor, device, class, class_shift, hook) 2390#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 2391 class_shift, hook) \ 2392 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2393 resume##hook, vendor, device, class, class_shift, hook) 2394#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 2395 class_shift, hook) \ 2396 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2397 resume_early##hook, vendor, device, class, class_shift, hook) 2398#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 2399 class_shift, hook) \ 2400 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2401 suspend##hook, vendor, device, class, class_shift, hook) 2402#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 2403 class_shift, hook) \ 2404 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2405 suspend_late##hook, vendor, device, class, class_shift, hook) 2406 2407#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 2408 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2409 hook, vendor, device, PCI_ANY_ID, 0, hook) 2410#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 2411 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2412 hook, vendor, device, PCI_ANY_ID, 0, hook) 2413#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 2414 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2415 hook, vendor, device, PCI_ANY_ID, 0, hook) 2416#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 2417 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2418 hook, vendor, device, PCI_ANY_ID, 0, hook) 2419#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 2420 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2421 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 2422#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 2423 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2424 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 2425#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 2426 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2427 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 2428#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 2429 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2430 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 2431 2432#ifdef CONFIG_PCI_QUIRKS 2433void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 2434#else 2435static inline void pci_fixup_device(enum pci_fixup_pass pass, 2436 struct pci_dev *dev) { } 2437#endif 2438 2439int pcim_intx(struct pci_dev *pdev, int enabled); 2440int pcim_request_all_regions(struct pci_dev *pdev, const char *name); 2441void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 2442void __iomem *pcim_iomap_region(struct pci_dev *pdev, int bar, 2443 const char *name); 2444void pcim_iounmap_region(struct pci_dev *pdev, int bar); 2445void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 2446void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 2447int pcim_request_region(struct pci_dev *pdev, int bar, const char *name); 2448int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 2449void __iomem *pcim_iomap_range(struct pci_dev *pdev, int bar, 2450 unsigned long offset, unsigned long len); 2451 2452extern int pci_pci_problems; 2453#define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 2454#define PCIPCI_TRITON 2 2455#define PCIPCI_NATOMA 4 2456#define PCIPCI_VIAETBF 8 2457#define PCIPCI_VSFX 16 2458#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 2459#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 2460 2461extern u8 pci_dfl_cache_line_size; 2462extern u8 pci_cache_line_size; 2463 2464/* Architecture-specific versions may override these (weak) */ 2465void pcibios_disable_device(struct pci_dev *dev); 2466void pcibios_set_master(struct pci_dev *dev); 2467int pcibios_set_pcie_reset_state(struct pci_dev *dev, 2468 enum pcie_reset_state state); 2469int pcibios_device_add(struct pci_dev *dev); 2470void pcibios_release_device(struct pci_dev *dev); 2471#ifdef CONFIG_PCI 2472void pcibios_penalize_isa_irq(int irq, int active); 2473#else 2474static inline void pcibios_penalize_isa_irq(int irq, int active) {} 2475#endif 2476int pcibios_alloc_irq(struct pci_dev *dev); 2477void pcibios_free_irq(struct pci_dev *dev); 2478resource_size_t pcibios_default_alignment(void); 2479 2480#if !defined(HAVE_PCI_MMAP) && !defined(ARCH_GENERIC_PCI_MMAP_RESOURCE) 2481extern int pci_create_resource_files(struct pci_dev *dev); 2482extern void pci_remove_resource_files(struct pci_dev *dev); 2483#endif 2484 2485#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 2486void __init pci_mmcfg_early_init(void); 2487void __init pci_mmcfg_late_init(void); 2488#else 2489static inline void pci_mmcfg_early_init(void) { } 2490static inline void pci_mmcfg_late_init(void) { } 2491#endif 2492 2493int pci_ext_cfg_avail(void); 2494 2495void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 2496void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 2497 2498#ifdef CONFIG_PCI_IOV 2499int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2500int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2501int pci_iov_vf_id(struct pci_dev *dev); 2502void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver); 2503int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2504void pci_disable_sriov(struct pci_dev *dev); 2505 2506int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id); 2507int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2508void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2509int pci_num_vf(struct pci_dev *dev); 2510int pci_vfs_assigned(struct pci_dev *dev); 2511int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2512int pci_sriov_get_totalvfs(struct pci_dev *dev); 2513int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2514resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 2515int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size); 2516u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs); 2517void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2518 2519/* Arch may override these (weak) */ 2520int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2521int pcibios_sriov_disable(struct pci_dev *pdev); 2522resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 2523#else 2524static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2525{ 2526 return -ENOSYS; 2527} 2528static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2529{ 2530 return -ENOSYS; 2531} 2532 2533static inline int pci_iov_vf_id(struct pci_dev *dev) 2534{ 2535 return -ENOSYS; 2536} 2537 2538static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev, 2539 struct pci_driver *pf_driver) 2540{ 2541 return ERR_PTR(-EINVAL); 2542} 2543 2544static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2545{ return -ENODEV; } 2546 2547static inline int pci_iov_sysfs_link(struct pci_dev *dev, 2548 struct pci_dev *virtfn, int id) 2549{ 2550 return -ENODEV; 2551} 2552static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2553{ 2554 return -ENOSYS; 2555} 2556static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2557 int id) { } 2558static inline void pci_disable_sriov(struct pci_dev *dev) { } 2559static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2560static inline int pci_vfs_assigned(struct pci_dev *dev) 2561{ return 0; } 2562static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2563{ return 0; } 2564static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 2565{ return 0; } 2566#define pci_sriov_configure_simple NULL 2567static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 2568{ return 0; } 2569static inline int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size) 2570{ return -ENODEV; } 2571static inline u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs) 2572{ return 0; } 2573static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2574#endif 2575 2576/** 2577 * pci_pcie_cap - get the saved PCIe capability offset 2578 * @dev: PCI device 2579 * 2580 * PCIe capability offset is calculated at PCI device initialization 2581 * time and saved in the data structure. This function returns saved 2582 * PCIe capability offset. Using this instead of pci_find_capability() 2583 * reduces unnecessary search in the PCI configuration space. If you 2584 * need to calculate PCIe capability offset from raw device for some 2585 * reasons, please use pci_find_capability() instead. 2586 */ 2587static inline int pci_pcie_cap(struct pci_dev *dev) 2588{ 2589 return dev->pcie_cap; 2590} 2591 2592/** 2593 * pci_is_pcie - check if the PCI device is PCI Express capable 2594 * @dev: PCI device 2595 * 2596 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2597 */ 2598static inline bool pci_is_pcie(struct pci_dev *dev) 2599{ 2600 return pci_pcie_cap(dev); 2601} 2602 2603/** 2604 * pcie_caps_reg - get the PCIe Capabilities Register 2605 * @dev: PCI device 2606 */ 2607static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2608{ 2609 return dev->pcie_flags_reg; 2610} 2611 2612/** 2613 * pci_pcie_type - get the PCIe device/port type 2614 * @dev: PCI device 2615 */ 2616static inline int pci_pcie_type(const struct pci_dev *dev) 2617{ 2618 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2619} 2620 2621/** 2622 * pcie_find_root_port - Get the PCIe root port device 2623 * @dev: PCI device 2624 * 2625 * Traverse up the parent chain and return the PCIe Root Port PCI Device 2626 * for a given PCI/PCIe Device. 2627 */ 2628static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2629{ 2630 while (dev) { 2631 if (pci_is_pcie(dev) && 2632 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2633 return dev; 2634 dev = pci_upstream_bridge(dev); 2635 } 2636 2637 return NULL; 2638} 2639 2640static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) 2641{ 2642 /* 2643 * error_state is set in pci_dev_set_io_state() using xchg/cmpxchg() 2644 * and read w/o common lock. READ_ONCE() ensures compiler cannot cache 2645 * the value (e.g. inside the loop in pci_dev_wait()). 2646 */ 2647 return READ_ONCE(dev->error_state) == pci_channel_io_perm_failure; 2648} 2649 2650void pci_request_acs(void); 2651bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2652bool pci_acs_path_enabled(struct pci_dev *start, 2653 struct pci_dev *end, u16 acs_flags); 2654int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2655 2656#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2657#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2658 2659/* Large Resource Data Type Tag Item Names */ 2660#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2661#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2662#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2663 2664#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2665#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2666#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2667 2668#define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2669#define PCI_VPD_RO_KEYWORD_SERIALNO "SN" 2670#define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2671#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2672#define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2673 2674/** 2675 * pci_vpd_alloc - Allocate buffer and read VPD into it 2676 * @dev: PCI device 2677 * @size: pointer to field where VPD length is returned 2678 * 2679 * Returns pointer to allocated buffer or an ERR_PTR in case of failure 2680 */ 2681void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size); 2682 2683/** 2684 * pci_vpd_find_id_string - Locate id string in VPD 2685 * @buf: Pointer to buffered VPD data 2686 * @len: The length of the buffer area in which to search 2687 * @size: Pointer to field where length of id string is returned 2688 * 2689 * Returns the index of the id string or -ENOENT if not found. 2690 */ 2691int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size); 2692 2693/** 2694 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section 2695 * @buf: Pointer to buffered VPD data 2696 * @len: The length of the buffer area in which to search 2697 * @kw: The keyword to search for 2698 * @size: Pointer to field where length of found keyword data is returned 2699 * 2700 * Returns the index of the information field keyword data or -ENOENT if 2701 * not found. 2702 */ 2703int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len, 2704 const char *kw, unsigned int *size); 2705 2706/** 2707 * pci_vpd_check_csum - Check VPD checksum 2708 * @buf: Pointer to buffered VPD data 2709 * @len: VPD size 2710 * 2711 * Returns 1 if VPD has no checksum, otherwise 0 or an errno 2712 */ 2713int pci_vpd_check_csum(const void *buf, unsigned int len); 2714 2715/* PCI <-> OF binding helpers */ 2716#ifdef CONFIG_OF 2717struct device_node; 2718struct irq_domain; 2719struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2720bool pci_host_of_has_msi_map(struct device *dev); 2721 2722/* Arch may override this (weak) */ 2723struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2724 2725#else /* CONFIG_OF */ 2726static inline struct irq_domain * 2727pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2728static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; } 2729#endif /* CONFIG_OF */ 2730 2731static inline struct device_node * 2732pci_device_to_OF_node(const struct pci_dev *pdev) 2733{ 2734 return pdev ? pdev->dev.of_node : NULL; 2735} 2736 2737static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2738{ 2739 return bus ? bus->dev.of_node : NULL; 2740} 2741 2742#ifdef CONFIG_ACPI 2743struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2744 2745void 2746pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2747bool pci_pr3_present(struct pci_dev *pdev); 2748#else 2749static inline struct irq_domain * 2750pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2751static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } 2752#endif 2753 2754#if defined(CONFIG_X86) && defined(CONFIG_ACPI) 2755bool arch_pci_dev_is_removable(struct pci_dev *pdev); 2756#else 2757static inline bool arch_pci_dev_is_removable(struct pci_dev *pdev) { return false; } 2758#endif 2759 2760#ifdef CONFIG_EEH 2761static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2762{ 2763 return pdev->dev.archdata.edev; 2764} 2765#endif 2766 2767void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns); 2768bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2769int pci_for_each_dma_alias(struct pci_dev *pdev, 2770 int (*fn)(struct pci_dev *pdev, 2771 u16 alias, void *data), void *data); 2772 2773/* Helper functions for operation of device flag */ 2774static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2775{ 2776 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2777} 2778static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2779{ 2780 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2781} 2782static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2783{ 2784 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2785} 2786 2787/** 2788 * pci_ari_enabled - query ARI forwarding status 2789 * @bus: the PCI bus 2790 * 2791 * Returns true if ARI forwarding is enabled. 2792 */ 2793static inline bool pci_ari_enabled(struct pci_bus *bus) 2794{ 2795 return bus->self && bus->self->ari_enabled; 2796} 2797 2798/** 2799 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2800 * @pdev: PCI device to check 2801 * 2802 * Walk upwards from @pdev and check for each encountered bridge if it's part 2803 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2804 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2805 */ 2806static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2807{ 2808 struct pci_dev *parent = pdev; 2809 2810 if (pdev->is_thunderbolt) 2811 return true; 2812 2813 while ((parent = pci_upstream_bridge(parent))) 2814 if (parent->is_thunderbolt) 2815 return true; 2816 2817 return false; 2818} 2819 2820#if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) || defined(CONFIG_S390) 2821void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2822#endif 2823 2824#include <linux/dma-mapping.h> 2825 2826#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2827#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2828#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2829#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2830#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2831#define pci_warn_once(pdev, fmt, arg...) dev_warn_once(&(pdev)->dev, fmt, ##arg) 2832#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2833#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2834#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2835 2836#define pci_notice_ratelimited(pdev, fmt, arg...) \ 2837 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) 2838 2839#define pci_info_ratelimited(pdev, fmt, arg...) \ 2840 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg) 2841 2842#define pci_WARN(pdev, condition, fmt, arg...) \ 2843 WARN(condition, "%s %s: " fmt, \ 2844 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2845 2846#define pci_WARN_ONCE(pdev, condition, fmt, arg...) \ 2847 WARN_ONCE(condition, "%s %s: " fmt, \ 2848 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2849 2850#endif /* LINUX_PCI_H */
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