pci-epc.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * PCI Endpoint *Controller* (EPC) header file
  4 *
  5 * Copyright (C) 2017 Texas Instruments
  6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
  7 */
  8
  9#ifndef __LINUX_PCI_EPC_H
 10#define __LINUX_PCI_EPC_H
 11
 12#include <linux/pci-epf.h>
 13
 14struct pci_epc;
 15
 16enum pci_epc_interface_type {
 17	UNKNOWN_INTERFACE = -1,
 18	PRIMARY_INTERFACE,
 19	SECONDARY_INTERFACE,
 20};
 21
 22static inline const char *
 23pci_epc_interface_string(enum pci_epc_interface_type type)
 24{
 25	switch (type) {
 26	case PRIMARY_INTERFACE:
 27		return "primary";
 28	case SECONDARY_INTERFACE:
 29		return "secondary";
 30	default:
 31		return "UNKNOWN interface";
 32	}
 33}
 34
 35/**
 36 * struct pci_epc_map - information about EPC memory for mapping a RC PCI
 37 *                      address range
 38 * @pci_addr: start address of the RC PCI address range to map
 39 * @pci_size: size of the RC PCI address range mapped from @pci_addr
 40 * @map_pci_addr: RC PCI address used as the first address mapped (may be lower
 41 *                than @pci_addr)
 42 * @map_size: size of the controller memory needed for mapping the RC PCI address
 43 *            range @map_pci_addr..@pci_addr+@pci_size
 44 * @phys_base: base physical address of the allocated EPC memory for mapping the
 45 *             RC PCI address range
 46 * @phys_addr: physical address at which @pci_addr is mapped
 47 * @virt_base: base virtual address of the allocated EPC memory for mapping the
 48 *             RC PCI address range
 49 * @virt_addr: virtual address at which @pci_addr is mapped
 50 */
 51struct pci_epc_map {
 52	u64		pci_addr;
 53	size_t		pci_size;
 54
 55	u64		map_pci_addr;
 56	size_t		map_size;
 57
 58	phys_addr_t	phys_base;
 59	phys_addr_t	phys_addr;
 60	void __iomem	*virt_base;
 61	void __iomem	*virt_addr;
 62};
 63
 64/**
 65 * struct pci_epc_ops - set of function pointers for performing EPC operations
 66 * @write_header: ops to populate configuration space header
 67 * @set_bar: ops to configure the BAR
 68 * @clear_bar: ops to reset the BAR
 69 * @align_addr: operation to get the mapping address, mapping size and offset
 70 *		into a controller memory window needed to map an RC PCI address
 71 *		region
 72 * @map_addr: ops to map CPU address to PCI address
 73 * @unmap_addr: ops to unmap CPU address and PCI address
 74 * @set_msi: ops to set the requested number of MSI interrupts in the MSI
 75 *	     capability register
 76 * @get_msi: ops to get the number of MSI interrupts allocated by the RC from
 77 *	     the MSI capability register
 78 * @set_msix: ops to set the requested number of MSI-X interrupts in the
 79 *	     MSI-X capability register
 80 * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
 81 *	     from the MSI-X capability register
 82 * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
 83 * @map_msi_irq: ops to map physical address to MSI address and return MSI data
 84 * @start: ops to start the PCI link
 85 * @stop: ops to stop the PCI link
 86 * @get_features: ops to get the features supported by the EPC
 87 * @owner: the module owner containing the ops
 88 */
 89struct pci_epc_ops {
 90	int	(*write_header)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
 91				struct pci_epf_header *hdr);
 92	int	(*set_bar)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
 93			   struct pci_epf_bar *epf_bar);
 94	void	(*clear_bar)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
 95			     struct pci_epf_bar *epf_bar);
 96	u64	(*align_addr)(struct pci_epc *epc, u64 pci_addr, size_t *size,
 97			      size_t *offset);
 98	int	(*map_addr)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
 99			    phys_addr_t addr, u64 pci_addr, size_t size);
100	void	(*unmap_addr)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
101			      phys_addr_t addr);
102	int	(*set_msi)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
103			   u8 nr_irqs);
104	int	(*get_msi)(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
105	int	(*set_msix)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
106			    u16 nr_irqs, enum pci_barno, u32 offset);
107	int	(*get_msix)(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
108	int	(*raise_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
109			     unsigned int type, u16 interrupt_num);
110	int	(*map_msi_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
111			       phys_addr_t phys_addr, u8 interrupt_num,
112			       u32 entry_size, u32 *msi_data,
113			       u32 *msi_addr_offset);
114	int	(*start)(struct pci_epc *epc);
115	void	(*stop)(struct pci_epc *epc);
116	const struct pci_epc_features* (*get_features)(struct pci_epc *epc,
117						       u8 func_no, u8 vfunc_no);
118	struct module *owner;
119};
120
121/**
122 * struct pci_epc_mem_window - address window of the endpoint controller
123 * @phys_base: physical base address of the PCI address window
124 * @size: the size of the PCI address window
125 * @page_size: size of each page
126 */
127struct pci_epc_mem_window {
128	phys_addr_t	phys_base;
129	size_t		size;
130	size_t		page_size;
131};
132
133/**
134 * struct pci_epc_mem - address space of the endpoint controller
135 * @window: address window of the endpoint controller
136 * @bitmap: bitmap to manage the PCI address space
137 * @pages: number of bits representing the address region
138 * @lock: mutex to protect bitmap
139 */
140struct pci_epc_mem {
141	struct pci_epc_mem_window window;
142	unsigned long	*bitmap;
143	int		pages;
144	/* mutex to protect against concurrent access for memory allocation*/
145	struct mutex	lock;
146};
147
148/**
149 * struct pci_epc - represents the PCI EPC device
150 * @dev: PCI EPC device
151 * @pci_epf: list of endpoint functions present in this EPC device
152 * @list_lock: Mutex for protecting pci_epf list
153 * @ops: function pointers for performing endpoint operations
154 * @windows: array of address space of the endpoint controller
155 * @mem: first window of the endpoint controller, which corresponds to
156 *       default address space of the endpoint controller supporting
157 *       single window.
158 * @num_windows: number of windows supported by device
159 * @max_functions: max number of functions that can be configured in this EPC
160 * @max_vfs: Array indicating the maximum number of virtual functions that can
161 *   be associated with each physical function
162 * @group: configfs group representing the PCI EPC device
163 * @lock: mutex to protect pci_epc ops
164 * @function_num_map: bitmap to manage physical function number
165 * @domain_nr: PCI domain number of the endpoint controller
166 * @init_complete: flag to indicate whether the EPC initialization is complete
167 *                 or not
168 */
169struct pci_epc {
170	struct device			dev;
171	struct list_head		pci_epf;
172	struct mutex			list_lock;
173	const struct pci_epc_ops	*ops;
174	struct pci_epc_mem		**windows;
175	struct pci_epc_mem		*mem;
176	unsigned int			num_windows;
177	u8				max_functions;
178	u8				*max_vfs;
179	struct config_group		*group;
180	/* mutex to protect against concurrent access of EP controller */
181	struct mutex			lock;
182	unsigned long			function_num_map;
183	int				domain_nr;
184	bool				init_complete;
185};
186
187/**
188 * enum pci_epc_bar_type - configurability of endpoint BAR
189 * @BAR_PROGRAMMABLE: The BAR mask can be configured by the EPC.
190 * @BAR_FIXED: The BAR mask is fixed by the hardware.
191 * @BAR_RESIZABLE: The BAR implements the PCI-SIG Resizable BAR Capability.
192 *		   NOTE: An EPC driver can currently only set a single supported
193 *		   size.
194 * @BAR_RESERVED: The BAR should not be touched by an EPF driver.
195 */
196enum pci_epc_bar_type {
197	BAR_PROGRAMMABLE = 0,
198	BAR_FIXED,
199	BAR_RESIZABLE,
200	BAR_RESERVED,
201};
202
203/**
204 * struct pci_epc_bar_desc - hardware description for a BAR
205 * @type: the type of the BAR
206 * @fixed_size: the fixed size, only applicable if type is BAR_FIXED_MASK.
207 * @only_64bit: if true, an EPF driver is not allowed to choose if this BAR
208 *		should be configured as 32-bit or 64-bit, the EPF driver must
209 *		configure this BAR as 64-bit. Additionally, the BAR succeeding
210 *		this BAR must be set to type BAR_RESERVED.
211 *
212 *		only_64bit should not be set on a BAR of type BAR_RESERVED.
213 *		(If BARx is a 64-bit BAR that an EPF driver is not allowed to
214 *		touch, then both BARx and BARx+1 must be set to type
215 *		BAR_RESERVED.)
216 */
217struct pci_epc_bar_desc {
218	enum pci_epc_bar_type type;
219	u64 fixed_size;
220	bool only_64bit;
221};
222
223/**
224 * struct pci_epc_features - features supported by a EPC device per function
225 * @linkup_notifier: indicate if the EPC device can notify EPF driver on link up
226 * @dynamic_inbound_mapping: indicate if the EPC device supports updating
227 *                           inbound mappings for an already configured BAR
228 *                           (i.e. allow calling pci_epc_set_bar() again
229 *                           without first calling pci_epc_clear_bar())
230 * @subrange_mapping: indicate if the EPC device can map inbound subranges for a
231 *                    BAR. This feature depends on @dynamic_inbound_mapping
232 *                    feature.
233 * @msi_capable: indicate if the endpoint function has MSI capability
234 * @msix_capable: indicate if the endpoint function has MSI-X capability
235 * @intx_capable: indicate if the endpoint can raise INTx interrupts
236 * @bar: array specifying the hardware description for each BAR
237 * @align: alignment size required for BAR buffer allocation
238 */
239struct pci_epc_features {
240	unsigned int	linkup_notifier : 1;
241	unsigned int	dynamic_inbound_mapping : 1;
242	unsigned int	subrange_mapping : 1;
243	unsigned int	msi_capable : 1;
244	unsigned int	msix_capable : 1;
245	unsigned int	intx_capable : 1;
246	struct	pci_epc_bar_desc bar[PCI_STD_NUM_BARS];
247	size_t	align;
248};
249
250#define to_pci_epc(device) container_of((device), struct pci_epc, dev)
251
252#ifdef CONFIG_PCI_ENDPOINT
253
254#define pci_epc_create(dev, ops)    \
255		__pci_epc_create((dev), (ops), THIS_MODULE)
256#define devm_pci_epc_create(dev, ops)    \
257		__devm_pci_epc_create((dev), (ops), THIS_MODULE)
258
259static inline void epc_set_drvdata(struct pci_epc *epc, void *data)
260{
261	dev_set_drvdata(&epc->dev, data);
262}
263
264static inline void *epc_get_drvdata(struct pci_epc *epc)
265{
266	return dev_get_drvdata(&epc->dev);
267}
268
269struct pci_epc *
270__devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
271		      struct module *owner);
272struct pci_epc *
273__pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
274		 struct module *owner);
275void pci_epc_destroy(struct pci_epc *epc);
276int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf,
277		    enum pci_epc_interface_type type);
278void pci_epc_linkup(struct pci_epc *epc);
279void pci_epc_linkdown(struct pci_epc *epc);
280void pci_epc_init_notify(struct pci_epc *epc);
281void pci_epc_notify_pending_init(struct pci_epc *epc, struct pci_epf *epf);
282void pci_epc_deinit_notify(struct pci_epc *epc);
283void pci_epc_bus_master_enable_notify(struct pci_epc *epc);
284void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf,
285			enum pci_epc_interface_type type);
286int pci_epc_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
287			 struct pci_epf_header *hdr);
288int pci_epc_bar_size_to_rebar_cap(size_t size, u32 *cap);
289int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
290		    struct pci_epf_bar *epf_bar);
291void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
292		       struct pci_epf_bar *epf_bar);
293int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
294		     phys_addr_t phys_addr,
295		     u64 pci_addr, size_t size);
296void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
297			phys_addr_t phys_addr);
298int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no, u8 nr_irqs);
299int pci_epc_get_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
300int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no, u16 nr_irqs,
301		     enum pci_barno, u32 offset);
302int pci_epc_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
303int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
304			phys_addr_t phys_addr, u8 interrupt_num,
305			u32 entry_size, u32 *msi_data, u32 *msi_addr_offset);
306int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
307		      unsigned int type, u16 interrupt_num);
308int pci_epc_start(struct pci_epc *epc);
309void pci_epc_stop(struct pci_epc *epc);
310const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
311						    u8 func_no, u8 vfunc_no);
312enum pci_barno
313pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features);
314enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features
315					 *epc_features, enum pci_barno bar);
316struct pci_epc *pci_epc_get(const char *epc_name);
317void pci_epc_put(struct pci_epc *epc);
318
319int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base,
320		     size_t size, size_t page_size);
321int pci_epc_multi_mem_init(struct pci_epc *epc,
322			   struct pci_epc_mem_window *window,
323			   unsigned int num_windows);
324void pci_epc_mem_exit(struct pci_epc *epc);
325void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
326				     phys_addr_t *phys_addr, size_t size);
327void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
328			   void __iomem *virt_addr, size_t size);
329int pci_epc_mem_map(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
330		    u64 pci_addr, size_t pci_size, struct pci_epc_map *map);
331void pci_epc_mem_unmap(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
332		       struct pci_epc_map *map);
333
334#else
335static inline void pci_epc_init_notify(struct pci_epc *epc)
336{
337}
338
339static inline void pci_epc_deinit_notify(struct pci_epc *epc)
340{
341}
342#endif /* CONFIG_PCI_ENDPOINT */
343#endif /* __LINUX_PCI_EPC_H */