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spinand.h
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linux-6.19.14/include/linux/mtd/spinand.h
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2016-2017 Micron Technology, Inc. 4 * 5 * Authors: 6 * Peter Pan <peterpandong@micron.com> 7 */ 8#ifndef __LINUX_MTD_SPINAND_H 9#define __LINUX_MTD_SPINAND_H 10 11#include <linux/mutex.h> 12#include <linux/bitops.h> 13#include <linux/device.h> 14#include <linux/mtd/mtd.h> 15#include <linux/mtd/nand.h> 16#include <linux/spi/spi.h> 17#include <linux/spi/spi-mem.h> 18 19/** 20 * Standard SPI NAND flash operations 21 */ 22 23#define SPINAND_RESET_1S_0_0_OP \ 24 SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1), \ 25 SPI_MEM_OP_NO_ADDR, \ 26 SPI_MEM_OP_NO_DUMMY, \ 27 SPI_MEM_OP_NO_DATA) 28 29#define SPINAND_WR_EN_DIS_1S_0_0_OP(enable) \ 30 SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \ 31 SPI_MEM_OP_NO_ADDR, \ 32 SPI_MEM_OP_NO_DUMMY, \ 33 SPI_MEM_OP_NO_DATA) 34 35#define SPINAND_READID_1S_1S_1S_OP(naddr, ndummy, buf, len) \ 36 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \ 37 SPI_MEM_OP_ADDR(naddr, 0, 1), \ 38 SPI_MEM_OP_DUMMY(ndummy, 1), \ 39 SPI_MEM_OP_DATA_IN(len, buf, 1)) 40 41#define SPINAND_SET_FEATURE_1S_1S_1S_OP(reg, valptr) \ 42 SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \ 43 SPI_MEM_OP_ADDR(1, reg, 1), \ 44 SPI_MEM_OP_NO_DUMMY, \ 45 SPI_MEM_OP_DATA_OUT(1, valptr, 1)) 46 47#define SPINAND_GET_FEATURE_1S_1S_1S_OP(reg, valptr) \ 48 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1), \ 49 SPI_MEM_OP_ADDR(1, reg, 1), \ 50 SPI_MEM_OP_NO_DUMMY, \ 51 SPI_MEM_OP_DATA_IN(1, valptr, 1)) 52 53#define SPINAND_BLK_ERASE_1S_1S_0_OP(addr) \ 54 SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1), \ 55 SPI_MEM_OP_ADDR(3, addr, 1), \ 56 SPI_MEM_OP_NO_DUMMY, \ 57 SPI_MEM_OP_NO_DATA) 58 59#define SPINAND_PAGE_READ_1S_1S_0_OP(addr) \ 60 SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1), \ 61 SPI_MEM_OP_ADDR(3, addr, 1), \ 62 SPI_MEM_OP_NO_DUMMY, \ 63 SPI_MEM_OP_NO_DATA) 64 65#define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(addr, ndummy, buf, len, freq) \ 66 SPI_MEM_OP(SPI_MEM_OP_CMD(0x03, 1), \ 67 SPI_MEM_OP_ADDR(2, addr, 1), \ 68 SPI_MEM_OP_DUMMY(ndummy, 1), \ 69 SPI_MEM_OP_DATA_IN(len, buf, 1), \ 70 SPI_MEM_OP_MAX_FREQ(freq)) 71 72#define SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(addr, ndummy, buf, len, freq) \ 73 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \ 74 SPI_MEM_OP_ADDR(2, addr, 1), \ 75 SPI_MEM_OP_DUMMY(ndummy, 1), \ 76 SPI_MEM_OP_DATA_IN(len, buf, 1), \ 77 SPI_MEM_OP_MAX_FREQ(freq)) 78 79#define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_1S_1S_OP(addr, ndummy, buf, len, freq) \ 80 SPI_MEM_OP(SPI_MEM_OP_CMD(0x03, 1), \ 81 SPI_MEM_OP_ADDR(3, addr, 1), \ 82 SPI_MEM_OP_DUMMY(ndummy, 1), \ 83 SPI_MEM_OP_DATA_IN(len, buf, 1), \ 84 SPI_MEM_OP_MAX_FREQ(freq)) 85 86#define SPINAND_PAGE_READ_FROM_CACHE_FAST_3A_1S_1S_1S_OP(addr, ndummy, buf, len, freq) \ 87 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \ 88 SPI_MEM_OP_ADDR(3, addr, 1), \ 89 SPI_MEM_OP_DUMMY(ndummy, 1), \ 90 SPI_MEM_OP_DATA_IN(len, buf, 1), \ 91 SPI_MEM_OP_MAX_FREQ(freq)) 92 93#define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_1D_OP(addr, ndummy, buf, len, freq) \ 94 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0d, 1), \ 95 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \ 96 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \ 97 SPI_MEM_DTR_OP_DATA_IN(len, buf, 1), \ 98 SPI_MEM_OP_MAX_FREQ(freq)) 99 100#define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_2S_OP(addr, ndummy, buf, len, freq) \ 101 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ 102 SPI_MEM_OP_ADDR(2, addr, 1), \ 103 SPI_MEM_OP_DUMMY(ndummy, 1), \ 104 SPI_MEM_OP_DATA_IN(len, buf, 2), \ 105 SPI_MEM_OP_MAX_FREQ(freq)) 106 107#define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_1S_2S_OP(addr, ndummy, buf, len, freq) \ 108 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ 109 SPI_MEM_OP_ADDR(3, addr, 1), \ 110 SPI_MEM_OP_DUMMY(ndummy, 1), \ 111 SPI_MEM_OP_DATA_IN(len, buf, 2), \ 112 SPI_MEM_OP_MAX_FREQ(freq)) 113 114#define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_2D_OP(addr, ndummy, buf, len, freq) \ 115 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3d, 1), \ 116 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \ 117 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \ 118 SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \ 119 SPI_MEM_OP_MAX_FREQ(freq)) 120 121#define SPINAND_PAGE_READ_FROM_CACHE_1S_2S_2S_OP(addr, ndummy, buf, len, freq) \ 122 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \ 123 SPI_MEM_OP_ADDR(2, addr, 2), \ 124 SPI_MEM_OP_DUMMY(ndummy, 2), \ 125 SPI_MEM_OP_DATA_IN(len, buf, 2), \ 126 SPI_MEM_OP_MAX_FREQ(freq)) 127 128#define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_2S_2S_OP(addr, ndummy, buf, len, freq) \ 129 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \ 130 SPI_MEM_OP_ADDR(3, addr, 2), \ 131 SPI_MEM_OP_DUMMY(ndummy, 2), \ 132 SPI_MEM_OP_DATA_IN(len, buf, 2), \ 133 SPI_MEM_OP_MAX_FREQ(freq)) 134 135#define SPINAND_PAGE_READ_FROM_CACHE_1S_2D_2D_OP(addr, ndummy, buf, len, freq) \ 136 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbd, 1), \ 137 SPI_MEM_DTR_OP_ADDR(2, addr, 2), \ 138 SPI_MEM_DTR_OP_DUMMY(ndummy, 2), \ 139 SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \ 140 SPI_MEM_OP_MAX_FREQ(freq)) 141 142#define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP(addr, ndummy, buf, len, freq) \ 143 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ 144 SPI_MEM_OP_ADDR(2, addr, 1), \ 145 SPI_MEM_OP_DUMMY(ndummy, 1), \ 146 SPI_MEM_OP_DATA_IN(len, buf, 4), \ 147 SPI_MEM_OP_MAX_FREQ(freq)) 148 149#define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_1S_4S_OP(addr, ndummy, buf, len, freq) \ 150 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ 151 SPI_MEM_OP_ADDR(3, addr, 1), \ 152 SPI_MEM_OP_DUMMY(ndummy, 1), \ 153 SPI_MEM_OP_DATA_IN(len, buf, 4), \ 154 SPI_MEM_OP_MAX_FREQ(freq)) 155 156#define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_4D_OP(addr, ndummy, buf, len, freq) \ 157 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6d, 1), \ 158 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \ 159 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \ 160 SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \ 161 SPI_MEM_OP_MAX_FREQ(freq)) 162 163#define SPINAND_PAGE_READ_FROM_CACHE_1S_4S_4S_OP(addr, ndummy, buf, len, freq) \ 164 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \ 165 SPI_MEM_OP_ADDR(2, addr, 4), \ 166 SPI_MEM_OP_DUMMY(ndummy, 4), \ 167 SPI_MEM_OP_DATA_IN(len, buf, 4), \ 168 SPI_MEM_OP_MAX_FREQ(freq)) 169 170#define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_4S_4S_OP(addr, ndummy, buf, len, freq) \ 171 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \ 172 SPI_MEM_OP_ADDR(3, addr, 4), \ 173 SPI_MEM_OP_DUMMY(ndummy, 4), \ 174 SPI_MEM_OP_DATA_IN(len, buf, 4), \ 175 SPI_MEM_OP_MAX_FREQ(freq)) 176 177#define SPINAND_PAGE_READ_FROM_CACHE_1S_4D_4D_OP(addr, ndummy, buf, len, freq) \ 178 SPI_MEM_OP(SPI_MEM_OP_CMD(0xed, 1), \ 179 SPI_MEM_DTR_OP_ADDR(2, addr, 4), \ 180 SPI_MEM_DTR_OP_DUMMY(ndummy, 4), \ 181 SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \ 182 SPI_MEM_OP_MAX_FREQ(freq)) 183 184#define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_8S_OP(addr, ndummy, buf, len, freq) \ 185 SPI_MEM_OP(SPI_MEM_OP_CMD(0x8b, 1), \ 186 SPI_MEM_OP_ADDR(2, addr, 1), \ 187 SPI_MEM_OP_DUMMY(ndummy, 1), \ 188 SPI_MEM_OP_DATA_IN(len, buf, 8), \ 189 SPI_MEM_OP_MAX_FREQ(freq)) 190 191#define SPINAND_PAGE_READ_FROM_CACHE_1S_8S_8S_OP(addr, ndummy, buf, len, freq) \ 192 SPI_MEM_OP(SPI_MEM_OP_CMD(0xcb, 1), \ 193 SPI_MEM_OP_ADDR(2, addr, 8), \ 194 SPI_MEM_OP_DUMMY(ndummy, 8), \ 195 SPI_MEM_OP_DATA_IN(len, buf, 8), \ 196 SPI_MEM_OP_MAX_FREQ(freq)) 197 198#define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_8D_OP(addr, ndummy, buf, len, freq) \ 199 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9d, 1), \ 200 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \ 201 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \ 202 SPI_MEM_DTR_OP_DATA_IN(len, buf, 8), \ 203 SPI_MEM_OP_MAX_FREQ(freq)) 204 205#define SPINAND_PROG_EXEC_1S_1S_0_OP(addr) \ 206 SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \ 207 SPI_MEM_OP_ADDR(3, addr, 1), \ 208 SPI_MEM_OP_NO_DUMMY, \ 209 SPI_MEM_OP_NO_DATA) 210 211#define SPINAND_PROG_LOAD_1S_1S_1S_OP(reset, addr, buf, len) \ 212 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1), \ 213 SPI_MEM_OP_ADDR(2, addr, 1), \ 214 SPI_MEM_OP_NO_DUMMY, \ 215 SPI_MEM_OP_DATA_OUT(len, buf, 1)) 216 217#define SPINAND_PROG_LOAD_1S_1S_4S_OP(reset, addr, buf, len) \ 218 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1), \ 219 SPI_MEM_OP_ADDR(2, addr, 1), \ 220 SPI_MEM_OP_NO_DUMMY, \ 221 SPI_MEM_OP_DATA_OUT(len, buf, 4)) 222 223#define SPINAND_PROG_LOAD_1S_1S_8S_OP(addr, buf, len) \ 224 SPI_MEM_OP(SPI_MEM_OP_CMD(0x82, 1), \ 225 SPI_MEM_OP_ADDR(2, addr, 1), \ 226 SPI_MEM_OP_NO_DUMMY, \ 227 SPI_MEM_OP_DATA_OUT(len, buf, 8)) 228 229#define SPINAND_PROG_LOAD_1S_8S_8S_OP(reset, addr, buf, len) \ 230 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0xc2 : 0xc4, 1), \ 231 SPI_MEM_OP_ADDR(2, addr, 8), \ 232 SPI_MEM_OP_NO_DUMMY, \ 233 SPI_MEM_OP_DATA_OUT(len, buf, 8)) 234 235/** 236 * Standard SPI NAND flash commands 237 */ 238#define SPINAND_CMD_PROG_LOAD_X4 0x32 239#define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4 0x34 240 241/* feature register */ 242#define REG_BLOCK_LOCK 0xa0 243#define BL_ALL_UNLOCKED 0x00 244 245/* configuration register */ 246#define REG_CFG 0xb0 247#define CFG_OTP_ENABLE BIT(6) 248#define CFG_ECC_ENABLE BIT(4) 249#define CFG_QUAD_ENABLE BIT(0) 250 251/* status register */ 252#define REG_STATUS 0xc0 253#define STATUS_BUSY BIT(0) 254#define STATUS_ERASE_FAILED BIT(2) 255#define STATUS_PROG_FAILED BIT(3) 256#define STATUS_ECC_MASK GENMASK(5, 4) 257#define STATUS_ECC_NO_BITFLIPS (0 << 4) 258#define STATUS_ECC_HAS_BITFLIPS (1 << 4) 259#define STATUS_ECC_UNCOR_ERROR (2 << 4) 260 261struct spinand_op; 262struct spinand_device; 263 264#define SPINAND_MAX_ID_LEN 5 265/* 266 * For erase, write and read operation, we got the following timings : 267 * tBERS (erase) 1ms to 4ms 268 * tPROG 300us to 400us 269 * tREAD 25us to 100us 270 * In order to minimize latency, the min value is divided by 4 for the 271 * initial delay, and dividing by 20 for the poll delay. 272 * For reset, 5us/10us/500us if the device is respectively 273 * reading/programming/erasing when the RESET occurs. Since we always 274 * issue a RESET when the device is IDLE, 5us is selected for both initial 275 * and poll delay. 276 */ 277#define SPINAND_READ_INITIAL_DELAY_US 6 278#define SPINAND_READ_POLL_DELAY_US 5 279#define SPINAND_RESET_INITIAL_DELAY_US 5 280#define SPINAND_RESET_POLL_DELAY_US 5 281#define SPINAND_WRITE_INITIAL_DELAY_US 75 282#define SPINAND_WRITE_POLL_DELAY_US 15 283#define SPINAND_ERASE_INITIAL_DELAY_US 250 284#define SPINAND_ERASE_POLL_DELAY_US 50 285 286#define SPINAND_WAITRDY_TIMEOUT_MS 400 287 288/** 289 * struct spinand_id - SPI NAND id structure 290 * @data: buffer containing the id bytes. Currently 5 bytes large, but can 291 * be extended if required 292 * @len: ID length 293 */ 294struct spinand_id { 295 u8 data[SPINAND_MAX_ID_LEN]; 296 int len; 297}; 298 299enum spinand_readid_method { 300 SPINAND_READID_METHOD_OPCODE, 301 SPINAND_READID_METHOD_OPCODE_ADDR, 302 SPINAND_READID_METHOD_OPCODE_DUMMY, 303}; 304 305/** 306 * struct spinand_devid - SPI NAND device id structure 307 * @id: device id of current chip 308 * @len: number of bytes in device id 309 * @method: method to read chip id 310 * There are 3 possible variants: 311 * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately 312 * after read_id opcode. 313 * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after 314 * read_id opcode + 1-byte address. 315 * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after 316 * read_id opcode + 1 dummy byte. 317 */ 318struct spinand_devid { 319 const u8 *id; 320 const u8 len; 321 const enum spinand_readid_method method; 322}; 323 324/** 325 * struct manufacurer_ops - SPI NAND manufacturer specific operations 326 * @init: initialize a SPI NAND device 327 * @cleanup: cleanup a SPI NAND device 328 * 329 * Each SPI NAND manufacturer driver should implement this interface so that 330 * NAND chips coming from this vendor can be initialized properly. 331 */ 332struct spinand_manufacturer_ops { 333 int (*init)(struct spinand_device *spinand); 334 void (*cleanup)(struct spinand_device *spinand); 335}; 336 337/** 338 * struct spinand_manufacturer - SPI NAND manufacturer instance 339 * @id: manufacturer ID 340 * @name: manufacturer name 341 * @devid_len: number of bytes in device ID 342 * @chips: supported SPI NANDs under current manufacturer 343 * @nchips: number of SPI NANDs available in chips array 344 * @ops: manufacturer operations 345 */ 346struct spinand_manufacturer { 347 u8 id; 348 char *name; 349 const struct spinand_info *chips; 350 const size_t nchips; 351 const struct spinand_manufacturer_ops *ops; 352}; 353 354/* SPI NAND manufacturers */ 355extern const struct spinand_manufacturer alliancememory_spinand_manufacturer; 356extern const struct spinand_manufacturer ato_spinand_manufacturer; 357extern const struct spinand_manufacturer esmt_8c_spinand_manufacturer; 358extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; 359extern const struct spinand_manufacturer fmsh_spinand_manufacturer; 360extern const struct spinand_manufacturer foresee_spinand_manufacturer; 361extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; 362extern const struct spinand_manufacturer macronix_spinand_manufacturer; 363extern const struct spinand_manufacturer micron_spinand_manufacturer; 364extern const struct spinand_manufacturer paragon_spinand_manufacturer; 365extern const struct spinand_manufacturer skyhigh_spinand_manufacturer; 366extern const struct spinand_manufacturer toshiba_spinand_manufacturer; 367extern const struct spinand_manufacturer winbond_spinand_manufacturer; 368extern const struct spinand_manufacturer xtx_spinand_manufacturer; 369 370/** 371 * struct spinand_op_variants - SPI NAND operation variants 372 * @ops: the list of variants for a given operation 373 * @nops: the number of variants 374 * 375 * Some operations like read-from-cache/write-to-cache have several variants 376 * depending on the number of IO lines you use to transfer data or address 377 * cycles. This structure is a way to describe the different variants supported 378 * by a chip and let the core pick the best one based on the SPI mem controller 379 * capabilities. 380 */ 381struct spinand_op_variants { 382 const struct spi_mem_op *ops; 383 unsigned int nops; 384}; 385 386#define SPINAND_OP_VARIANTS(name, ...) \ 387 const struct spinand_op_variants name = { \ 388 .ops = (struct spi_mem_op[]) { __VA_ARGS__ }, \ 389 .nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) / \ 390 sizeof(struct spi_mem_op), \ 391 } 392 393/** 394 * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND 395 * chip 396 * @get_status: get the ECC status. Should return a positive number encoding 397 * the number of corrected bitflips if correction was possible or 398 * -EBADMSG if there are uncorrectable errors. I can also return 399 * other negative error codes if the error is not caused by 400 * uncorrectable bitflips 401 * @ooblayout: the OOB layout used by the on-die ECC implementation 402 */ 403struct spinand_ecc_info { 404 int (*get_status)(struct spinand_device *spinand, u8 status); 405 const struct mtd_ooblayout_ops *ooblayout; 406}; 407 408#define SPINAND_HAS_QE_BIT BIT(0) 409#define SPINAND_HAS_CR_FEAT_BIT BIT(1) 410#define SPINAND_HAS_PROG_PLANE_SELECT_BIT BIT(2) 411#define SPINAND_HAS_READ_PLANE_SELECT_BIT BIT(3) 412#define SPINAND_NO_RAW_ACCESS BIT(4) 413 414/** 415 * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure 416 * @status: status of the last wait operation that will be used in case 417 * ->get_status() is not populated by the spinand device. 418 */ 419struct spinand_ondie_ecc_conf { 420 u8 status; 421}; 422 423/** 424 * struct spinand_otp_layout - structure to describe the SPI NAND OTP area 425 * @npages: number of pages in the OTP 426 * @start_page: start page of the user/factory OTP area. 427 */ 428struct spinand_otp_layout { 429 unsigned int npages; 430 unsigned int start_page; 431}; 432 433/** 434 * struct spinand_fact_otp_ops - SPI NAND OTP methods for factory area 435 * @info: get the OTP area information 436 * @read: read from the SPI NAND OTP area 437 */ 438struct spinand_fact_otp_ops { 439 int (*info)(struct spinand_device *spinand, size_t len, 440 struct otp_info *buf, size_t *retlen); 441 int (*read)(struct spinand_device *spinand, loff_t from, size_t len, 442 size_t *retlen, u8 *buf); 443}; 444 445/** 446 * struct spinand_user_otp_ops - SPI NAND OTP methods for user area 447 * @info: get the OTP area information 448 * @lock: lock an OTP region 449 * @erase: erase an OTP region 450 * @read: read from the SPI NAND OTP area 451 * @write: write to the SPI NAND OTP area 452 */ 453struct spinand_user_otp_ops { 454 int (*info)(struct spinand_device *spinand, size_t len, 455 struct otp_info *buf, size_t *retlen); 456 int (*lock)(struct spinand_device *spinand, loff_t from, size_t len); 457 int (*erase)(struct spinand_device *spinand, loff_t from, size_t len); 458 int (*read)(struct spinand_device *spinand, loff_t from, size_t len, 459 size_t *retlen, u8 *buf); 460 int (*write)(struct spinand_device *spinand, loff_t from, size_t len, 461 size_t *retlen, const u8 *buf); 462}; 463 464/** 465 * struct spinand_fact_otp - SPI NAND OTP grouping structure for factory area 466 * @layout: OTP region layout 467 * @ops: OTP access ops 468 */ 469struct spinand_fact_otp { 470 const struct spinand_otp_layout layout; 471 const struct spinand_fact_otp_ops *ops; 472}; 473 474/** 475 * struct spinand_user_otp - SPI NAND OTP grouping structure for user area 476 * @layout: OTP region layout 477 * @ops: OTP access ops 478 */ 479struct spinand_user_otp { 480 const struct spinand_otp_layout layout; 481 const struct spinand_user_otp_ops *ops; 482}; 483 484/** 485 * struct spinand_info - Structure used to describe SPI NAND chips 486 * @model: model name 487 * @devid: device ID 488 * @flags: OR-ing of the SPINAND_XXX flags 489 * @memorg: memory organization 490 * @eccreq: ECC requirements 491 * @eccinfo: on-die ECC info 492 * @op_variants: operations variants 493 * @op_variants.read_cache: variants of the read-cache operation 494 * @op_variants.write_cache: variants of the write-cache operation 495 * @op_variants.update_cache: variants of the update-cache operation 496 * @select_target: function used to select a target/die. Required only for 497 * multi-die chips 498 * @configure_chip: Align the chip configuration with the core settings 499 * @set_cont_read: enable/disable continuous cached reads 500 * @fact_otp: SPI NAND factory OTP info. 501 * @user_otp: SPI NAND user OTP info. 502 * @read_retries: the number of read retry modes supported 503 * @set_read_retry: enable/disable read retry for data recovery 504 * 505 * Each SPI NAND manufacturer driver should have a spinand_info table 506 * describing all the chips supported by the driver. 507 */ 508struct spinand_info { 509 const char *model; 510 struct spinand_devid devid; 511 u32 flags; 512 struct nand_memory_organization memorg; 513 struct nand_ecc_props eccreq; 514 struct spinand_ecc_info eccinfo; 515 struct { 516 const struct spinand_op_variants *read_cache; 517 const struct spinand_op_variants *write_cache; 518 const struct spinand_op_variants *update_cache; 519 } op_variants; 520 int (*select_target)(struct spinand_device *spinand, 521 unsigned int target); 522 int (*configure_chip)(struct spinand_device *spinand); 523 int (*set_cont_read)(struct spinand_device *spinand, 524 bool enable); 525 struct spinand_fact_otp fact_otp; 526 struct spinand_user_otp user_otp; 527 unsigned int read_retries; 528 int (*set_read_retry)(struct spinand_device *spinand, 529 unsigned int read_retry); 530}; 531 532#define SPINAND_ID(__method, ...) \ 533 { \ 534 .id = (const u8[]){ __VA_ARGS__ }, \ 535 .len = sizeof((u8[]){ __VA_ARGS__ }), \ 536 .method = __method, \ 537 } 538 539#define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \ 540 { \ 541 .read_cache = __read, \ 542 .write_cache = __write, \ 543 .update_cache = __update, \ 544 } 545 546#define SPINAND_ECCINFO(__ooblayout, __get_status) \ 547 .eccinfo = { \ 548 .ooblayout = __ooblayout, \ 549 .get_status = __get_status, \ 550 } 551 552#define SPINAND_SELECT_TARGET(__func) \ 553 .select_target = __func 554 555#define SPINAND_CONFIGURE_CHIP(__configure_chip) \ 556 .configure_chip = __configure_chip 557 558#define SPINAND_CONT_READ(__set_cont_read) \ 559 .set_cont_read = __set_cont_read 560 561#define SPINAND_FACT_OTP_INFO(__npages, __start_page, __ops) \ 562 .fact_otp = { \ 563 .layout = { \ 564 .npages = __npages, \ 565 .start_page = __start_page, \ 566 }, \ 567 .ops = __ops, \ 568 } 569 570#define SPINAND_USER_OTP_INFO(__npages, __start_page, __ops) \ 571 .user_otp = { \ 572 .layout = { \ 573 .npages = __npages, \ 574 .start_page = __start_page, \ 575 }, \ 576 .ops = __ops, \ 577 } 578 579#define SPINAND_READ_RETRY(__read_retries, __set_read_retry) \ 580 .read_retries = __read_retries, \ 581 .set_read_retry = __set_read_retry 582 583#define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \ 584 __flags, ...) \ 585 { \ 586 .model = __model, \ 587 .devid = __id, \ 588 .memorg = __memorg, \ 589 .eccreq = __eccreq, \ 590 .op_variants = __op_variants, \ 591 .flags = __flags, \ 592 __VA_ARGS__ \ 593 } 594 595struct spinand_dirmap { 596 struct spi_mem_dirmap_desc *wdesc; 597 struct spi_mem_dirmap_desc *rdesc; 598 struct spi_mem_dirmap_desc *wdesc_ecc; 599 struct spi_mem_dirmap_desc *rdesc_ecc; 600}; 601 602/** 603 * struct spinand_device - SPI NAND device instance 604 * @base: NAND device instance 605 * @spimem: pointer to the SPI mem object 606 * @lock: lock used to serialize accesses to the NAND 607 * @id: NAND ID as returned by READ_ID 608 * @flags: NAND flags 609 * @op_templates: various SPI mem op templates 610 * @op_templates.read_cache: read cache op template 611 * @op_templates.write_cache: write cache op template 612 * @op_templates.update_cache: update cache op template 613 * @select_target: select a specific target/die. Usually called before sending 614 * a command addressing a page or an eraseblock embedded in 615 * this die. Only required if your chip exposes several dies 616 * @cur_target: currently selected target/die 617 * @eccinfo: on-die ECC information 618 * @cfg_cache: config register cache. One entry per die 619 * @databuf: bounce buffer for data 620 * @oobbuf: bounce buffer for OOB data 621 * @scratchbuf: buffer used for everything but page accesses. This is needed 622 * because the spi-mem interface explicitly requests that buffers 623 * passed in spi_mem_op be DMA-able, so we can't based the bufs on 624 * the stack 625 * @manufacturer: SPI NAND manufacturer information 626 * @configure_chip: Align the chip configuration with the core settings 627 * @cont_read_possible: Field filled by the core once the whole system 628 * configuration is known to tell whether continuous reads are 629 * suitable to use or not in general with this chip/configuration. 630 * A per-transfer check must of course be done to ensure it is 631 * actually relevant to enable this feature. 632 * @set_cont_read: Enable/disable the continuous read feature 633 * @priv: manufacturer private data 634 * @fact_otp: SPI NAND factory OTP info. 635 * @user_otp: SPI NAND user OTP info. 636 * @read_retries: the number of read retry modes supported 637 * @set_read_retry: Enable/disable the read retry feature 638 */ 639struct spinand_device { 640 struct nand_device base; 641 struct spi_mem *spimem; 642 struct mutex lock; 643 struct spinand_id id; 644 u32 flags; 645 646 struct { 647 const struct spi_mem_op *read_cache; 648 const struct spi_mem_op *write_cache; 649 const struct spi_mem_op *update_cache; 650 } op_templates; 651 652 struct spinand_dirmap *dirmaps; 653 654 int (*select_target)(struct spinand_device *spinand, 655 unsigned int target); 656 unsigned int cur_target; 657 658 struct spinand_ecc_info eccinfo; 659 660 u8 *cfg_cache; 661 u8 *databuf; 662 u8 *oobbuf; 663 u8 *scratchbuf; 664 const struct spinand_manufacturer *manufacturer; 665 void *priv; 666 667 int (*configure_chip)(struct spinand_device *spinand); 668 bool cont_read_possible; 669 int (*set_cont_read)(struct spinand_device *spinand, 670 bool enable); 671 672 const struct spinand_fact_otp *fact_otp; 673 const struct spinand_user_otp *user_otp; 674 675 unsigned int read_retries; 676 int (*set_read_retry)(struct spinand_device *spinand, 677 unsigned int retry_mode); 678}; 679 680/** 681 * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance 682 * @mtd: MTD instance 683 * 684 * Return: the SPI NAND device attached to @mtd. 685 */ 686static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd) 687{ 688 return container_of(mtd_to_nanddev(mtd), struct spinand_device, base); 689} 690 691/** 692 * spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device 693 * @spinand: SPI NAND device 694 * 695 * Return: the MTD device embedded in @spinand. 696 */ 697static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand) 698{ 699 return nanddev_to_mtd(&spinand->base); 700} 701 702/** 703 * nand_to_spinand() - Get the SPI NAND device embedding an NAND object 704 * @nand: NAND object 705 * 706 * Return: the SPI NAND device embedding @nand. 707 */ 708static inline struct spinand_device *nand_to_spinand(struct nand_device *nand) 709{ 710 return container_of(nand, struct spinand_device, base); 711} 712 713/** 714 * spinand_to_nand() - Get the NAND device embedded in a SPI NAND object 715 * @spinand: SPI NAND device 716 * 717 * Return: the NAND device embedded in @spinand. 718 */ 719static inline struct nand_device * 720spinand_to_nand(struct spinand_device *spinand) 721{ 722 return &spinand->base; 723} 724 725/** 726 * spinand_set_of_node - Attach a DT node to a SPI NAND device 727 * @spinand: SPI NAND device 728 * @np: DT node 729 * 730 * Attach a DT node to a SPI NAND device. 731 */ 732static inline void spinand_set_of_node(struct spinand_device *spinand, 733 struct device_node *np) 734{ 735 nanddev_set_of_node(&spinand->base, np); 736} 737 738int spinand_match_and_init(struct spinand_device *spinand, 739 const struct spinand_info *table, 740 unsigned int table_size, 741 enum spinand_readid_method rdid_method); 742 743int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val); 744int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val); 745int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val); 746int spinand_write_enable_op(struct spinand_device *spinand); 747int spinand_select_target(struct spinand_device *spinand, unsigned int target); 748 749int spinand_wait(struct spinand_device *spinand, unsigned long initial_delay_us, 750 unsigned long poll_delay_us, u8 *s); 751 752int spinand_read_page(struct spinand_device *spinand, 753 const struct nand_page_io_req *req); 754 755int spinand_write_page(struct spinand_device *spinand, 756 const struct nand_page_io_req *req); 757 758size_t spinand_otp_page_size(struct spinand_device *spinand); 759size_t spinand_fact_otp_size(struct spinand_device *spinand); 760size_t spinand_user_otp_size(struct spinand_device *spinand); 761 762int spinand_fact_otp_read(struct spinand_device *spinand, loff_t ofs, 763 size_t len, size_t *retlen, u8 *buf); 764int spinand_user_otp_read(struct spinand_device *spinand, loff_t ofs, 765 size_t len, size_t *retlen, u8 *buf); 766int spinand_user_otp_write(struct spinand_device *spinand, loff_t ofs, 767 size_t len, size_t *retlen, const u8 *buf); 768 769int spinand_set_mtd_otp_ops(struct spinand_device *spinand); 770 771#endif /* __LINUX_MTD_SPINAND_H */
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