host.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 *  linux/include/linux/mmc/host.h
  4 *
  5 *  Host driver specific definitions.
  6 */
  7#ifndef LINUX_MMC_HOST_H
  8#define LINUX_MMC_HOST_H
  9
 10#include <linux/sched.h>
 11#include <linux/device.h>
 12#include <linux/fault-inject.h>
 13#include <linux/debugfs.h>
 14
 15#include <linux/mmc/core.h>
 16#include <linux/mmc/card.h>
 17#include <linux/mmc/pm.h>
 18#include <linux/dma-direction.h>
 19#include <linux/blk-crypto-profile.h>
 20#include <linux/mmc/sd_uhs2.h>
 21
 22struct mmc_ios {
 23	unsigned int	clock;			/* clock rate */
 24	unsigned short	vdd;
 25	unsigned int	power_delay_ms;		/* waiting for stable power */
 26
 27/* vdd stores the bit number of the selected voltage range from below. */
 28
 29	unsigned char	bus_mode;		/* command output mode */
 30
 31#define MMC_BUSMODE_OPENDRAIN	1
 32#define MMC_BUSMODE_PUSHPULL	2
 33
 34	unsigned char	chip_select;		/* SPI chip select */
 35
 36#define MMC_CS_DONTCARE		0
 37#define MMC_CS_HIGH		1
 38#define MMC_CS_LOW		2
 39
 40	unsigned char	power_mode;		/* power supply mode */
 41
 42#define MMC_POWER_OFF		0
 43#define MMC_POWER_UP		1
 44#define MMC_POWER_ON		2
 45#define MMC_POWER_UNDEFINED	3
 46
 47	unsigned char	bus_width;		/* data bus width */
 48
 49#define MMC_BUS_WIDTH_1		0
 50#define MMC_BUS_WIDTH_4		2
 51#define MMC_BUS_WIDTH_8		3
 52
 53	unsigned char	timing;			/* timing specification used */
 54
 55#define MMC_TIMING_LEGACY	0
 56#define MMC_TIMING_MMC_HS	1
 57#define MMC_TIMING_SD_HS	2
 58#define MMC_TIMING_UHS_SDR12	3
 59#define MMC_TIMING_UHS_SDR25	4
 60#define MMC_TIMING_UHS_SDR50	5
 61#define MMC_TIMING_UHS_SDR104	6
 62#define MMC_TIMING_UHS_DDR50	7
 63#define MMC_TIMING_MMC_DDR52	8
 64#define MMC_TIMING_MMC_HS200	9
 65#define MMC_TIMING_MMC_HS400	10
 66#define MMC_TIMING_SD_EXP	11
 67#define MMC_TIMING_SD_EXP_1_2V	12
 68#define MMC_TIMING_UHS2_SPEED_A    13
 69#define MMC_TIMING_UHS2_SPEED_A_HD 14
 70#define MMC_TIMING_UHS2_SPEED_B    15
 71#define MMC_TIMING_UHS2_SPEED_B_HD 16
 72
 73	unsigned char	signal_voltage;		/* signalling voltage (1.8V or 3.3V) */
 74
 75#define MMC_SIGNAL_VOLTAGE_330	0
 76#define MMC_SIGNAL_VOLTAGE_180	1
 77#define MMC_SIGNAL_VOLTAGE_120	2
 78
 79	unsigned char	vqmmc2_voltage;
 80#define MMC_VQMMC2_VOLTAGE_180	0
 81
 82	unsigned char	drv_type;		/* driver type (A, B, C, D) */
 83
 84#define MMC_SET_DRIVER_TYPE_B	0
 85#define MMC_SET_DRIVER_TYPE_A	1
 86#define MMC_SET_DRIVER_TYPE_C	2
 87#define MMC_SET_DRIVER_TYPE_D	3
 88
 89	bool enhanced_strobe;			/* hs400es selection */
 90};
 91
 92struct mmc_clk_phase {
 93	bool valid;
 94	u16 in_deg;
 95	u16 out_deg;
 96};
 97
 98#define MMC_NUM_CLK_PHASES (MMC_TIMING_MMC_HS400 + 1)
 99struct mmc_clk_phase_map {
100	struct mmc_clk_phase phase[MMC_NUM_CLK_PHASES];
101};
102
103struct sd_uhs2_caps {
104	u32	dap;
105	u32	gap;
106	u32	group_desc;
107	u32	maxblk_len;
108	u32	n_fcu;
109	u8	n_lanes;
110	u8	addr64;
111	u8	card_type;
112	u8	phy_rev;
113	u8	speed_range;
114	u8	n_lss_sync;
115	u8	n_lss_dir;
116	u8	link_rev;
117	u8	host_type;
118	u8	n_data_gap;
119
120	u32	maxblk_len_set;
121	u32	n_fcu_set;
122	u8	n_lanes_set;
123	u8	n_lss_sync_set;
124	u8	n_lss_dir_set;
125	u8	n_data_gap_set;
126	u8	max_retry_set;
127};
128
129enum sd_uhs2_operation {
130	UHS2_PHY_INIT = 0,
131	UHS2_SET_CONFIG,
132	UHS2_ENABLE_INT,
133	UHS2_DISABLE_INT,
134	UHS2_ENABLE_CLK,
135	UHS2_DISABLE_CLK,
136	UHS2_CHECK_DORMANT,
137	UHS2_SET_IOS,
138};
139
140struct mmc_host;
141
142enum mmc_err_stat {
143	MMC_ERR_CMD_TIMEOUT,
144	MMC_ERR_CMD_CRC,
145	MMC_ERR_DAT_TIMEOUT,
146	MMC_ERR_DAT_CRC,
147	MMC_ERR_AUTO_CMD,
148	MMC_ERR_ADMA,
149	MMC_ERR_TUNING,
150	MMC_ERR_CMDQ_RED,
151	MMC_ERR_CMDQ_GCE,
152	MMC_ERR_CMDQ_ICCE,
153	MMC_ERR_REQ_TIMEOUT,
154	MMC_ERR_CMDQ_REQ_TIMEOUT,
155	MMC_ERR_ICE_CFG,
156	MMC_ERR_CTRL_TIMEOUT,
157	MMC_ERR_UNEXPECTED_IRQ,
158	MMC_ERR_MAX,
159};
160
161struct mmc_host_ops {
162	/*
163	 * It is optional for the host to implement pre_req and post_req in
164	 * order to support double buffering of requests (prepare one
165	 * request while another request is active).
166	 * pre_req() must always be followed by a post_req().
167	 * To undo a call made to pre_req(), call post_req() with
168	 * a nonzero err condition.
169	 */
170	void	(*post_req)(struct mmc_host *host, struct mmc_request *req,
171			    int err);
172	void	(*pre_req)(struct mmc_host *host, struct mmc_request *req);
173	void	(*request)(struct mmc_host *host, struct mmc_request *req);
174	/* Submit one request to host in atomic context. */
175	int	(*request_atomic)(struct mmc_host *host,
176				  struct mmc_request *req);
177
178	/*
179	 * Avoid calling the next three functions too often or in a "fast
180	 * path", since underlaying controller might implement them in an
181	 * expensive and/or slow way. Also note that these functions might
182	 * sleep, so don't call them in the atomic contexts!
183	 */
184
185	/*
186	 * Notes to the set_ios callback:
187	 * ios->clock might be 0. For some controllers, setting 0Hz
188	 * as any other frequency works. However, some controllers
189	 * explicitly need to disable the clock. Otherwise e.g. voltage
190	 * switching might fail because the SDCLK is not really quiet.
191	 */
192	void	(*set_ios)(struct mmc_host *host, struct mmc_ios *ios);
193
194	/*
195	 * Return values for the get_ro callback should be:
196	 *   0 for a read/write card
197	 *   1 for a read-only card
198	 *   -ENOSYS when not supported (equal to NULL callback)
199	 *   or a negative errno value when something bad happened
200	 */
201	int	(*get_ro)(struct mmc_host *host);
202
203	/*
204	 * Return values for the get_cd callback should be:
205	 *   0 for a absent card
206	 *   1 for a present card
207	 *   -ENOSYS when not supported (equal to NULL callback)
208	 *   or a negative errno value when something bad happened
209	 */
210	int	(*get_cd)(struct mmc_host *host);
211
212	void	(*enable_sdio_irq)(struct mmc_host *host, int enable);
213	/* Mandatory callback when using MMC_CAP2_SDIO_IRQ_NOTHREAD. */
214	void	(*ack_sdio_irq)(struct mmc_host *host);
215
216	/* optional callback for HC quirks */
217	void	(*init_card)(struct mmc_host *host, struct mmc_card *card);
218
219	int	(*start_signal_voltage_switch)(struct mmc_host *host, struct mmc_ios *ios);
220
221	/* Check if the card is pulling dat[0] low */
222	int	(*card_busy)(struct mmc_host *host);
223
224	/* The tuning command opcode value is different for SD and eMMC cards */
225	int	(*execute_tuning)(struct mmc_host *host, u32 opcode);
226
227	/* Prepare HS400 target operating frequency depending host driver */
228	int	(*prepare_hs400_tuning)(struct mmc_host *host, struct mmc_ios *ios);
229
230	/* Execute HS400 tuning depending host driver */
231	int	(*execute_hs400_tuning)(struct mmc_host *host, struct mmc_card *card);
232
233	/* Optional callback to prepare for SD high-speed tuning */
234	int	(*prepare_sd_hs_tuning)(struct mmc_host *host, struct mmc_card *card);
235
236	/* Optional callback to execute SD high-speed tuning */
237	int	(*execute_sd_hs_tuning)(struct mmc_host *host, struct mmc_card *card);
238
239	/* Prepare switch to DDR during the HS400 init sequence */
240	int	(*hs400_prepare_ddr)(struct mmc_host *host);
241
242	/* Prepare for switching from HS400 to HS200 */
243	void	(*hs400_downgrade)(struct mmc_host *host);
244
245	/* Complete selection of HS400 */
246	void	(*hs400_complete)(struct mmc_host *host);
247
248	/* Prepare enhanced strobe depending host driver */
249	void	(*hs400_enhanced_strobe)(struct mmc_host *host,
250					 struct mmc_ios *ios);
251	int	(*select_drive_strength)(struct mmc_card *card,
252					 unsigned int max_dtr, int host_drv,
253					 int card_drv, int *drv_type);
254	/* Reset the eMMC card via RST_n */
255	void	(*card_hw_reset)(struct mmc_host *host);
256	void	(*card_event)(struct mmc_host *host);
257
258	/*
259	 * Optional callback to support controllers with HW issues for multiple
260	 * I/O. Returns the number of supported blocks for the request.
261	 */
262	int	(*multi_io_quirk)(struct mmc_card *card,
263				  unsigned int direction, int blk_size);
264
265	/* Initialize an SD express card, mandatory for MMC_CAP2_SD_EXP. */
266	int	(*init_sd_express)(struct mmc_host *host, struct mmc_ios *ios);
267
268	/*
269	 * The uhs2_control callback is used to execute SD UHS-II specific
270	 * operations. It's mandatory to implement for hosts that supports the
271	 * SD UHS-II interface (MMC_CAP2_SD_UHS2). Expected return values are a
272	 * negative errno in case of a failure or zero for success.
273	 */
274	int	(*uhs2_control)(struct mmc_host *host, enum sd_uhs2_operation op);
275};
276
277struct mmc_cqe_ops {
278	/* Allocate resources, and make the CQE operational */
279	int	(*cqe_enable)(struct mmc_host *host, struct mmc_card *card);
280	/* Free resources, and make the CQE non-operational */
281	void	(*cqe_disable)(struct mmc_host *host);
282	/*
283	 * Issue a read, write or DCMD request to the CQE. Also deal with the
284	 * effect of ->cqe_off().
285	 */
286	int	(*cqe_request)(struct mmc_host *host, struct mmc_request *mrq);
287	/* Free resources (e.g. DMA mapping) associated with the request */
288	void	(*cqe_post_req)(struct mmc_host *host, struct mmc_request *mrq);
289	/*
290	 * Prepare the CQE and host controller to accept non-CQ commands. There
291	 * is no corresponding ->cqe_on(), instead ->cqe_request() is required
292	 * to deal with that.
293	 */
294	void	(*cqe_off)(struct mmc_host *host);
295	/*
296	 * Wait for all CQE tasks to complete. Return an error if recovery
297	 * becomes necessary.
298	 */
299	int	(*cqe_wait_for_idle)(struct mmc_host *host);
300	/*
301	 * Notify CQE that a request has timed out. Return false if the request
302	 * completed or true if a timeout happened in which case indicate if
303	 * recovery is needed.
304	 */
305	bool	(*cqe_timeout)(struct mmc_host *host, struct mmc_request *mrq,
306			       bool *recovery_needed);
307	/*
308	 * Stop all CQE activity and prepare the CQE and host controller to
309	 * accept recovery commands.
310	 */
311	void	(*cqe_recovery_start)(struct mmc_host *host);
312	/*
313	 * Clear the queue and call mmc_cqe_request_done() on all requests.
314	 * Requests that errored will have the error set on the mmc_request
315	 * (data->error or cmd->error for DCMD).  Requests that did not error
316	 * will have zero data bytes transferred.
317	 */
318	void	(*cqe_recovery_finish)(struct mmc_host *host);
319};
320
321/**
322 * struct mmc_slot - MMC slot functions
323 *
324 * @cd_irq:		MMC/SD-card slot hotplug detection IRQ or -EINVAL
325 * @handler_priv:	MMC/SD-card slot context
326 *
327 * Some MMC/SD host controllers implement slot-functions like card and
328 * write-protect detection natively. However, a large number of controllers
329 * leave these functions to the CPU. This struct provides a hook to attach
330 * such slot-function drivers.
331 */
332struct mmc_slot {
333	int cd_irq;
334	bool cd_wake_enabled;
335	void *handler_priv;
336};
337
338struct regulator;
339struct mmc_pwrseq;
340struct notifier_block;
341
342struct mmc_supply {
343	struct regulator *vmmc;		/* Card power supply */
344	struct regulator *vqmmc;	/* Optional Vccq supply */
345	struct regulator *vqmmc2;	/* Optional supply for phy */
346
347	struct notifier_block vmmc_nb;	/* Notifier for vmmc */
348	struct work_struct uv_work;	/* Undervoltage work */
349};
350
351struct mmc_ctx {
352	struct task_struct *task;
353};
354
355struct mmc_host {
356	struct device		*parent;
357	struct device		class_dev;
358	int			index;
359	const struct mmc_host_ops *ops;
360	struct mmc_pwrseq	*pwrseq;
361	unsigned int		f_min;
362	unsigned int		f_max;
363	unsigned int		f_init;
364	u32			ocr_avail;
365	u32			ocr_avail_sdio;	/* SDIO-specific OCR */
366	u32			ocr_avail_sd;	/* SD-specific OCR */
367	u32			ocr_avail_mmc;	/* MMC-specific OCR */
368	struct wakeup_source	*ws;		/* Enable consume of uevents */
369	u32			max_current_330;
370	u32			max_current_300;
371	u32			max_current_180;
372
373#define MMC_VDD_165_195		0x00000080	/* VDD voltage 1.65 - 1.95 */
374#define MMC_VDD_20_21		0x00000100	/* VDD voltage 2.0 ~ 2.1 */
375#define MMC_VDD_21_22		0x00000200	/* VDD voltage 2.1 ~ 2.2 */
376#define MMC_VDD_22_23		0x00000400	/* VDD voltage 2.2 ~ 2.3 */
377#define MMC_VDD_23_24		0x00000800	/* VDD voltage 2.3 ~ 2.4 */
378#define MMC_VDD_24_25		0x00001000	/* VDD voltage 2.4 ~ 2.5 */
379#define MMC_VDD_25_26		0x00002000	/* VDD voltage 2.5 ~ 2.6 */
380#define MMC_VDD_26_27		0x00004000	/* VDD voltage 2.6 ~ 2.7 */
381#define MMC_VDD_27_28		0x00008000	/* VDD voltage 2.7 ~ 2.8 */
382#define MMC_VDD_28_29		0x00010000	/* VDD voltage 2.8 ~ 2.9 */
383#define MMC_VDD_29_30		0x00020000	/* VDD voltage 2.9 ~ 3.0 */
384#define MMC_VDD_30_31		0x00040000	/* VDD voltage 3.0 ~ 3.1 */
385#define MMC_VDD_31_32		0x00080000	/* VDD voltage 3.1 ~ 3.2 */
386#define MMC_VDD_32_33		0x00100000	/* VDD voltage 3.2 ~ 3.3 */
387#define MMC_VDD_33_34		0x00200000	/* VDD voltage 3.3 ~ 3.4 */
388#define MMC_VDD_34_35		0x00400000	/* VDD voltage 3.4 ~ 3.5 */
389#define MMC_VDD_35_36		0x00800000	/* VDD voltage 3.5 ~ 3.6 */
390
391	u32			caps;		/* Host capabilities */
392
393#define MMC_CAP_4_BIT_DATA	(1 << 0)	/* Can the host do 4 bit transfers */
394#define MMC_CAP_MMC_HIGHSPEED	(1 << 1)	/* Can do MMC high-speed timing */
395#define MMC_CAP_SD_HIGHSPEED	(1 << 2)	/* Can do SD high-speed timing */
396#define MMC_CAP_SDIO_IRQ	(1 << 3)	/* Can signal pending SDIO IRQs */
397#define MMC_CAP_SPI		(1 << 4)	/* Talks only SPI protocols */
398#define MMC_CAP_NEEDS_POLL	(1 << 5)	/* Needs polling for card-detection */
399#define MMC_CAP_8_BIT_DATA	(1 << 6)	/* Can the host do 8 bit transfers */
400#define MMC_CAP_AGGRESSIVE_PM	(1 << 7)	/* Suspend (e)MMC/SD at idle  */
401#define MMC_CAP_NONREMOVABLE	(1 << 8)	/* Nonremovable e.g. eMMC */
402#define MMC_CAP_WAIT_WHILE_BUSY	(1 << 9)	/* Waits while card is busy */
403#define MMC_CAP_3_3V_DDR	(1 << 11)	/* Host supports eMMC DDR 3.3V */
404#define MMC_CAP_1_8V_DDR	(1 << 12)	/* Host supports eMMC DDR 1.8V */
405#define MMC_CAP_1_2V_DDR	(1 << 13)	/* Host supports eMMC DDR 1.2V */
406#define MMC_CAP_DDR		(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR | \
407				 MMC_CAP_1_2V_DDR)
408#define MMC_CAP_POWER_OFF_CARD	(1 << 14)	/* Can power off after boot */
409#define MMC_CAP_BUS_WIDTH_TEST	(1 << 15)	/* CMD14/CMD19 bus width ok */
410#define MMC_CAP_UHS_SDR12	(1 << 16)	/* Host supports UHS SDR12 mode */
411#define MMC_CAP_UHS_SDR25	(1 << 17)	/* Host supports UHS SDR25 mode */
412#define MMC_CAP_UHS_SDR50	(1 << 18)	/* Host supports UHS SDR50 mode */
413#define MMC_CAP_UHS_SDR104	(1 << 19)	/* Host supports UHS SDR104 mode */
414#define MMC_CAP_UHS_DDR50	(1 << 20)	/* Host supports UHS DDR50 mode */
415#define MMC_CAP_UHS		(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | \
416				 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | \
417				 MMC_CAP_UHS_DDR50)
418#define MMC_CAP_SYNC_RUNTIME_PM	(1 << 21)	/* Synced runtime PM suspends. */
419#define MMC_CAP_NEED_RSP_BUSY	(1 << 22)	/* Commands with R1B can't use R1. */
420#define MMC_CAP_DRIVER_TYPE_A	(1 << 23)	/* Host supports Driver Type A */
421#define MMC_CAP_DRIVER_TYPE_C	(1 << 24)	/* Host supports Driver Type C */
422#define MMC_CAP_DRIVER_TYPE_D	(1 << 25)	/* Host supports Driver Type D */
423#define MMC_CAP_DONE_COMPLETE	(1 << 27)	/* RW reqs can be completed within mmc_request_done() */
424#define MMC_CAP_CD_WAKE		(1 << 28)	/* Enable card detect wake */
425#define MMC_CAP_CMD_DURING_TFR	(1 << 29)	/* Commands during data transfer */
426#define MMC_CAP_CMD23		(1 << 30)	/* CMD23 supported. */
427#define MMC_CAP_HW_RESET	(1 << 31)	/* Reset the eMMC card via RST_n */
428
429	u32			caps2;		/* More host capabilities */
430
431#define MMC_CAP2_BOOTPART_NOACC	(1 << 0)	/* Boot partition no access */
432#define MMC_CAP2_FULL_PWR_CYCLE	(1 << 2)	/* Can do full power cycle */
433#define MMC_CAP2_FULL_PWR_CYCLE_IN_SUSPEND (1 << 3) /* Can do full power cycle in suspend */
434#define MMC_CAP2_HS200_1_8V_SDR	(1 << 5)        /* can support */
435#define MMC_CAP2_HS200_1_2V_SDR	(1 << 6)        /* can support */
436#define MMC_CAP2_HS200		(MMC_CAP2_HS200_1_8V_SDR | \
437				 MMC_CAP2_HS200_1_2V_SDR)
438#define MMC_CAP2_SD_EXP		(1 << 7)	/* SD express via PCIe */
439#define MMC_CAP2_SD_EXP_1_2V	(1 << 8)	/* SD express 1.2V */
440#define MMC_CAP2_SD_UHS2	(1 << 9)	/* SD UHS-II support */
441#define MMC_CAP2_CD_ACTIVE_HIGH	(1 << 10)	/* Card-detect signal active high */
442#define MMC_CAP2_RO_ACTIVE_HIGH	(1 << 11)	/* Write-protect signal active high */
443#define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14)	/* Don't power up before scan */
444#define MMC_CAP2_HS400_1_8V	(1 << 15)	/* Can support HS400 1.8V */
445#define MMC_CAP2_HS400_1_2V	(1 << 16)	/* Can support HS400 1.2V */
446#define MMC_CAP2_HS400		(MMC_CAP2_HS400_1_8V | \
447				 MMC_CAP2_HS400_1_2V)
448#define MMC_CAP2_HSX00_1_8V	(MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)
449#define MMC_CAP2_HSX00_1_2V	(MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V)
450#define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17)
451#define MMC_CAP2_NO_WRITE_PROTECT (1 << 18)	/* No physical write protect pin, assume that card is always read-write */
452#define MMC_CAP2_NO_SDIO	(1 << 19)	/* Do not send SDIO commands during initialization */
453#define MMC_CAP2_HS400_ES	(1 << 20)	/* Host supports enhanced strobe */
454#define MMC_CAP2_NO_SD		(1 << 21)	/* Do not send SD commands during initialization */
455#define MMC_CAP2_NO_MMC		(1 << 22)	/* Do not send (e)MMC commands during initialization */
456#define MMC_CAP2_CQE		(1 << 23)	/* Has eMMC command queue engine */
457#define MMC_CAP2_CQE_DCMD	(1 << 24)	/* CQE can issue a direct command */
458#define MMC_CAP2_AVOID_3_3V	(1 << 25)	/* Host must negotiate down from 3.3V */
459#define MMC_CAP2_MERGE_CAPABLE	(1 << 26)	/* Host can merge a segment over the segment size */
460#ifdef CONFIG_MMC_CRYPTO
461#define MMC_CAP2_CRYPTO		(1 << 27)	/* Host supports inline encryption */
462#else
463#define MMC_CAP2_CRYPTO		0
464#endif
465#define MMC_CAP2_ALT_GPT_TEGRA	(1 << 28)	/* Host with eMMC that has GPT entry at a non-standard location */
466
467	bool			uhs2_sd_tran;	/* UHS-II flag for SD_TRAN state */
468	bool			uhs2_app_cmd;	/* UHS-II flag for APP command */
469	struct sd_uhs2_caps	uhs2_caps;	/* Host UHS-II capabilities */
470
471	int			fixed_drv_type;	/* fixed driver type for non-removable media */
472
473	mmc_pm_flag_t		pm_caps;	/* supported pm features */
474
475	/* host specific block data */
476	unsigned int		max_seg_size;	/* lim->max_segment_size */
477	unsigned short		max_segs;	/* lim->max_segments */
478	unsigned short		unused;
479	unsigned int		max_req_size;	/* maximum number of bytes in one req */
480	unsigned int		max_blk_size;	/* maximum size of one mmc block */
481	unsigned int		max_blk_count;	/* maximum number of blocks in one req */
482	unsigned int		max_busy_timeout; /* max busy timeout in ms */
483
484	/* private data */
485	spinlock_t		lock;		/* lock for claim and bus ops */
486
487	struct mmc_ios		ios;		/* current io bus settings */
488
489	bool			claimed;	/* host exclusively claimed */
490
491	/* group bitfields together to minimize padding */
492	unsigned int		use_spi_crc:1;
493	unsigned int		doing_init_tune:1; /* initial tuning in progress */
494	unsigned int		doing_retune:1;	/* re-tuning in progress */
495	unsigned int		retune_crc_disable:1; /* don't trigger retune upon crc */
496	unsigned int		can_dma_map_merge:1; /* merging can be used */
497	unsigned int		vqmmc_enabled:1; /* vqmmc regulator is enabled */
498
499	/*
500	 * Indicates if an undervoltage event has already been handled.
501	 * This prevents repeated regulator notifiers from triggering
502	 * multiple REGULATOR_EVENT_UNDER_VOLTAGE events.
503	 */
504	unsigned int		undervoltage:1;	 /* Undervoltage state */
505
506	int			rescan_disable;	/* disable card detection */
507	int			rescan_entered;	/* used with nonremovable devices */
508
509	bool			can_retune;	/* re-tuning can be used */
510	bool			retune_now;	/* do re-tuning at next req */
511	bool			retune_paused;	/* re-tuning is temporarily disabled */
512	int			need_retune;	/* re-tuning is needed */
513	int			hold_retune;	/* hold off re-tuning */
514	unsigned int		retune_period;	/* re-tuning period in secs */
515	struct timer_list	retune_timer;	/* for periodic re-tuning */
516
517	bool			trigger_card_event; /* card_event necessary */
518
519	struct mmc_card		*card;		/* device attached to this host */
520
521	wait_queue_head_t	wq;
522	struct mmc_ctx		*claimer;	/* context that has host claimed */
523	int			claim_cnt;	/* "claim" nesting count */
524	struct mmc_ctx		default_ctx;	/* default context */
525
526	struct delayed_work	detect;
527	int			detect_change;	/* card detect flag */
528	struct mmc_slot		slot;
529
530	const struct mmc_bus_ops *bus_ops;	/* current bus driver */
531
532	unsigned int		sdio_irqs;
533	struct task_struct	*sdio_irq_thread;
534	struct work_struct	sdio_irq_work;
535	bool			sdio_irq_pending;
536	atomic_t		sdio_irq_thread_abort;
537
538	mmc_pm_flag_t		pm_flags;	/* requested pm features */
539
540	struct led_trigger	*led;		/* activity led */
541
542#ifdef CONFIG_REGULATOR
543	bool			regulator_enabled; /* regulator state */
544#endif
545	struct mmc_supply	supply;
546
547	struct dentry		*debugfs_root;
548
549	/* Ongoing data transfer that allows commands during transfer */
550	struct mmc_request	*ongoing_mrq;
551
552#ifdef CONFIG_FAIL_MMC_REQUEST
553	struct fault_attr	fail_mmc_request;
554#endif
555
556	unsigned int		actual_clock;	/* Actual HC clock rate */
557
558	unsigned int		slotno;	/* used for sdio acpi binding */
559
560	int			dsr_req;	/* DSR value is valid */
561	u32			dsr;	/* optional driver stage (DSR) value */
562
563	/* Command Queue Engine (CQE) support */
564	const struct mmc_cqe_ops *cqe_ops;
565	void			*cqe_private;
566	int			cqe_qdepth;
567	bool			cqe_enabled;
568	bool			cqe_on;
569
570	/* Inline encryption support */
571#ifdef CONFIG_MMC_CRYPTO
572	struct blk_crypto_profile crypto_profile;
573#endif
574
575	/* Host Software Queue support */
576	bool			hsq_enabled;
577	int			hsq_depth;
578
579	u32			err_stats[MMC_ERR_MAX];
580	u32			max_sd_hs_hz;
581	unsigned long		private[] ____cacheline_aligned;
582};
583
584struct device_node;
585
586struct mmc_host *mmc_alloc_host(int extra, struct device *);
587struct mmc_host *devm_mmc_alloc_host(struct device *dev, int extra);
588int mmc_add_host(struct mmc_host *);
589void mmc_remove_host(struct mmc_host *);
590void mmc_free_host(struct mmc_host *);
591void mmc_of_parse_clk_phase(struct device *dev,
592			    struct mmc_clk_phase_map *map);
593int mmc_of_parse(struct mmc_host *host);
594int mmc_of_parse_voltage(struct mmc_host *host, u32 *mask);
595
596static inline void *mmc_priv(struct mmc_host *host)
597{
598	return (void *)host->private;
599}
600
601static inline struct mmc_host *mmc_from_priv(void *priv)
602{
603	return container_of(priv, struct mmc_host, private);
604}
605
606#ifdef CONFIG_MMC_CRYPTO
607static inline struct mmc_host *
608mmc_from_crypto_profile(struct blk_crypto_profile *profile)
609{
610	return container_of(profile, struct mmc_host, crypto_profile);
611}
612#endif
613
614#define mmc_host_is_spi(host)	((host)->caps & MMC_CAP_SPI)
615
616#define mmc_dev(x)	((x)->parent)
617#define mmc_classdev(x)	(&(x)->class_dev)
618#define mmc_hostname(x)	(dev_name(&(x)->class_dev))
619
620void mmc_detect_change(struct mmc_host *, unsigned long delay);
621void mmc_request_done(struct mmc_host *, struct mmc_request *);
622void mmc_command_done(struct mmc_host *host, struct mmc_request *mrq);
623
624void mmc_cqe_request_done(struct mmc_host *host, struct mmc_request *mrq);
625
626/*
627 * May be called from host driver's system/runtime suspend/resume callbacks,
628 * to know if SDIO IRQs has been claimed.
629 */
630static inline bool sdio_irq_claimed(struct mmc_host *host)
631{
632	return host->sdio_irqs > 0;
633}
634
635static inline void mmc_signal_sdio_irq(struct mmc_host *host)
636{
637	host->ops->enable_sdio_irq(host, 0);
638	host->sdio_irq_pending = true;
639	if (host->sdio_irq_thread)
640		wake_up_process(host->sdio_irq_thread);
641}
642
643void sdio_signal_irq(struct mmc_host *host);
644
645#ifdef CONFIG_REGULATOR
646int mmc_regulator_set_ocr(struct mmc_host *mmc,
647			struct regulator *supply,
648			unsigned short vdd_bit);
649int mmc_regulator_set_vqmmc(struct mmc_host *mmc, struct mmc_ios *ios);
650int mmc_regulator_set_vqmmc2(struct mmc_host *mmc, struct mmc_ios *ios);
651#else
652static inline int mmc_regulator_set_ocr(struct mmc_host *mmc,
653				 struct regulator *supply,
654				 unsigned short vdd_bit)
655{
656	return 0;
657}
658
659static inline int mmc_regulator_set_vqmmc(struct mmc_host *mmc,
660					  struct mmc_ios *ios)
661{
662	return -EINVAL;
663}
664
665static inline int mmc_regulator_set_vqmmc2(struct mmc_host *mmc,
666					   struct mmc_ios *ios)
667{
668	return -EINVAL;
669}
670#endif
671
672int mmc_regulator_get_supply(struct mmc_host *mmc);
673int mmc_regulator_enable_vqmmc(struct mmc_host *mmc);
674void mmc_regulator_disable_vqmmc(struct mmc_host *mmc);
675
676static inline int mmc_card_is_removable(struct mmc_host *host)
677{
678	return !(host->caps & MMC_CAP_NONREMOVABLE);
679}
680
681static inline int mmc_card_keep_power(struct mmc_host *host)
682{
683	return host->pm_flags & MMC_PM_KEEP_POWER;
684}
685
686static inline int mmc_card_wake_sdio_irq(struct mmc_host *host)
687{
688	return host->pm_flags & MMC_PM_WAKE_SDIO_IRQ;
689}
690
691/* TODO: Move to private header */
692static inline int mmc_card_hs(struct mmc_card *card)
693{
694	return card->host->ios.timing == MMC_TIMING_SD_HS ||
695		card->host->ios.timing == MMC_TIMING_MMC_HS;
696}
697
698/* TODO: Move to private header */
699static inline int mmc_card_uhs(struct mmc_card *card)
700{
701	return card->host->ios.timing >= MMC_TIMING_UHS_SDR12 &&
702		card->host->ios.timing <= MMC_TIMING_UHS_DDR50;
703}
704
705static inline bool mmc_card_uhs2(struct mmc_host *host)
706{
707	return host->ios.timing == MMC_TIMING_UHS2_SPEED_A ||
708	       host->ios.timing == MMC_TIMING_UHS2_SPEED_A_HD ||
709	       host->ios.timing == MMC_TIMING_UHS2_SPEED_B ||
710	       host->ios.timing == MMC_TIMING_UHS2_SPEED_B_HD;
711}
712
713void mmc_retune_timer_stop(struct mmc_host *host);
714
715static inline void mmc_retune_needed(struct mmc_host *host)
716{
717	if (host->can_retune)
718		host->need_retune = 1;
719}
720
721static inline bool mmc_can_retune(struct mmc_host *host)
722{
723	return host->can_retune == 1;
724}
725
726static inline bool mmc_doing_retune(struct mmc_host *host)
727{
728	return host->doing_retune == 1;
729}
730
731static inline bool mmc_doing_tune(struct mmc_host *host)
732{
733	return host->doing_retune == 1 || host->doing_init_tune == 1;
734}
735
736static inline enum dma_data_direction mmc_get_dma_dir(struct mmc_data *data)
737{
738	return data->flags & MMC_DATA_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
739}
740
741static inline void mmc_debugfs_err_stats_inc(struct mmc_host *host,
742					     enum mmc_err_stat stat)
743{
744	host->err_stats[stat] += 1;
745}
746
747static inline int mmc_card_uhs2_hd_mode(struct mmc_host *host)
748{
749	return host->ios.timing == MMC_TIMING_UHS2_SPEED_A_HD ||
750	       host->ios.timing == MMC_TIMING_UHS2_SPEED_B_HD;
751}
752
753int mmc_sd_switch(struct mmc_card *card, bool mode, int group,
754		u8 value, u8 *resp);
755int mmc_send_status(struct mmc_card *card, u32 *status);
756int mmc_send_tuning(struct mmc_host *host, u32 opcode, int *cmd_error);
757int mmc_send_abort_tuning(struct mmc_host *host, u32 opcode);
758int mmc_get_ext_csd(struct mmc_card *card, u8 **new_ext_csd);
759int mmc_read_tuning(struct mmc_host *host, unsigned int blksz, unsigned int blocks);
760
761#endif /* LINUX_MMC_HOST_H */