mlx5_ifc_vdpa.h

  1/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
  2/* Copyright (c) 2020 Mellanox Technologies Ltd. */
  3
  4#ifndef __MLX5_IFC_VDPA_H_
  5#define __MLX5_IFC_VDPA_H_
  6
  7enum {
  8	MLX5_VIRTIO_Q_EVENT_MODE_NO_MSIX_MODE  = 0x0,
  9	MLX5_VIRTIO_Q_EVENT_MODE_QP_MODE       = 0x1,
 10	MLX5_VIRTIO_Q_EVENT_MODE_MSIX_MODE     = 0x2,
 11};
 12
 13enum {
 14	MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYPE_SPLIT   = 0,
 15	MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYPE_PACKED  = 1,
 16};
 17
 18enum {
 19	MLX5_VIRTIO_EMULATION_CAP_VIRTIO_QUEUE_TYPE_SPLIT =
 20		BIT(MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYPE_SPLIT),
 21	MLX5_VIRTIO_EMULATION_CAP_VIRTIO_QUEUE_TYPE_PACKED =
 22		BIT(MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYPE_PACKED),
 23};
 24
 25struct mlx5_ifc_virtio_q_bits {
 26	u8    virtio_q_type[0x8];
 27	u8    reserved_at_8[0x5];
 28	u8    event_mode[0x3];
 29	u8    queue_index[0x10];
 30
 31	u8    full_emulation[0x1];
 32	u8    virtio_version_1_0[0x1];
 33	u8    reserved_at_22[0x2];
 34	u8    offload_type[0x4];
 35	u8    event_qpn_or_msix[0x18];
 36
 37	u8    doorbell_stride_index[0x10];
 38	u8    queue_size[0x10];
 39
 40	u8    device_emulation_id[0x20];
 41
 42	u8    desc_addr[0x40];
 43
 44	u8    used_addr[0x40];
 45
 46	u8    available_addr[0x40];
 47
 48	u8    virtio_q_mkey[0x20];
 49
 50	u8    max_tunnel_desc[0x10];
 51	u8    reserved_at_170[0x8];
 52	u8    error_type[0x8];
 53
 54	u8    umem_1_id[0x20];
 55
 56	u8    umem_1_size[0x20];
 57
 58	u8    umem_1_offset[0x40];
 59
 60	u8    umem_2_id[0x20];
 61
 62	u8    umem_2_size[0x20];
 63
 64	u8    umem_2_offset[0x40];
 65
 66	u8    umem_3_id[0x20];
 67
 68	u8    umem_3_size[0x20];
 69
 70	u8    umem_3_offset[0x40];
 71
 72	u8    counter_set_id[0x20];
 73
 74	u8    reserved_at_320[0x8];
 75	u8    pd[0x18];
 76
 77	u8    reserved_at_340[0x20];
 78
 79	u8    desc_group_mkey[0x20];
 80
 81	u8    reserved_at_380[0x80];
 82};
 83
 84struct mlx5_ifc_virtio_net_q_object_bits {
 85	u8    modify_field_select[0x40];
 86
 87	u8    reserved_at_40[0x20];
 88
 89	u8    vhca_id[0x10];
 90	u8    reserved_at_70[0x10];
 91
 92	u8    queue_feature_bit_mask_12_3[0xa];
 93	u8    dirty_bitmap_dump_enable[0x1];
 94	u8    vhost_log_page[0x5];
 95	u8    reserved_at_90[0xc];
 96	u8    state[0x4];
 97
 98	u8    reserved_at_a0[0x5];
 99	u8    queue_feature_bit_mask_2_0[0x3];
100	u8    tisn_or_qpn[0x18];
101
102	u8    dirty_bitmap_mkey[0x20];
103
104	u8    dirty_bitmap_size[0x20];
105
106	u8    dirty_bitmap_addr[0x40];
107
108	u8    hw_available_index[0x10];
109	u8    hw_used_index[0x10];
110
111	u8    reserved_at_160[0xa0];
112
113	struct mlx5_ifc_virtio_q_bits virtio_q_context;
114};
115
116struct mlx5_ifc_create_virtio_net_q_in_bits {
117	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
118
119	struct mlx5_ifc_virtio_net_q_object_bits obj_context;
120};
121
122struct mlx5_ifc_create_virtio_net_q_out_bits {
123	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
124};
125
126struct mlx5_ifc_destroy_virtio_net_q_in_bits {
127	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_out_cmd_hdr;
128};
129
130struct mlx5_ifc_destroy_virtio_net_q_out_bits {
131	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
132};
133
134struct mlx5_ifc_query_virtio_net_q_in_bits {
135	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
136};
137
138struct mlx5_ifc_query_virtio_net_q_out_bits {
139	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
140
141	struct mlx5_ifc_virtio_net_q_object_bits obj_context;
142};
143
144enum {
145	MLX5_VIRTQ_MODIFY_MASK_STATE                    = (u64)1 << 0,
146	MLX5_VIRTQ_MODIFY_MASK_DIRTY_BITMAP_PARAMS      = (u64)1 << 3,
147	MLX5_VIRTQ_MODIFY_MASK_DIRTY_BITMAP_DUMP_ENABLE = (u64)1 << 4,
148	MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_ADDRS           = (u64)1 << 6,
149	MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_AVAIL_IDX       = (u64)1 << 7,
150	MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_USED_IDX        = (u64)1 << 8,
151	MLX5_VIRTQ_MODIFY_MASK_QUEUE_VIRTIO_VERSION	= (u64)1 << 10,
152	MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_MKEY            = (u64)1 << 11,
153	MLX5_VIRTQ_MODIFY_MASK_QUEUE_FEATURES		= (u64)1 << 12,
154	MLX5_VIRTQ_MODIFY_MASK_DESC_GROUP_MKEY          = (u64)1 << 14,
155};
156
157enum {
158	MLX5_VIRTIO_NET_Q_OBJECT_STATE_INIT     = 0x0,
159	MLX5_VIRTIO_NET_Q_OBJECT_STATE_RDY      = 0x1,
160	MLX5_VIRTIO_NET_Q_OBJECT_STATE_SUSPEND  = 0x2,
161	MLX5_VIRTIO_NET_Q_OBJECT_STATE_ERR      = 0x3,
162};
163
164/* This indicates that the object was not created or has already
165 * been desroyed. It is very safe to assume that this object will never
166 * have so many states
167 */
168enum {
169	MLX5_VIRTIO_NET_Q_OBJECT_NONE = 0xffffffff
170};
171
172enum {
173	MLX5_RQTC_LIST_Q_TYPE_RQ            = 0x0,
174	MLX5_RQTC_LIST_Q_TYPE_VIRTIO_NET_Q  = 0x1,
175};
176
177struct mlx5_ifc_modify_virtio_net_q_in_bits {
178	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
179
180	struct mlx5_ifc_virtio_net_q_object_bits obj_context;
181};
182
183struct mlx5_ifc_modify_virtio_net_q_out_bits {
184	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
185};
186
187struct mlx5_ifc_virtio_q_counters_bits {
188	u8    modify_field_select[0x40];
189	u8    reserved_at_40[0x40];
190	u8    received_desc[0x40];
191	u8    completed_desc[0x40];
192	u8    error_cqes[0x20];
193	u8    bad_desc_errors[0x20];
194	u8    exceed_max_chain[0x20];
195	u8    invalid_buffer[0x20];
196	u8    reserved_at_180[0x280];
197};
198
199struct mlx5_ifc_create_virtio_q_counters_in_bits {
200	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
201	struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
202};
203
204struct mlx5_ifc_create_virtio_q_counters_out_bits {
205	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
206	struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
207};
208
209struct mlx5_ifc_destroy_virtio_q_counters_in_bits {
210	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
211};
212
213struct mlx5_ifc_destroy_virtio_q_counters_out_bits {
214	struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr;
215};
216
217struct mlx5_ifc_query_virtio_q_counters_in_bits {
218	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
219};
220
221struct mlx5_ifc_query_virtio_q_counters_out_bits {
222	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
223	struct mlx5_ifc_virtio_q_counters_bits counters;
224};
225
226#endif /* __MLX5_IFC_VDPA_H_ */