device.h

   1/*
   2 * Copyright (c) 2006, 2007 Cisco Systems, Inc.  All rights reserved.
   3 *
   4 * This software is available to you under a choice of one of two
   5 * licenses.  You may choose to be licensed under the terms of the GNU
   6 * General Public License (GPL) Version 2, available from the file
   7 * COPYING in the main directory of this source tree, or the
   8 * OpenIB.org BSD license below:
   9 *
  10 *     Redistribution and use in source and binary forms, with or
  11 *     without modification, are permitted provided that the following
  12 *     conditions are met:
  13 *
  14 *	- Redistributions of source code must retain the above
  15 *	  copyright notice, this list of conditions and the following
  16 *	  disclaimer.
  17 *
  18 *	- Redistributions in binary form must reproduce the above
  19 *	  copyright notice, this list of conditions and the following
  20 *	  disclaimer in the documentation and/or other materials
  21 *	  provided with the distribution.
  22 *
  23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30 * SOFTWARE.
  31 */
  32
  33#ifndef MLX4_DEVICE_H
  34#define MLX4_DEVICE_H
  35
  36#include <linux/auxiliary_bus.h>
  37#include <linux/if_ether.h>
  38#include <linux/pci.h>
  39#include <linux/completion.h>
  40#include <linux/radix-tree.h>
  41#include <linux/cpu_rmap.h>
  42#include <linux/crash_dump.h>
  43
  44#include <linux/refcount.h>
  45
  46#include <linux/timecounter.h>
  47
  48#define DEFAULT_UAR_PAGE_SHIFT  12
  49
  50#define MAX_MSIX		128
  51#define MIN_MSIX_P_PORT		5
  52#define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \
  53					 (dev_cap).num_ports * MIN_MSIX_P_PORT)
  54
  55#define MLX4_MAX_100M_UNITS_VAL		255	/*
  56						 * work around: can't set values
  57						 * greater then this value when
  58						 * using 100 Mbps units.
  59						 */
  60#define MLX4_RATELIMIT_100M_UNITS	3	/* 100 Mbps */
  61#define MLX4_RATELIMIT_1G_UNITS		4	/* 1 Gbps */
  62#define MLX4_RATELIMIT_DEFAULT		0x00ff
  63
  64#define MLX4_ROCE_MAX_GIDS	128
  65#define MLX4_ROCE_PF_GIDS	16
  66
  67enum {
  68	MLX4_FLAG_MSI_X		= 1 << 0,
  69	MLX4_FLAG_OLD_PORT_CMDS	= 1 << 1,
  70	MLX4_FLAG_MASTER	= 1 << 2,
  71	MLX4_FLAG_SLAVE		= 1 << 3,
  72	MLX4_FLAG_SRIOV		= 1 << 4,
  73	MLX4_FLAG_OLD_REG_MAC	= 1 << 6,
  74	MLX4_FLAG_BONDED	= 1 << 7,
  75	MLX4_FLAG_SECURE_HOST	= 1 << 8,
  76};
  77
  78enum {
  79	MLX4_PORT_CAP_IS_SM	= 1 << 1,
  80	MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
  81};
  82
  83enum {
  84	MLX4_MAX_PORTS		= 2,
  85	MLX4_MAX_PORT_PKEYS	= 128,
  86	MLX4_MAX_PORT_GIDS	= 128
  87};
  88
  89/* base qkey for use in sriov tunnel-qp/proxy-qp communication.
  90 * These qkeys must not be allowed for general use. This is a 64k range,
  91 * and to test for violation, we use the mask (protect against future chg).
  92 */
  93#define MLX4_RESERVED_QKEY_BASE  (0xFFFF0000)
  94#define MLX4_RESERVED_QKEY_MASK  (0xFFFF0000)
  95
  96enum {
  97	MLX4_BOARD_ID_LEN = 64
  98};
  99
 100enum {
 101	MLX4_MAX_NUM_PF		= 16,
 102	MLX4_MAX_NUM_VF		= 126,
 103	MLX4_MAX_NUM_VF_P_PORT  = 64,
 104	MLX4_MFUNC_MAX		= 128,
 105	MLX4_MAX_EQ_NUM		= 1024,
 106	MLX4_MFUNC_EQ_NUM	= 4,
 107	MLX4_MFUNC_MAX_EQES     = 8,
 108	MLX4_MFUNC_EQE_MASK     = (MLX4_MFUNC_MAX_EQES - 1)
 109};
 110
 111/* Driver supports 3 different device methods to manage traffic steering:
 112 *	-device managed - High level API for ib and eth flow steering. FW is
 113 *			  managing flow steering tables.
 114 *	- B0 steering mode - Common low level API for ib and (if supported) eth.
 115 *	- A0 steering mode - Limited low level API for eth. In case of IB,
 116 *			     B0 mode is in use.
 117 */
 118enum {
 119	MLX4_STEERING_MODE_A0,
 120	MLX4_STEERING_MODE_B0,
 121	MLX4_STEERING_MODE_DEVICE_MANAGED
 122};
 123
 124enum {
 125	MLX4_STEERING_DMFS_A0_DEFAULT,
 126	MLX4_STEERING_DMFS_A0_DYNAMIC,
 127	MLX4_STEERING_DMFS_A0_STATIC,
 128	MLX4_STEERING_DMFS_A0_DISABLE,
 129	MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
 130};
 131
 132static inline const char *mlx4_steering_mode_str(int steering_mode)
 133{
 134	switch (steering_mode) {
 135	case MLX4_STEERING_MODE_A0:
 136		return "A0 steering";
 137
 138	case MLX4_STEERING_MODE_B0:
 139		return "B0 steering";
 140
 141	case MLX4_STEERING_MODE_DEVICE_MANAGED:
 142		return "Device managed flow steering";
 143
 144	default:
 145		return "Unrecognize steering mode";
 146	}
 147}
 148
 149enum {
 150	MLX4_TUNNEL_OFFLOAD_MODE_NONE,
 151	MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
 152};
 153
 154enum {
 155	MLX4_DEV_CAP_FLAG_RC		= 1LL <<  0,
 156	MLX4_DEV_CAP_FLAG_UC		= 1LL <<  1,
 157	MLX4_DEV_CAP_FLAG_UD		= 1LL <<  2,
 158	MLX4_DEV_CAP_FLAG_XRC		= 1LL <<  3,
 159	MLX4_DEV_CAP_FLAG_SRQ		= 1LL <<  6,
 160	MLX4_DEV_CAP_FLAG_IPOIB_CSUM	= 1LL <<  7,
 161	MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR	= 1LL <<  8,
 162	MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR	= 1LL <<  9,
 163	MLX4_DEV_CAP_FLAG_DPDP		= 1LL << 12,
 164	MLX4_DEV_CAP_FLAG_BLH		= 1LL << 15,
 165	MLX4_DEV_CAP_FLAG_MEM_WINDOW	= 1LL << 16,
 166	MLX4_DEV_CAP_FLAG_APM		= 1LL << 17,
 167	MLX4_DEV_CAP_FLAG_ATOMIC	= 1LL << 18,
 168	MLX4_DEV_CAP_FLAG_RAW_MCAST	= 1LL << 19,
 169	MLX4_DEV_CAP_FLAG_UD_AV_PORT	= 1LL << 20,
 170	MLX4_DEV_CAP_FLAG_UD_MCAST	= 1LL << 21,
 171	MLX4_DEV_CAP_FLAG_IBOE		= 1LL << 30,
 172	MLX4_DEV_CAP_FLAG_UC_LOOPBACK	= 1LL << 32,
 173	MLX4_DEV_CAP_FLAG_FCS_KEEP	= 1LL << 34,
 174	MLX4_DEV_CAP_FLAG_WOL_PORT1	= 1LL << 37,
 175	MLX4_DEV_CAP_FLAG_WOL_PORT2	= 1LL << 38,
 176	MLX4_DEV_CAP_FLAG_UDP_RSS	= 1LL << 40,
 177	MLX4_DEV_CAP_FLAG_VEP_UC_STEER	= 1LL << 41,
 178	MLX4_DEV_CAP_FLAG_VEP_MC_STEER	= 1LL << 42,
 179	MLX4_DEV_CAP_FLAG_COUNTERS	= 1LL << 48,
 180	MLX4_DEV_CAP_FLAG_RSS_IP_FRAG   = 1LL << 52,
 181	MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
 182	MLX4_DEV_CAP_FLAG_SENSE_SUPPORT	= 1LL << 55,
 183	MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
 184	MLX4_DEV_CAP_FLAG_64B_EQE	= 1LL << 61,
 185	MLX4_DEV_CAP_FLAG_64B_CQE	= 1LL << 62
 186};
 187
 188enum {
 189	MLX4_DEV_CAP_FLAG2_RSS			= 1LL <<  0,
 190	MLX4_DEV_CAP_FLAG2_RSS_TOP		= 1LL <<  1,
 191	MLX4_DEV_CAP_FLAG2_RSS_XOR		= 1LL <<  2,
 192	MLX4_DEV_CAP_FLAG2_FS_EN		= 1LL <<  3,
 193	MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN	= 1LL <<  4,
 194	MLX4_DEV_CAP_FLAG2_TS			= 1LL <<  5,
 195	MLX4_DEV_CAP_FLAG2_VLAN_CONTROL		= 1LL <<  6,
 196	MLX4_DEV_CAP_FLAG2_FSM			= 1LL <<  7,
 197	MLX4_DEV_CAP_FLAG2_UPDATE_QP		= 1LL <<  8,
 198	MLX4_DEV_CAP_FLAG2_DMFS_IPOIB		= 1LL <<  9,
 199	MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS	= 1LL <<  10,
 200	MLX4_DEV_CAP_FLAG2_MAD_DEMUX		= 1LL <<  11,
 201	MLX4_DEV_CAP_FLAG2_CQE_STRIDE		= 1LL <<  12,
 202	MLX4_DEV_CAP_FLAG2_EQE_STRIDE		= 1LL <<  13,
 203	MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL        = 1LL <<  14,
 204	MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP	= 1LL <<  15,
 205	MLX4_DEV_CAP_FLAG2_CONFIG_DEV		= 1LL <<  16,
 206	MLX4_DEV_CAP_FLAG2_SYS_EQS		= 1LL <<  17,
 207	MLX4_DEV_CAP_FLAG2_80_VFS		= 1LL <<  18,
 208	MLX4_DEV_CAP_FLAG2_FS_A0		= 1LL <<  19,
 209	MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
 210	MLX4_DEV_CAP_FLAG2_PORT_REMAP		= 1LL <<  21,
 211	MLX4_DEV_CAP_FLAG2_QCN			= 1LL <<  22,
 212	MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT	= 1LL <<  23,
 213	MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN         = 1LL <<  24,
 214	MLX4_DEV_CAP_FLAG2_QOS_VPP		= 1LL <<  25,
 215	MLX4_DEV_CAP_FLAG2_ETS_CFG		= 1LL <<  26,
 216	MLX4_DEV_CAP_FLAG2_PORT_BEACON		= 1LL <<  27,
 217	MLX4_DEV_CAP_FLAG2_IGNORE_FCS		= 1LL <<  28,
 218	MLX4_DEV_CAP_FLAG2_PHV_EN		= 1LL <<  29,
 219	MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN	= 1LL <<  30,
 220	MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31,
 221	MLX4_DEV_CAP_FLAG2_LB_SRC_CHK           = 1ULL << 32,
 222	MLX4_DEV_CAP_FLAG2_ROCE_V1_V2		= 1ULL <<  33,
 223	MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER   = 1ULL <<  34,
 224	MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT	= 1ULL <<  35,
 225	MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP          = 1ULL <<  36,
 226	MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT = 1ULL << 37,
 227	MLX4_DEV_CAP_FLAG2_USER_MAC_EN		= 1ULL << 38,
 228	MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW = 1ULL << 39,
 229	MLX4_DEV_CAP_FLAG2_SW_CQ_INIT           = 1ULL << 40,
 230};
 231
 232enum {
 233	MLX4_QUERY_FUNC_FLAGS_BF_RES_QP		= 1LL << 0,
 234	MLX4_QUERY_FUNC_FLAGS_A0_RES_QP		= 1LL << 1
 235};
 236
 237enum {
 238	MLX4_VF_CAP_FLAG_RESET			= 1 << 0
 239};
 240
 241/* bit enums for an 8-bit flags field indicating special use
 242 * QPs which require special handling in qp_reserve_range.
 243 * Currently, this only includes QPs used by the ETH interface,
 244 * where we expect to use blueflame.  These QPs must not have
 245 * bits 6 and 7 set in their qp number.
 246 *
 247 * This enum may use only bits 0..7.
 248 */
 249enum {
 250	MLX4_RESERVE_A0_QP	= 1 << 6,
 251	MLX4_RESERVE_ETH_BF_QP	= 1 << 7,
 252};
 253
 254enum {
 255	MLX4_DEV_CAP_64B_EQE_ENABLED	= 1LL << 0,
 256	MLX4_DEV_CAP_64B_CQE_ENABLED	= 1LL << 1,
 257	MLX4_DEV_CAP_CQE_STRIDE_ENABLED	= 1LL << 2,
 258	MLX4_DEV_CAP_EQE_STRIDE_ENABLED	= 1LL << 3
 259};
 260
 261enum {
 262	MLX4_FUNC_CAP_64B_EQE_CQE	= 1L << 0,
 263	MLX4_FUNC_CAP_EQE_CQE_STRIDE	= 1L << 1,
 264	MLX4_FUNC_CAP_DMFS_A0_STATIC	= 1L << 2
 265};
 266
 267
 268#define MLX4_ATTR_EXTENDED_PORT_INFO	cpu_to_be16(0xff90)
 269
 270enum {
 271	MLX4_BMME_FLAG_WIN_TYPE_2B	= 1 <<  1,
 272	MLX4_BMME_FLAG_LOCAL_INV	= 1 <<  6,
 273	MLX4_BMME_FLAG_REMOTE_INV	= 1 <<  7,
 274	MLX4_BMME_FLAG_TYPE_2_WIN	= 1 <<  9,
 275	MLX4_BMME_FLAG_RESERVED_LKEY	= 1 << 10,
 276	MLX4_BMME_FLAG_FAST_REG_WR	= 1 << 11,
 277	MLX4_BMME_FLAG_ROCE_V1_V2	= 1 << 19,
 278	MLX4_BMME_FLAG_PORT_REMAP	= 1 << 24,
 279	MLX4_BMME_FLAG_VSD_INIT2RTR	= 1 << 28,
 280};
 281
 282enum {
 283	MLX4_FLAG_PORT_REMAP		= MLX4_BMME_FLAG_PORT_REMAP,
 284	MLX4_FLAG_ROCE_V1_V2		= MLX4_BMME_FLAG_ROCE_V1_V2
 285};
 286
 287enum mlx4_event {
 288	MLX4_EVENT_TYPE_COMP		   = 0x00,
 289	MLX4_EVENT_TYPE_PATH_MIG	   = 0x01,
 290	MLX4_EVENT_TYPE_COMM_EST	   = 0x02,
 291	MLX4_EVENT_TYPE_SQ_DRAINED	   = 0x03,
 292	MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE	   = 0x13,
 293	MLX4_EVENT_TYPE_SRQ_LIMIT	   = 0x14,
 294	MLX4_EVENT_TYPE_CQ_ERROR	   = 0x04,
 295	MLX4_EVENT_TYPE_WQ_CATAS_ERROR	   = 0x05,
 296	MLX4_EVENT_TYPE_EEC_CATAS_ERROR	   = 0x06,
 297	MLX4_EVENT_TYPE_PATH_MIG_FAILED	   = 0x07,
 298	MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
 299	MLX4_EVENT_TYPE_WQ_ACCESS_ERROR	   = 0x11,
 300	MLX4_EVENT_TYPE_SRQ_CATAS_ERROR	   = 0x12,
 301	MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR  = 0x08,
 302	MLX4_EVENT_TYPE_PORT_CHANGE	   = 0x09,
 303	MLX4_EVENT_TYPE_EQ_OVERFLOW	   = 0x0f,
 304	MLX4_EVENT_TYPE_ECC_DETECT	   = 0x0e,
 305	MLX4_EVENT_TYPE_CMD		   = 0x0a,
 306	MLX4_EVENT_TYPE_VEP_UPDATE	   = 0x19,
 307	MLX4_EVENT_TYPE_COMM_CHANNEL	   = 0x18,
 308	MLX4_EVENT_TYPE_OP_REQUIRED	   = 0x1a,
 309	MLX4_EVENT_TYPE_FATAL_WARNING	   = 0x1b,
 310	MLX4_EVENT_TYPE_FLR_EVENT	   = 0x1c,
 311	MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
 312	MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT  = 0x3e,
 313	MLX4_EVENT_TYPE_NONE		   = 0xff,
 314};
 315
 316enum {
 317	MLX4_PORT_CHANGE_SUBTYPE_DOWN	= 1,
 318	MLX4_PORT_CHANGE_SUBTYPE_ACTIVE	= 4
 319};
 320
 321enum {
 322	MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE		= 1,
 323	MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE	= 2,
 324};
 325
 326enum {
 327	MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
 328};
 329
 330enum slave_port_state {
 331	SLAVE_PORT_DOWN = 0,
 332	SLAVE_PENDING_UP,
 333	SLAVE_PORT_UP,
 334};
 335
 336enum slave_port_gen_event {
 337	SLAVE_PORT_GEN_EVENT_DOWN = 0,
 338	SLAVE_PORT_GEN_EVENT_UP,
 339	SLAVE_PORT_GEN_EVENT_NONE,
 340};
 341
 342enum slave_port_state_event {
 343	MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
 344	MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
 345	MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
 346	MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
 347};
 348
 349enum {
 350	MLX4_PERM_LOCAL_READ	= 1 << 10,
 351	MLX4_PERM_LOCAL_WRITE	= 1 << 11,
 352	MLX4_PERM_REMOTE_READ	= 1 << 12,
 353	MLX4_PERM_REMOTE_WRITE	= 1 << 13,
 354	MLX4_PERM_ATOMIC	= 1 << 14,
 355	MLX4_PERM_BIND_MW	= 1 << 15,
 356	MLX4_PERM_MASK		= 0xFC00
 357};
 358
 359enum {
 360	MLX4_OPCODE_NOP			= 0x00,
 361	MLX4_OPCODE_SEND_INVAL		= 0x01,
 362	MLX4_OPCODE_RDMA_WRITE		= 0x08,
 363	MLX4_OPCODE_RDMA_WRITE_IMM	= 0x09,
 364	MLX4_OPCODE_SEND		= 0x0a,
 365	MLX4_OPCODE_SEND_IMM		= 0x0b,
 366	MLX4_OPCODE_LSO			= 0x0e,
 367	MLX4_OPCODE_RDMA_READ		= 0x10,
 368	MLX4_OPCODE_ATOMIC_CS		= 0x11,
 369	MLX4_OPCODE_ATOMIC_FA		= 0x12,
 370	MLX4_OPCODE_MASKED_ATOMIC_CS	= 0x14,
 371	MLX4_OPCODE_MASKED_ATOMIC_FA	= 0x15,
 372	MLX4_OPCODE_BIND_MW		= 0x18,
 373	MLX4_OPCODE_FMR			= 0x19,
 374	MLX4_OPCODE_LOCAL_INVAL		= 0x1b,
 375	MLX4_OPCODE_CONFIG_CMD		= 0x1f,
 376
 377	MLX4_RECV_OPCODE_RDMA_WRITE_IMM	= 0x00,
 378	MLX4_RECV_OPCODE_SEND		= 0x01,
 379	MLX4_RECV_OPCODE_SEND_IMM	= 0x02,
 380	MLX4_RECV_OPCODE_SEND_INVAL	= 0x03,
 381
 382	MLX4_CQE_OPCODE_ERROR		= 0x1e,
 383	MLX4_CQE_OPCODE_RESIZE		= 0x16,
 384};
 385
 386enum {
 387	MLX4_STAT_RATE_OFFSET	= 5
 388};
 389
 390enum mlx4_protocol {
 391	MLX4_PROT_IB_IPV6 = 0,
 392	MLX4_PROT_ETH,
 393	MLX4_PROT_IB_IPV4,
 394	MLX4_PROT_FCOE
 395};
 396
 397enum {
 398	MLX4_MTT_FLAG_PRESENT		= 1
 399};
 400
 401enum mlx4_qp_region {
 402	MLX4_QP_REGION_FW = 0,
 403	MLX4_QP_REGION_RSS_RAW_ETH,
 404	MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH,
 405	MLX4_QP_REGION_ETH_ADDR,
 406	MLX4_QP_REGION_FC_ADDR,
 407	MLX4_QP_REGION_FC_EXCH,
 408	MLX4_NUM_QP_REGION
 409};
 410
 411enum mlx4_port_type {
 412	MLX4_PORT_TYPE_NONE	= 0,
 413	MLX4_PORT_TYPE_IB	= 1,
 414	MLX4_PORT_TYPE_ETH	= 2,
 415	MLX4_PORT_TYPE_AUTO	= 3
 416};
 417
 418enum mlx4_special_vlan_idx {
 419	MLX4_NO_VLAN_IDX        = 0,
 420	MLX4_VLAN_MISS_IDX,
 421	MLX4_VLAN_REGULAR
 422};
 423
 424enum mlx4_steer_type {
 425	MLX4_MC_STEER = 0,
 426	MLX4_UC_STEER,
 427	MLX4_NUM_STEERS
 428};
 429
 430enum mlx4_resource_usage {
 431	MLX4_RES_USAGE_NONE,
 432	MLX4_RES_USAGE_DRIVER,
 433	MLX4_RES_USAGE_USER_VERBS,
 434};
 435
 436enum {
 437	MLX4_NUM_FEXCH          = 64 * 1024,
 438};
 439
 440enum {
 441	MLX4_MAX_FAST_REG_PAGES = 511,
 442};
 443
 444enum {
 445	/*
 446	 * Max wqe size for rdma read is 512 bytes, so this
 447	 * limits our max_sge_rd as the wqe needs to fit:
 448	 * - ctrl segment (16 bytes)
 449	 * - rdma segment (16 bytes)
 450	 * - scatter elements (16 bytes each)
 451	 */
 452	MLX4_MAX_SGE_RD	= (512 - 16 - 16) / 16
 453};
 454
 455enum {
 456	MLX4_DEV_PMC_SUBTYPE_GUID_INFO	 = 0x14,
 457	MLX4_DEV_PMC_SUBTYPE_PORT_INFO	 = 0x15,
 458	MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE	 = 0x16,
 459	MLX4_DEV_PMC_SUBTYPE_SL_TO_VL_MAP = 0x17,
 460};
 461
 462/* Port mgmt change event handling */
 463enum {
 464	MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK	= 1 << 0,
 465	MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK		= 1 << 1,
 466	MLX4_EQ_PORT_INFO_LID_CHANGE_MASK		= 1 << 2,
 467	MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK		= 1 << 3,
 468	MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK	= 1 << 4,
 469};
 470
 471union sl2vl_tbl_to_u64 {
 472	u8	sl8[8];
 473	u64	sl64;
 474};
 475
 476enum {
 477	MLX4_DEVICE_STATE_UP			= 1 << 0,
 478	MLX4_DEVICE_STATE_INTERNAL_ERROR	= 1 << 1,
 479};
 480
 481enum {
 482	MLX4_INTERFACE_STATE_UP		= 1 << 0,
 483	MLX4_INTERFACE_STATE_DELETION	= 1 << 1,
 484	MLX4_INTERFACE_STATE_NOWAIT	= 1 << 2,
 485};
 486
 487#define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
 488			     MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
 489
 490enum mlx4_module_id {
 491	MLX4_MODULE_ID_SFP              = 0x3,
 492	MLX4_MODULE_ID_QSFP             = 0xC,
 493	MLX4_MODULE_ID_QSFP_PLUS        = 0xD,
 494	MLX4_MODULE_ID_QSFP28           = 0x11,
 495};
 496
 497enum { /* rl */
 498	MLX4_QP_RATE_LIMIT_NONE		= 0,
 499	MLX4_QP_RATE_LIMIT_KBS		= 1,
 500	MLX4_QP_RATE_LIMIT_MBS		= 2,
 501	MLX4_QP_RATE_LIMIT_GBS		= 3
 502};
 503
 504struct mlx4_rate_limit_caps {
 505	u16	num_rates; /* Number of different rates */
 506	u8	min_unit;
 507	u16	min_val;
 508	u8	max_unit;
 509	u16	max_val;
 510};
 511
 512static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
 513{
 514	return (major << 32) | (minor << 16) | subminor;
 515}
 516
 517struct mlx4_phys_caps {
 518	u32			gid_phys_table_len[MLX4_MAX_PORTS + 1];
 519	u32			pkey_phys_table_len[MLX4_MAX_PORTS + 1];
 520	u32			num_phys_eqs;
 521	u32			base_sqpn;
 522	u32			base_proxy_sqpn;
 523	u32			base_tunnel_sqpn;
 524};
 525
 526struct mlx4_spec_qps {
 527	u32 qp0_qkey;
 528	u32 qp0_proxy;
 529	u32 qp0_tunnel;
 530	u32 qp1_proxy;
 531	u32 qp1_tunnel;
 532};
 533
 534struct mlx4_caps {
 535	u64			fw_ver;
 536	u32			function;
 537	int			num_ports;
 538	int			vl_cap[MLX4_MAX_PORTS + 1];
 539	int			ib_mtu_cap[MLX4_MAX_PORTS + 1];
 540	__be32			ib_port_def_cap[MLX4_MAX_PORTS + 1];
 541	u64			def_mac[MLX4_MAX_PORTS + 1];
 542	int			eth_mtu_cap[MLX4_MAX_PORTS + 1];
 543	int			gid_table_len[MLX4_MAX_PORTS + 1];
 544	int			pkey_table_len[MLX4_MAX_PORTS + 1];
 545	int			trans_type[MLX4_MAX_PORTS + 1];
 546	int			vendor_oui[MLX4_MAX_PORTS + 1];
 547	int			wavelength[MLX4_MAX_PORTS + 1];
 548	u64			trans_code[MLX4_MAX_PORTS + 1];
 549	int			local_ca_ack_delay;
 550	int			num_uars;
 551	u32			uar_page_size;
 552	int			bf_reg_size;
 553	int			bf_regs_per_page;
 554	int			max_sq_sg;
 555	int			max_rq_sg;
 556	int			num_qps;
 557	int			max_wqes;
 558	int			max_sq_desc_sz;
 559	int			max_rq_desc_sz;
 560	int			max_qp_init_rdma;
 561	int			max_qp_dest_rdma;
 562	int			max_tc_eth;
 563	struct mlx4_spec_qps   *spec_qps;
 564	int			num_srqs;
 565	int			max_srq_wqes;
 566	int			max_srq_sge;
 567	int			reserved_srqs;
 568	int			num_cqs;
 569	int			max_cqes;
 570	int			reserved_cqs;
 571	int			num_sys_eqs;
 572	int			num_eqs;
 573	int			reserved_eqs;
 574	int			num_comp_vectors;
 575	int			num_mpts;
 576	int			num_mtts;
 577	int			fmr_reserved_mtts;
 578	int			reserved_mtts;
 579	int			reserved_mrws;
 580	int			reserved_uars;
 581	int			num_mgms;
 582	int			num_amgms;
 583	int			reserved_mcgs;
 584	int			num_qp_per_mgm;
 585	int			steering_mode;
 586	int			dmfs_high_steer_mode;
 587	int			fs_log_max_ucast_qp_range_size;
 588	int			num_pds;
 589	int			reserved_pds;
 590	int			max_xrcds;
 591	int			reserved_xrcds;
 592	int			mtt_entry_sz;
 593	u32			max_msg_sz;
 594	u32			page_size_cap;
 595	u64			flags;
 596	u64			flags2;
 597	u32			bmme_flags;
 598	u32			reserved_lkey;
 599	u16			stat_rate_support;
 600	u8			port_width_cap[MLX4_MAX_PORTS + 1];
 601	int			max_gso_sz;
 602	int			max_rss_tbl_sz;
 603	int                     reserved_qps_cnt[MLX4_NUM_QP_REGION];
 604	int			reserved_qps;
 605	int                     reserved_qps_base[MLX4_NUM_QP_REGION];
 606	int                     log_num_macs;
 607	int                     log_num_vlans;
 608	enum mlx4_port_type	port_type[MLX4_MAX_PORTS + 1];
 609	u8			supported_type[MLX4_MAX_PORTS + 1];
 610	u8                      suggested_type[MLX4_MAX_PORTS + 1];
 611	u8                      default_sense[MLX4_MAX_PORTS + 1];
 612	u32			port_mask[MLX4_MAX_PORTS + 1];
 613	enum mlx4_port_type	possible_type[MLX4_MAX_PORTS + 1];
 614	u32			max_counters;
 615	u8			port_ib_mtu[MLX4_MAX_PORTS + 1];
 616	u16			sqp_demux;
 617	u32			eqe_size;
 618	u32			cqe_size;
 619	u8			eqe_factor;
 620	u32			userspace_caps; /* userspace must be aware of these */
 621	u32			function_caps;  /* VFs must be aware of these */
 622	u16			hca_core_clock;
 623	u64			phys_port_id[MLX4_MAX_PORTS + 1];
 624	int			tunnel_offload_mode;
 625	u8			rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
 626	u8			phv_bit[MLX4_MAX_PORTS + 1];
 627	u8			alloc_res_qp_mask;
 628	u32			dmfs_high_rate_qpn_base;
 629	u32			dmfs_high_rate_qpn_range;
 630	u32			vf_caps;
 631	bool			wol_port[MLX4_MAX_PORTS + 1];
 632	struct mlx4_rate_limit_caps rl_caps;
 633	u32			health_buffer_addrs;
 634	bool			map_clock_to_user;
 635};
 636
 637struct mlx4_buf_list {
 638	void		       *buf;
 639	dma_addr_t		map;
 640};
 641
 642struct mlx4_buf {
 643	struct mlx4_buf_list	direct;
 644	struct mlx4_buf_list   *page_list;
 645	int			nbufs;
 646	int			npages;
 647	int			page_shift;
 648};
 649
 650struct mlx4_mtt {
 651	u32			offset;
 652	int			order;
 653	int			page_shift;
 654};
 655
 656enum {
 657	MLX4_DB_PER_PAGE = PAGE_SIZE / 4
 658};
 659
 660struct mlx4_db_pgdir {
 661	struct list_head	list;
 662	DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
 663	DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
 664	unsigned long	       *bits[2];
 665	__be32		       *db_page;
 666	dma_addr_t		db_dma;
 667};
 668
 669struct mlx4_ib_user_db_page;
 670
 671struct mlx4_db {
 672	__be32			*db;
 673	union {
 674		struct mlx4_db_pgdir		*pgdir;
 675		struct mlx4_ib_user_db_page	*user_page;
 676	}			u;
 677	dma_addr_t		dma;
 678	int			index;
 679	int			order;
 680};
 681
 682struct mlx4_hwq_resources {
 683	struct mlx4_db		db;
 684	struct mlx4_mtt		mtt;
 685	struct mlx4_buf		buf;
 686};
 687
 688struct mlx4_mr {
 689	struct mlx4_mtt		mtt;
 690	u64			iova;
 691	u64			size;
 692	u32			key;
 693	u32			pd;
 694	u32			access;
 695	int			enabled;
 696};
 697
 698enum mlx4_mw_type {
 699	MLX4_MW_TYPE_1 = 1,
 700	MLX4_MW_TYPE_2 = 2,
 701};
 702
 703struct mlx4_mw {
 704	u32			key;
 705	u32			pd;
 706	enum mlx4_mw_type	type;
 707	int			enabled;
 708};
 709
 710struct mlx4_uar {
 711	unsigned long		pfn;
 712	int			index;
 713	struct list_head	bf_list;
 714	unsigned		free_bf_bmap;
 715	void __iomem	       *map;
 716	void __iomem	       *bf_map;
 717};
 718
 719struct mlx4_bf {
 720	unsigned int		offset;
 721	int			buf_size;
 722	struct mlx4_uar	       *uar;
 723	void __iomem	       *reg;
 724};
 725
 726struct mlx4_cq {
 727	void (*comp)		(struct mlx4_cq *);
 728	void (*event)		(struct mlx4_cq *, enum mlx4_event);
 729
 730	struct mlx4_uar	       *uar;
 731
 732	u32			cons_index;
 733
 734	u16                     irq;
 735	__be32		       *set_ci_db;
 736	__be32		       *arm_db;
 737	int			arm_sn;
 738
 739	int			cqn;
 740	unsigned		vector;
 741
 742	refcount_t		refcount;
 743	struct completion	free;
 744	struct {
 745		struct list_head list;
 746		void (*comp)(struct mlx4_cq *);
 747		void		*priv;
 748	} tasklet_ctx;
 749	int		reset_notify_added;
 750	struct list_head	reset_notify;
 751	u8			usage;
 752};
 753
 754struct mlx4_qp {
 755	void (*event)		(struct mlx4_qp *, enum mlx4_event);
 756
 757	int			qpn;
 758
 759	refcount_t		refcount;
 760	struct completion	free;
 761	u8			usage;
 762};
 763
 764struct mlx4_srq {
 765	void (*event)		(struct mlx4_srq *, enum mlx4_event);
 766
 767	int			srqn;
 768	int			max;
 769	int			max_gs;
 770	int			wqe_shift;
 771
 772	refcount_t		refcount;
 773	struct completion	free;
 774};
 775
 776struct mlx4_av {
 777	__be32			port_pd;
 778	u8			reserved1;
 779	u8			g_slid;
 780	__be16			dlid;
 781	u8			reserved2;
 782	u8			gid_index;
 783	u8			stat_rate;
 784	u8			hop_limit;
 785	__be32			sl_tclass_flowlabel;
 786	u8			dgid[16];
 787};
 788
 789struct mlx4_eth_av {
 790	__be32		port_pd;
 791	u8		reserved1;
 792	u8		smac_idx;
 793	u16		reserved2;
 794	u8		reserved3;
 795	u8		gid_index;
 796	u8		stat_rate;
 797	u8		hop_limit;
 798	__be32		sl_tclass_flowlabel;
 799	u8		dgid[16];
 800	u8		s_mac[6];
 801	u8		reserved4[2];
 802	__be16		vlan;
 803	u8		mac[ETH_ALEN];
 804};
 805
 806union mlx4_ext_av {
 807	struct mlx4_av		ib;
 808	struct mlx4_eth_av	eth;
 809};
 810
 811/* Counters should be saturate once they reach their maximum value */
 812#define ASSIGN_32BIT_COUNTER(counter, value) do {	\
 813	if ((value) > U32_MAX)				\
 814		counter = cpu_to_be32(U32_MAX);		\
 815	else						\
 816		counter = cpu_to_be32(value);		\
 817} while (0)
 818
 819struct mlx4_counter {
 820	u8	reserved1[3];
 821	u8	counter_mode;
 822	__be32	num_ifc;
 823	u32	reserved2[2];
 824	__be64	rx_frames;
 825	__be64	rx_bytes;
 826	__be64	tx_frames;
 827	__be64	tx_bytes;
 828};
 829
 830struct mlx4_quotas {
 831	int qp;
 832	int cq;
 833	int srq;
 834	int mpt;
 835	int mtt;
 836	int counter;
 837	int xrcd;
 838};
 839
 840struct mlx4_vf_dev {
 841	u8			min_port;
 842	u8			n_ports;
 843};
 844
 845struct mlx4_fw_crdump {
 846	bool snapshot_enable;
 847	struct devlink_region *region_crspace;
 848	struct devlink_region *region_fw_health;
 849};
 850
 851enum mlx4_pci_status {
 852	MLX4_PCI_STATUS_DISABLED,
 853	MLX4_PCI_STATUS_ENABLED,
 854};
 855
 856struct mlx4_dev_persistent {
 857	struct pci_dev	       *pdev;
 858	struct mlx4_dev	       *dev;
 859	int                     nvfs[MLX4_MAX_PORTS + 1];
 860	int			num_vfs;
 861	enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
 862	enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
 863	struct work_struct      catas_work;
 864	struct workqueue_struct *catas_wq;
 865	struct mutex	device_state_mutex; /* protect HW state */
 866	u8		state;
 867	struct mutex	interface_state_mutex; /* protect SW state */
 868	u8	interface_state;
 869	struct mutex		pci_status_mutex; /* sync pci state */
 870	enum mlx4_pci_status	pci_status;
 871	struct mlx4_fw_crdump	crdump;
 872};
 873
 874struct mlx4_dev {
 875	struct mlx4_dev_persistent *persist;
 876	unsigned long		flags;
 877	unsigned long		num_slaves;
 878	struct mlx4_caps	caps;
 879	struct mlx4_phys_caps	phys_caps;
 880	struct mlx4_quotas	quotas;
 881	struct radix_tree_root	qp_table_tree;
 882	u8			rev_id;
 883	u8			port_random_macs;
 884	char			board_id[MLX4_BOARD_ID_LEN];
 885	int			numa_node;
 886	int			oper_log_mgm_entry_size;
 887	u64			regid_promisc_array[MLX4_MAX_PORTS + 1];
 888	u64			regid_allmulti_array[MLX4_MAX_PORTS + 1];
 889	struct mlx4_vf_dev     *dev_vfs;
 890	u8  uar_page_shift;
 891};
 892
 893struct mlx4_adev {
 894	struct auxiliary_device adev;
 895	struct mlx4_dev *mdev;
 896	int idx;
 897};
 898
 899struct mlx4_clock_params {
 900	u64 offset;
 901	u8 bar;
 902	u8 size;
 903};
 904
 905struct mlx4_eqe {
 906	u8			reserved1;
 907	u8			type;
 908	u8			reserved2;
 909	u8			subtype;
 910	union {
 911		u32		raw[6];
 912		struct {
 913			__be32	cqn;
 914		} __packed comp;
 915		struct {
 916			u16	reserved1;
 917			__be16	token;
 918			u32	reserved2;
 919			u8	reserved3[3];
 920			u8	status;
 921			__be64	out_param;
 922		} __packed cmd;
 923		struct {
 924			__be32	qpn;
 925		} __packed qp;
 926		struct {
 927			__be32	srqn;
 928		} __packed srq;
 929		struct {
 930			__be32	cqn;
 931			u32	reserved1;
 932			u8	reserved2[3];
 933			u8	syndrome;
 934		} __packed cq_err;
 935		struct {
 936			u32	reserved1[2];
 937			__be32	port;
 938		} __packed port_change;
 939		struct {
 940			#define COMM_CHANNEL_BIT_ARRAY_SIZE	4
 941			u32 reserved;
 942			u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
 943		} __packed comm_channel_arm;
 944		struct {
 945			u8	port;
 946			u8	reserved[3];
 947			__be64	mac;
 948		} __packed mac_update;
 949		struct {
 950			__be32	slave_id;
 951		} __packed flr_event;
 952		struct {
 953			__be16  current_temperature;
 954			__be16  warning_threshold;
 955		} __packed warming;
 956		struct {
 957			u8 reserved[3];
 958			u8 port;
 959			union {
 960				struct {
 961					__be16 mstr_sm_lid;
 962					__be16 port_lid;
 963					__be32 changed_attr;
 964					u8 reserved[3];
 965					u8 mstr_sm_sl;
 966					__be64 gid_prefix;
 967				} __packed port_info;
 968				struct {
 969					__be32 block_ptr;
 970					__be32 tbl_entries_mask;
 971				} __packed tbl_change_info;
 972				struct {
 973					u8 sl2vl_table[8];
 974				} __packed sl2vl_tbl_change_info;
 975			} params;
 976		} __packed port_mgmt_change;
 977		struct {
 978			u8 reserved[3];
 979			u8 port;
 980			u32 reserved1[5];
 981		} __packed bad_cable;
 982	}			event;
 983	u8			slave_id;
 984	u8			reserved3[2];
 985	u8			owner;
 986} __packed;
 987
 988struct mlx4_init_port_param {
 989	int			set_guid0;
 990	int			set_node_guid;
 991	int			set_si_guid;
 992	u16			mtu;
 993	int			port_width_cap;
 994	u16			vl_cap;
 995	u16			max_gid;
 996	u16			max_pkey;
 997	u64			guid0;
 998	u64			node_guid;
 999	u64			si_guid;
1000};
1001
1002#define MAD_IFC_DATA_SZ 192
1003/* MAD IFC Mailbox */
1004struct mlx4_mad_ifc {
1005	u8	base_version;
1006	u8	mgmt_class;
1007	u8	class_version;
1008	u8	method;
1009	__be16	status;
1010	__be16	class_specific;
1011	__be64	tid;
1012	__be16	attr_id;
1013	__be16	resv;
1014	__be32	attr_mod;
1015	__be64	mkey;
1016	__be16	dr_slid;
1017	__be16	dr_dlid;
1018	u8	reserved[28];
1019	u8	data[MAD_IFC_DATA_SZ];
1020} __packed;
1021
1022#define mlx4_foreach_port(port, dev, type)				\
1023	for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++)	\
1024		if ((type) == (dev)->caps.port_mask[(port)])
1025
1026#define mlx4_foreach_ib_transport_port(port, dev)                         \
1027	for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++)       \
1028		if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
1029		    ((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_ETH))
1030
1031#define MLX4_INVALID_SLAVE_ID	0xFF
1032#define MLX4_SINK_COUNTER_INDEX(dev)	(dev->caps.max_counters - 1)
1033
1034void handle_port_mgmt_change_event(struct work_struct *work);
1035
1036static inline int mlx4_master_func_num(struct mlx4_dev *dev)
1037{
1038	return dev->caps.function;
1039}
1040
1041static inline int mlx4_is_master(struct mlx4_dev *dev)
1042{
1043	return dev->flags & MLX4_FLAG_MASTER;
1044}
1045
1046static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
1047{
1048	return dev->phys_caps.base_sqpn + 8 +
1049		16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
1050}
1051
1052static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
1053{
1054	return (qpn < dev->phys_caps.base_sqpn + 8 +
1055		16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) &&
1056		qpn >= dev->phys_caps.base_sqpn) ||
1057	       (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]);
1058}
1059
1060static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
1061{
1062	int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
1063
1064	if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
1065		return 1;
1066
1067	return 0;
1068}
1069
1070static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
1071{
1072	return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
1073}
1074
1075static inline int mlx4_is_slave(struct mlx4_dev *dev)
1076{
1077	return dev->flags & MLX4_FLAG_SLAVE;
1078}
1079
1080static inline int mlx4_is_eth(struct mlx4_dev *dev, int port)
1081{
1082	return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1;
1083}
1084
1085int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
1086		   struct mlx4_buf *buf);
1087void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
1088static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
1089{
1090	if (buf->nbufs == 1)
1091		return buf->direct.buf + offset;
1092	else
1093		return buf->page_list[offset >> PAGE_SHIFT].buf +
1094			(offset & (PAGE_SIZE - 1));
1095}
1096
1097static inline int mlx4_is_bonded(struct mlx4_dev *dev)
1098{
1099	return !!(dev->flags & MLX4_FLAG_BONDED);
1100}
1101
1102static inline int mlx4_is_mf_bonded(struct mlx4_dev *dev)
1103{
1104	return (mlx4_is_bonded(dev) && mlx4_is_mfunc(dev));
1105}
1106
1107int mlx4_queue_bond_work(struct mlx4_dev *dev, int is_bonded, u8 v2p_p1,
1108			 u8 v2p_p2);
1109
1110int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
1111void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
1112int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1113void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1114
1115int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
1116void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
1117int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
1118void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
1119
1120int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
1121		  struct mlx4_mtt *mtt);
1122void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1123u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1124
1125int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
1126		  int npages, int page_shift, struct mlx4_mr *mr);
1127int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
1128int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
1129int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
1130		  struct mlx4_mw *mw);
1131void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
1132int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
1133int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1134		   int start_index, int npages, u64 *page_list);
1135int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1136		       struct mlx4_buf *buf);
1137
1138int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, unsigned int order);
1139void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
1140
1141int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
1142		       int size);
1143void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
1144		       int size);
1145
1146int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
1147		  struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
1148		  unsigned int vector, int collapsed, int timestamp_en,
1149		  void *buf_addr, bool user_cq);
1150void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
1151int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1152			  int *base, u8 flags, u8 usage);
1153void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1154
1155int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
1156void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
1157
1158int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
1159		   struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
1160void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
1161int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
1162int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
1163
1164int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
1165int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
1166
1167int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1168			int block_mcast_loopback, enum mlx4_protocol prot);
1169int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1170			enum mlx4_protocol prot);
1171int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1172			  u8 port, int block_mcast_loopback,
1173			  enum mlx4_protocol protocol, u64 *reg_id);
1174int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1175			  enum mlx4_protocol protocol, u64 reg_id);
1176
1177enum {
1178	MLX4_DOMAIN_UVERBS	= 0x1000,
1179	MLX4_DOMAIN_ETHTOOL     = 0x2000,
1180	MLX4_DOMAIN_RFS         = 0x3000,
1181	MLX4_DOMAIN_NIC    = 0x5000,
1182};
1183
1184enum mlx4_net_trans_rule_id {
1185	MLX4_NET_TRANS_RULE_ID_ETH = 0,
1186	MLX4_NET_TRANS_RULE_ID_IB,
1187	MLX4_NET_TRANS_RULE_ID_IPV6,
1188	MLX4_NET_TRANS_RULE_ID_IPV4,
1189	MLX4_NET_TRANS_RULE_ID_TCP,
1190	MLX4_NET_TRANS_RULE_ID_UDP,
1191	MLX4_NET_TRANS_RULE_ID_VXLAN,
1192	MLX4_NET_TRANS_RULE_NUM, /* should be last */
1193};
1194
1195extern const u16 __sw_id_hw[];
1196
1197static inline int map_hw_to_sw_id(u16 header_id)
1198{
1199
1200	int i;
1201	for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
1202		if (header_id == __sw_id_hw[i])
1203			return i;
1204	}
1205	return -EINVAL;
1206}
1207
1208enum mlx4_net_trans_promisc_mode {
1209	MLX4_FS_REGULAR = 1,
1210	MLX4_FS_ALL_DEFAULT,
1211	MLX4_FS_MC_DEFAULT,
1212	MLX4_FS_MIRROR_RX_PORT,
1213	MLX4_FS_MIRROR_SX_PORT,
1214	MLX4_FS_UC_SNIFFER,
1215	MLX4_FS_MC_SNIFFER,
1216	MLX4_FS_MODE_NUM, /* should be last */
1217};
1218
1219struct mlx4_spec_eth {
1220	u8	dst_mac[ETH_ALEN];
1221	u8	dst_mac_msk[ETH_ALEN];
1222	u8	src_mac[ETH_ALEN];
1223	u8	src_mac_msk[ETH_ALEN];
1224	u8	ether_type_enable;
1225	__be16	ether_type;
1226	__be16	vlan_id_msk;
1227	__be16	vlan_id;
1228};
1229
1230struct mlx4_spec_tcp_udp {
1231	__be16 dst_port;
1232	__be16 dst_port_msk;
1233	__be16 src_port;
1234	__be16 src_port_msk;
1235};
1236
1237struct mlx4_spec_ipv4 {
1238	__be32 dst_ip;
1239	__be32 dst_ip_msk;
1240	__be32 src_ip;
1241	__be32 src_ip_msk;
1242};
1243
1244struct mlx4_spec_ib {
1245	__be32  l3_qpn;
1246	__be32	qpn_msk;
1247	u8	dst_gid[16];
1248	u8	dst_gid_msk[16];
1249};
1250
1251struct mlx4_spec_vxlan {
1252	__be32 vni;
1253	__be32 vni_mask;
1254
1255};
1256
1257struct mlx4_spec_list {
1258	struct	list_head list;
1259	enum	mlx4_net_trans_rule_id id;
1260	union {
1261		struct mlx4_spec_eth eth;
1262		struct mlx4_spec_ib ib;
1263		struct mlx4_spec_ipv4 ipv4;
1264		struct mlx4_spec_tcp_udp tcp_udp;
1265		struct mlx4_spec_vxlan vxlan;
1266	};
1267};
1268
1269enum mlx4_net_trans_hw_rule_queue {
1270	MLX4_NET_TRANS_Q_FIFO,
1271	MLX4_NET_TRANS_Q_LIFO,
1272};
1273
1274struct mlx4_net_trans_rule {
1275	struct	list_head list;
1276	enum	mlx4_net_trans_hw_rule_queue queue_mode;
1277	bool	exclusive;
1278	bool	allow_loopback;
1279	enum	mlx4_net_trans_promisc_mode promisc_mode;
1280	u8	port;
1281	u16	priority;
1282	u32	qpn;
1283};
1284
1285struct mlx4_net_trans_rule_hw_ctrl {
1286	__be16 prio;
1287	u8 type;
1288	u8 flags;
1289	u8 rsvd1;
1290	u8 funcid;
1291	u8 vep;
1292	u8 port;
1293	__be32 qpn;
1294	__be32 rsvd2;
1295};
1296
1297struct mlx4_net_trans_rule_hw_ib {
1298	u8 size;
1299	u8 rsvd1;
1300	__be16 id;
1301	u32 rsvd2;
1302	__be32 l3_qpn;
1303	__be32 qpn_mask;
1304	u8 dst_gid[16];
1305	u8 dst_gid_msk[16];
1306} __packed;
1307
1308struct mlx4_net_trans_rule_hw_eth {
1309	u8	size;
1310	u8	rsvd;
1311	__be16	id;
1312	u8	rsvd1[6];
1313	u8	dst_mac[6];
1314	u16	rsvd2;
1315	u8	dst_mac_msk[6];
1316	u16	rsvd3;
1317	u8	src_mac[6];
1318	u16	rsvd4;
1319	u8	src_mac_msk[6];
1320	u8      rsvd5;
1321	u8      ether_type_enable;
1322	__be16  ether_type;
1323	__be16  vlan_tag_msk;
1324	__be16  vlan_tag;
1325} __packed;
1326
1327struct mlx4_net_trans_rule_hw_tcp_udp {
1328	u8	size;
1329	u8	rsvd;
1330	__be16	id;
1331	__be16	rsvd1[3];
1332	__be16	dst_port;
1333	__be16	rsvd2;
1334	__be16	dst_port_msk;
1335	__be16	rsvd3;
1336	__be16	src_port;
1337	__be16	rsvd4;
1338	__be16	src_port_msk;
1339} __packed;
1340
1341struct mlx4_net_trans_rule_hw_ipv4 {
1342	u8	size;
1343	u8	rsvd;
1344	__be16	id;
1345	__be32	rsvd1;
1346	__be32	dst_ip;
1347	__be32	dst_ip_msk;
1348	__be32	src_ip;
1349	__be32	src_ip_msk;
1350} __packed;
1351
1352struct mlx4_net_trans_rule_hw_vxlan {
1353	u8	size;
1354	u8	rsvd;
1355	__be16	id;
1356	__be32	rsvd1;
1357	__be32	vni;
1358	__be32	vni_mask;
1359} __packed;
1360
1361struct _rule_hw {
1362	union {
1363		struct {
1364			u8 size;
1365			u8 rsvd;
1366			__be16 id;
1367		};
1368		struct mlx4_net_trans_rule_hw_eth eth;
1369		struct mlx4_net_trans_rule_hw_ib ib;
1370		struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1371		struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1372		struct mlx4_net_trans_rule_hw_vxlan vxlan;
1373	};
1374};
1375
1376enum {
1377	VXLAN_STEER_BY_OUTER_MAC	= 1 << 0,
1378	VXLAN_STEER_BY_OUTER_VLAN	= 1 << 1,
1379	VXLAN_STEER_BY_VSID_VNI		= 1 << 2,
1380	VXLAN_STEER_BY_INNER_MAC	= 1 << 3,
1381	VXLAN_STEER_BY_INNER_VLAN	= 1 << 4,
1382};
1383
1384enum {
1385	MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS = 0x2,
1386};
1387
1388int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1389				enum mlx4_net_trans_promisc_mode mode);
1390int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1391				   enum mlx4_net_trans_promisc_mode mode);
1392int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1393int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1394int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1395int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1396int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1397
1398int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1399void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1400int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1401int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1402int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1403			  u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1404int mlx4_SET_PORT_user_mac(struct mlx4_dev *dev, u8 port, u8 *user_mac);
1405int mlx4_SET_PORT_user_mtu(struct mlx4_dev *dev, u8 port, u16 user_mtu);
1406int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1407			   u8 promisc);
1408int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time);
1409int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port,
1410			    u8 ignore_fcs_value);
1411int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1412int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val);
1413int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv);
1414int mlx4_get_is_vlan_offload_disabled(struct mlx4_dev *dev, u8 port,
1415				      bool *vlan_offload_disabled);
1416void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl,
1417				       struct _rule_hw *eth_header);
1418int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1419int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1420void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1421
1422int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1423int mlx4_test_interrupt(struct mlx4_dev *dev, int vector);
1424int mlx4_test_async(struct mlx4_dev *dev);
1425int mlx4_query_diag_counters(struct mlx4_dev *dev, u8 op_modifier,
1426			     const u32 offset[], u32 value[],
1427			     size_t array_len, u8 port);
1428u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port);
1429bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector);
1430struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port);
1431int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector);
1432void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1433
1434int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector);
1435int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
1436
1437int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1438int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1439int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1440
1441int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage);
1442void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1443int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port);
1444
1445void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry,
1446			 int port);
1447__be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port);
1448void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port);
1449int mlx4_flow_attach(struct mlx4_dev *dev,
1450		     struct mlx4_net_trans_rule *rule, u64 *reg_id);
1451int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1452int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1453				    enum mlx4_net_trans_promisc_mode flow_type);
1454int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1455				  enum mlx4_net_trans_rule_id id);
1456int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1457
1458int mlx4_tunnel_steer_add(struct mlx4_dev *dev, const unsigned char *addr,
1459			  int port, int qpn, u16 prio, u64 *reg_id);
1460
1461void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1462			  int i, int val);
1463
1464int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1465
1466int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1467int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1468int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1469int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1470int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1471enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1472int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1473
1474void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1475__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1476
1477int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1478				 int *slave_id);
1479int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1480				 u8 *gid);
1481
1482int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1483				      u32 max_range_qpn);
1484
1485u64 mlx4_read_clock(struct mlx4_dev *dev);
1486
1487struct mlx4_active_ports {
1488	DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1489};
1490/* Returns a bitmap of the physical ports which are assigned to slave */
1491struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1492
1493/* Returns the physical port that represents the virtual port of the slave, */
1494/* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1495/* mapping is returned.							    */
1496int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1497
1498struct mlx4_slaves_pport {
1499	DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1500};
1501/* Returns a bitmap of all slaves that are assigned to port. */
1502struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1503						   int port);
1504
1505/* Returns a bitmap of all slaves that are assigned exactly to all the */
1506/* the ports that are set in crit_ports.			       */
1507struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1508		struct mlx4_dev *dev,
1509		const struct mlx4_active_ports *crit_ports);
1510
1511/* Returns the slave's virtual port that represents the physical port. */
1512int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1513
1514int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1515
1516int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1517int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis);
1518int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port);
1519int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2);
1520int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1521int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1522int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
1523				 int enable);
1524
1525struct mlx4_mpt_entry;
1526int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1527		       struct mlx4_mpt_entry ***mpt_entry);
1528int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1529			 struct mlx4_mpt_entry **mpt_entry);
1530int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
1531			 u32 pdn);
1532int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
1533			     struct mlx4_mpt_entry *mpt_entry,
1534			     u32 access);
1535void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
1536			struct mlx4_mpt_entry **mpt_entry);
1537void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
1538int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
1539			    u64 iova, u64 size, int npages,
1540			    int page_shift, struct mlx4_mpt_entry *mpt_entry);
1541
1542int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
1543			 u16 offset, u16 size, u8 *data);
1544int mlx4_max_tc(struct mlx4_dev *dev);
1545
1546/* Returns true if running in low memory profile (kdump kernel) */
1547static inline bool mlx4_low_memory_profile(void)
1548{
1549	return is_kdump_kernel();
1550}
1551
1552/* ACCESS REG commands */
1553enum mlx4_access_reg_method {
1554	MLX4_ACCESS_REG_QUERY = 0x1,
1555	MLX4_ACCESS_REG_WRITE = 0x2,
1556};
1557
1558/* ACCESS PTYS Reg command */
1559enum mlx4_ptys_proto {
1560	MLX4_PTYS_IB = 1<<0,
1561	MLX4_PTYS_EN = 1<<2,
1562};
1563
1564enum mlx4_ptys_flags {
1565	MLX4_PTYS_AN_DISABLE_CAP   = 1 << 5,
1566	MLX4_PTYS_AN_DISABLE_ADMIN = 1 << 6,
1567};
1568
1569struct mlx4_ptys_reg {
1570	u8 flags;
1571	u8 local_port;
1572	u8 resrvd2;
1573	u8 proto_mask;
1574	__be32 resrvd3[2];
1575	__be32 eth_proto_cap;
1576	__be16 ib_width_cap;
1577	__be16 ib_speed_cap;
1578	__be32 resrvd4;
1579	__be32 eth_proto_admin;
1580	__be16 ib_width_admin;
1581	__be16 ib_speed_admin;
1582	__be32 resrvd5;
1583	__be32 eth_proto_oper;
1584	__be16 ib_width_oper;
1585	__be16 ib_speed_oper;
1586	__be32 resrvd6;
1587	__be32 eth_proto_lp_adv;
1588} __packed;
1589
1590int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
1591			 enum mlx4_access_reg_method method,
1592			 struct mlx4_ptys_reg *ptys_reg);
1593
1594int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1595				   struct mlx4_clock_params *params);
1596
1597static inline int mlx4_to_hw_uar_index(struct mlx4_dev *dev, int index)
1598{
1599	return (index << (PAGE_SHIFT - dev->uar_page_shift));
1600}
1601
1602static inline int mlx4_get_num_reserved_uar(struct mlx4_dev *dev)
1603{
1604	/* The first 128 UARs are used for EQ doorbells */
1605	return (128 >> (PAGE_SHIFT - dev->uar_page_shift));
1606}
1607#endif /* MLX4_DEVICE_H */