twl.h

  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 * twl4030.h - header for TWL4030 PM and audio CODEC device
  4 *
  5 * Copyright (C) 2005-2006 Texas Instruments, Inc.
  6 *
  7 * Based on tlv320aic23.c:
  8 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
  9 */
 10
 11#ifndef __TWL_H_
 12#define __TWL_H_
 13
 14#include <linux/types.h>
 15#include <linux/input/matrix_keypad.h>
 16
 17/*
 18 * Using the twl4030 core we address registers using a pair
 19 *	{ module id, relative register offset }
 20 * which that core then maps to the relevant
 21 *	{ i2c slave, absolute register address }
 22 *
 23 * The module IDs are meaningful only to the twl4030 core code,
 24 * which uses them as array indices to look up the first register
 25 * address each module uses within a given i2c slave.
 26 */
 27
 28/* Module IDs for similar functionalities found in twl4030/twl6030 */
 29enum twl_module_ids {
 30	TWL_MODULE_USB,
 31	TWL_MODULE_PIH,
 32	TWL_MODULE_MAIN_CHARGE,
 33	TWL_MODULE_PM_MASTER,
 34	TWL_MODULE_PM_RECEIVER,
 35
 36	TWL_MODULE_RTC,
 37	TWL_MODULE_PWM,
 38	TWL_MODULE_LED,
 39	TWL_MODULE_SECURED_REG,
 40
 41	TWL_MODULE_LAST,
 42};
 43
 44/* Modules only available in twl4030 series */
 45enum twl4030_module_ids {
 46	TWL4030_MODULE_AUDIO_VOICE = TWL_MODULE_LAST,
 47	TWL4030_MODULE_GPIO,
 48	TWL4030_MODULE_INTBR,
 49	TWL4030_MODULE_TEST,
 50	TWL4030_MODULE_KEYPAD,
 51
 52	TWL4030_MODULE_MADC,
 53	TWL4030_MODULE_INTERRUPTS,
 54	TWL4030_MODULE_PRECHARGE,
 55	TWL4030_MODULE_BACKUP,
 56	TWL4030_MODULE_INT,
 57
 58	TWL5031_MODULE_ACCESSORY,
 59	TWL5031_MODULE_INTERRUPTS,
 60
 61	TWL4030_MODULE_LAST,
 62};
 63
 64/* Modules only available in twl6030 series */
 65enum twl6030_module_ids {
 66	TWL6030_MODULE_ID0 = TWL_MODULE_LAST,
 67	TWL6030_MODULE_ID1,
 68	TWL6030_MODULE_ID2,
 69	TWL6030_MODULE_GPADC,
 70	TWL6030_MODULE_GASGAUGE,
 71
 72	/* A few extra registers before the registers shared with the 6030 */
 73	TWL6032_MODULE_CHARGE,
 74	TWL6030_MODULE_LAST,
 75};
 76
 77/* Until the clients has been converted to use TWL_MODULE_LED */
 78#define TWL4030_MODULE_LED	TWL_MODULE_LED
 79
 80#define GPIO_INTR_OFFSET	0
 81#define KEYPAD_INTR_OFFSET	1
 82#define BCI_INTR_OFFSET		2
 83#define MADC_INTR_OFFSET	3
 84#define USB_INTR_OFFSET		4
 85#define CHARGERFAULT_INTR_OFFSET 5
 86#define BCI_PRES_INTR_OFFSET	9
 87#define USB_PRES_INTR_OFFSET	10
 88#define RTC_INTR_OFFSET		11
 89
 90/*
 91 * Offset from TWL6030_IRQ_BASE / pdata->irq_base
 92 */
 93#define PWR_INTR_OFFSET		0
 94#define HOTDIE_INTR_OFFSET	12
 95#define SMPSLDO_INTR_OFFSET	13
 96#define BATDETECT_INTR_OFFSET	14
 97#define SIMDETECT_INTR_OFFSET	15
 98#define MMCDETECT_INTR_OFFSET	16
 99#define GASGAUGE_INTR_OFFSET	17
100#define USBOTG_INTR_OFFSET	4
101#define CHARGER_INTR_OFFSET	2
102#define RSV_INTR_OFFSET		0
103
104/* INT register offsets */
105#define REG_INT_STS_A			0x00
106#define REG_INT_STS_B			0x01
107#define REG_INT_STS_C			0x02
108
109#define REG_INT_MSK_LINE_A		0x03
110#define REG_INT_MSK_LINE_B		0x04
111#define REG_INT_MSK_LINE_C		0x05
112
113#define REG_INT_MSK_STS_A		0x06
114#define REG_INT_MSK_STS_B		0x07
115#define REG_INT_MSK_STS_C		0x08
116
117/* MASK INT REG GROUP A */
118#define TWL6030_PWR_INT_MASK 		0x07
119#define TWL6030_RTC_INT_MASK 		0x18
120#define TWL6030_HOTDIE_INT_MASK 	0x20
121#define TWL6030_SMPSLDOA_INT_MASK	0xC0
122
123/* MASK INT REG GROUP B */
124#define TWL6030_SMPSLDOB_INT_MASK 	0x01
125#define TWL6030_BATDETECT_INT_MASK 	0x02
126#define TWL6030_SIMDETECT_INT_MASK 	0x04
127#define TWL6030_MMCDETECT_INT_MASK 	0x08
128#define TWL6030_GPADC_INT_MASK 		0x60
129#define TWL6030_GASGAUGE_INT_MASK 	0x80
130
131/* MASK INT REG GROUP C */
132#define TWL6030_USBOTG_INT_MASK  	0x0F
133#define TWL6030_CHARGER_CTRL_INT_MASK 	0x10
134#define TWL6030_CHARGER_FAULT_INT_MASK 	0x60
135
136#define TWL6030_MMCCTRL		0xEE
137#define VMMC_AUTO_OFF			(0x1 << 3)
138#define SW_FC				(0x1 << 2)
139#define STS_MMC			0x1
140
141#define TWL6030_CFG_INPUT_PUPD3	0xF2
142#define MMC_PU				(0x1 << 3)
143#define MMC_PD				(0x1 << 2)
144
145#define TWL_SIL_TYPE(rev)		((rev) & 0x00FFFFFF)
146#define TWL_SIL_REV(rev)		((rev) >> 24)
147#define TWL_SIL_5030			0x09002F
148#define TWL5030_REV_1_0			0x00
149#define TWL5030_REV_1_1			0x10
150#define TWL5030_REV_1_2			0x30
151
152#define TWL4030_CLASS_ID 		0x4030
153#define TWL6030_CLASS_ID 		0x6030
154unsigned int twl_rev(void);
155#define GET_TWL_REV (twl_rev())
156#define TWL_CLASS_IS(class, id)			\
157static inline int twl_class_is_ ##class(void)	\
158{						\
159	return ((id) == (GET_TWL_REV)) ? 1 : 0;	\
160}
161
162TWL_CLASS_IS(4030, TWL4030_CLASS_ID)
163TWL_CLASS_IS(6030, TWL6030_CLASS_ID)
164
165/* Set the regcache bypass for the regmap associated with the nodule */
166int twl_set_regcache_bypass(u8 mod_no, bool enable);
167
168/*
169 * Read and write several 8-bit registers at once.
170 */
171int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
172int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
173
174/*
175 * Read and write single 8-bit registers
176 */
177static inline int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg) {
178	return twl_i2c_write(mod_no, &val, reg, 1);
179}
180
181static inline int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg) {
182	return twl_i2c_read(mod_no, val, reg, 1);
183}
184
185static inline int twl_i2c_write_u16(u8 mod_no, u16 val, u8 reg) {
186	__le16 value;
187
188	value = cpu_to_le16(val);
189	return twl_i2c_write(mod_no, (u8 *) &value, reg, 2);
190}
191
192static inline int twl_i2c_read_u16(u8 mod_no, u16 *val, u8 reg) {
193	int ret;
194	__le16 value;
195
196	ret = twl_i2c_read(mod_no, (u8 *) &value, reg, 2);
197	*val = le16_to_cpu(value);
198	return ret;
199}
200
201int twl_get_type(void);
202int twl_get_version(void);
203int twl_get_hfclk_rate(void);
204
205int twl6030_interrupt_unmask(u8 bit_mask, u8 offset);
206int twl6030_interrupt_mask(u8 bit_mask, u8 offset);
207
208/*----------------------------------------------------------------------*/
209
210/*
211 * NOTE:  at up to 1024 registers, this is a big chip.
212 *
213 * Avoid putting register declarations in this file, instead of into
214 * a driver-private file, unless some of the registers in a block
215 * need to be shared with other drivers.  One example is blocks that
216 * have Secondary IRQ Handler (SIH) registers.
217 */
218
219#define TWL4030_SIH_CTRL_EXCLEN_MASK	BIT(0)
220#define TWL4030_SIH_CTRL_PENDDIS_MASK	BIT(1)
221#define TWL4030_SIH_CTRL_COR_MASK	BIT(2)
222
223/*----------------------------------------------------------------------*/
224
225/*
226 * GPIO Block Register offsets (use TWL4030_MODULE_GPIO)
227 */
228
229#define REG_GPIODATAIN1			0x0
230#define REG_GPIODATAIN2			0x1
231#define REG_GPIODATAIN3			0x2
232#define REG_GPIODATADIR1		0x3
233#define REG_GPIODATADIR2		0x4
234#define REG_GPIODATADIR3		0x5
235#define REG_GPIODATAOUT1		0x6
236#define REG_GPIODATAOUT2		0x7
237#define REG_GPIODATAOUT3		0x8
238#define REG_CLEARGPIODATAOUT1		0x9
239#define REG_CLEARGPIODATAOUT2		0xA
240#define REG_CLEARGPIODATAOUT3		0xB
241#define REG_SETGPIODATAOUT1		0xC
242#define REG_SETGPIODATAOUT2		0xD
243#define REG_SETGPIODATAOUT3		0xE
244#define REG_GPIO_DEBEN1			0xF
245#define REG_GPIO_DEBEN2			0x10
246#define REG_GPIO_DEBEN3			0x11
247#define REG_GPIO_CTRL			0x12
248#define REG_GPIOPUPDCTR1		0x13
249#define REG_GPIOPUPDCTR2		0x14
250#define REG_GPIOPUPDCTR3		0x15
251#define REG_GPIOPUPDCTR4		0x16
252#define REG_GPIOPUPDCTR5		0x17
253#define REG_GPIO_ISR1A			0x19
254#define REG_GPIO_ISR2A			0x1A
255#define REG_GPIO_ISR3A			0x1B
256#define REG_GPIO_IMR1A			0x1C
257#define REG_GPIO_IMR2A			0x1D
258#define REG_GPIO_IMR3A			0x1E
259#define REG_GPIO_ISR1B			0x1F
260#define REG_GPIO_ISR2B			0x20
261#define REG_GPIO_ISR3B			0x21
262#define REG_GPIO_IMR1B			0x22
263#define REG_GPIO_IMR2B			0x23
264#define REG_GPIO_IMR3B			0x24
265#define REG_GPIO_EDR1			0x28
266#define REG_GPIO_EDR2			0x29
267#define REG_GPIO_EDR3			0x2A
268#define REG_GPIO_EDR4			0x2B
269#define REG_GPIO_EDR5			0x2C
270#define REG_GPIO_SIH_CTRL		0x2D
271
272/* Up to 18 signals are available as GPIOs, when their
273 * pins are not assigned to another use (such as ULPI/USB).
274 */
275#define TWL4030_GPIO_MAX		18
276
277/*----------------------------------------------------------------------*/
278
279/*Interface Bit Register (INTBR) offsets
280 *(Use TWL_4030_MODULE_INTBR)
281 */
282
283#define REG_IDCODE_7_0			0x00
284#define REG_IDCODE_15_8			0x01
285#define REG_IDCODE_16_23		0x02
286#define REG_IDCODE_31_24		0x03
287#define REG_GPPUPDCTR1			0x0F
288#define REG_UNLOCK_TEST_REG		0x12
289
290/*I2C1 and I2C4(SR) SDA/SCL pull-up control bits */
291
292#define I2C_SCL_CTRL_PU			BIT(0)
293#define I2C_SDA_CTRL_PU			BIT(2)
294#define SR_I2C_SCL_CTRL_PU		BIT(4)
295#define SR_I2C_SDA_CTRL_PU		BIT(6)
296
297#define TWL_EEPROM_R_UNLOCK		0x49
298
299/*----------------------------------------------------------------------*/
300
301/*
302 * Keypad register offsets (use TWL4030_MODULE_KEYPAD)
303 * ... SIH/interrupt only
304 */
305
306#define TWL4030_KEYPAD_KEYP_ISR1	0x11
307#define TWL4030_KEYPAD_KEYP_IMR1	0x12
308#define TWL4030_KEYPAD_KEYP_ISR2	0x13
309#define TWL4030_KEYPAD_KEYP_IMR2	0x14
310#define TWL4030_KEYPAD_KEYP_SIR		0x15	/* test register */
311#define TWL4030_KEYPAD_KEYP_EDR		0x16
312#define TWL4030_KEYPAD_KEYP_SIH_CTRL	0x17
313
314/*----------------------------------------------------------------------*/
315
316/*
317 * Multichannel ADC register offsets (use TWL4030_MODULE_MADC)
318 * ... SIH/interrupt only
319 */
320
321#define TWL4030_MADC_ISR1		0x61
322#define TWL4030_MADC_IMR1		0x62
323#define TWL4030_MADC_ISR2		0x63
324#define TWL4030_MADC_IMR2		0x64
325#define TWL4030_MADC_SIR		0x65	/* test register */
326#define TWL4030_MADC_EDR		0x66
327#define TWL4030_MADC_SIH_CTRL		0x67
328
329/*----------------------------------------------------------------------*/
330
331/*
332 * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS)
333 */
334
335#define TWL4030_INTERRUPTS_BCIISR1A	0x0
336#define TWL4030_INTERRUPTS_BCIISR2A	0x1
337#define TWL4030_INTERRUPTS_BCIIMR1A	0x2
338#define TWL4030_INTERRUPTS_BCIIMR2A	0x3
339#define TWL4030_INTERRUPTS_BCIISR1B	0x4
340#define TWL4030_INTERRUPTS_BCIISR2B	0x5
341#define TWL4030_INTERRUPTS_BCIIMR1B	0x6
342#define TWL4030_INTERRUPTS_BCIIMR2B	0x7
343#define TWL4030_INTERRUPTS_BCISIR1	0x8	/* test register */
344#define TWL4030_INTERRUPTS_BCISIR2	0x9	/* test register */
345#define TWL4030_INTERRUPTS_BCIEDR1	0xa
346#define TWL4030_INTERRUPTS_BCIEDR2	0xb
347#define TWL4030_INTERRUPTS_BCIEDR3	0xc
348#define TWL4030_INTERRUPTS_BCISIHCTRL	0xd
349
350/*----------------------------------------------------------------------*/
351
352/*
353 * Power Interrupt block register offsets (use TWL4030_MODULE_INT)
354 */
355
356#define TWL4030_INT_PWR_ISR1		0x0
357#define TWL4030_INT_PWR_IMR1		0x1
358#define TWL4030_INT_PWR_ISR2		0x2
359#define TWL4030_INT_PWR_IMR2		0x3
360#define TWL4030_INT_PWR_SIR		0x4	/* test register */
361#define TWL4030_INT_PWR_EDR1		0x5
362#define TWL4030_INT_PWR_EDR2		0x6
363#define TWL4030_INT_PWR_SIH_CTRL	0x7
364
365/*----------------------------------------------------------------------*/
366
367/*
368 * Accessory Interrupts
369 */
370#define TWL5031_ACIIMR_LSB		0x05
371#define TWL5031_ACIIMR_MSB		0x06
372#define TWL5031_ACIIDR_LSB		0x07
373#define TWL5031_ACIIDR_MSB		0x08
374#define TWL5031_ACCISR1			0x0F
375#define TWL5031_ACCIMR1			0x10
376#define TWL5031_ACCISR2			0x11
377#define TWL5031_ACCIMR2			0x12
378#define TWL5031_ACCSIR			0x13
379#define TWL5031_ACCEDR1			0x14
380#define TWL5031_ACCSIHCTRL		0x15
381
382/*----------------------------------------------------------------------*/
383
384/*
385 * Battery Charger Controller
386 */
387
388#define TWL5031_INTERRUPTS_BCIISR1	0x0
389#define TWL5031_INTERRUPTS_BCIIMR1	0x1
390#define TWL5031_INTERRUPTS_BCIISR2	0x2
391#define TWL5031_INTERRUPTS_BCIIMR2	0x3
392#define TWL5031_INTERRUPTS_BCISIR	0x4
393#define TWL5031_INTERRUPTS_BCIEDR1	0x5
394#define TWL5031_INTERRUPTS_BCIEDR2	0x6
395#define TWL5031_INTERRUPTS_BCISIHCTRL	0x7
396
397/*----------------------------------------------------------------------*/
398
399/*
400 * PM Master module register offsets (use TWL4030_MODULE_PM_MASTER)
401 */
402
403#define TWL4030_PM_MASTER_CFG_P1_TRANSITION	0x00
404#define TWL4030_PM_MASTER_CFG_P2_TRANSITION	0x01
405#define TWL4030_PM_MASTER_CFG_P3_TRANSITION	0x02
406#define TWL4030_PM_MASTER_CFG_P123_TRANSITION	0x03
407#define TWL4030_PM_MASTER_STS_BOOT		0x04
408#define TWL4030_PM_MASTER_CFG_BOOT		0x05
409#define TWL4030_PM_MASTER_SHUNDAN		0x06
410#define TWL4030_PM_MASTER_BOOT_BCI		0x07
411#define TWL4030_PM_MASTER_CFG_PWRANA1		0x08
412#define TWL4030_PM_MASTER_CFG_PWRANA2		0x09
413#define TWL4030_PM_MASTER_BACKUP_MISC_STS	0x0b
414#define TWL4030_PM_MASTER_BACKUP_MISC_CFG	0x0c
415#define TWL4030_PM_MASTER_BACKUP_MISC_TST	0x0d
416#define TWL4030_PM_MASTER_PROTECT_KEY		0x0e
417#define TWL4030_PM_MASTER_STS_HW_CONDITIONS	0x0f
418#define TWL4030_PM_MASTER_P1_SW_EVENTS		0x10
419#define TWL4030_PM_MASTER_P2_SW_EVENTS		0x11
420#define TWL4030_PM_MASTER_P3_SW_EVENTS		0x12
421#define TWL4030_PM_MASTER_STS_P123_STATE	0x13
422#define TWL4030_PM_MASTER_PB_CFG		0x14
423#define TWL4030_PM_MASTER_PB_WORD_MSB		0x15
424#define TWL4030_PM_MASTER_PB_WORD_LSB		0x16
425#define TWL4030_PM_MASTER_SEQ_ADD_W2P		0x1c
426#define TWL4030_PM_MASTER_SEQ_ADD_P2A		0x1d
427#define TWL4030_PM_MASTER_SEQ_ADD_A2W		0x1e
428#define TWL4030_PM_MASTER_SEQ_ADD_A2S		0x1f
429#define TWL4030_PM_MASTER_SEQ_ADD_S2A12		0x20
430#define TWL4030_PM_MASTER_SEQ_ADD_S2A3		0x21
431#define TWL4030_PM_MASTER_SEQ_ADD_WARM		0x22
432#define TWL4030_PM_MASTER_MEMORY_ADDRESS	0x23
433#define TWL4030_PM_MASTER_MEMORY_DATA		0x24
434
435#define TWL4030_PM_MASTER_KEY_CFG1		0xc0
436#define TWL4030_PM_MASTER_KEY_CFG2		0x0c
437
438#define TWL4030_PM_MASTER_KEY_TST1		0xe0
439#define TWL4030_PM_MASTER_KEY_TST2		0x0e
440
441#define TWL4030_PM_MASTER_GLOBAL_TST		0xb6
442
443#define TWL6030_PHOENIX_DEV_ON                  0x06
444/*----------------------------------------------------------------------*/
445
446/* Power bus message definitions */
447
448/* The TWL4030/5030 splits its power-management resources (the various
449 * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
450 * P3. These groups can then be configured to transition between sleep, wait-on
451 * and active states by sending messages to the power bus.  See Section 5.4.2
452 * Power Resources of TWL4030 TRM
453 */
454
455/* Processor groups */
456#define DEV_GRP_NULL		0x0
457#define DEV_GRP_P1		0x1	/* P1: all OMAP devices */
458#define DEV_GRP_P2		0x2	/* P2: all Modem devices */
459#define DEV_GRP_P3		0x4	/* P3: all peripheral devices */
460
461/* Resource groups */
462#define RES_GRP_RES		0x0	/* Reserved */
463#define RES_GRP_PP		0x1	/* Power providers */
464#define RES_GRP_RC		0x2	/* Reset and control */
465#define RES_GRP_PP_RC		0x3
466#define RES_GRP_PR		0x4	/* Power references */
467#define RES_GRP_PP_PR		0x5
468#define RES_GRP_RC_PR		0x6
469#define RES_GRP_ALL		0x7	/* All resource groups */
470
471#define RES_TYPE2_R0		0x0
472#define RES_TYPE2_R1		0x1
473#define RES_TYPE2_R2		0x2
474
475#define RES_TYPE_R0		0x0
476#define RES_TYPE_ALL		0x7
477
478/* Resource states */
479#define RES_STATE_WRST		0xF
480#define RES_STATE_ACTIVE	0xE
481#define RES_STATE_SLEEP		0x8
482#define RES_STATE_OFF		0x0
483
484/* Power resources */
485
486/* Power providers */
487#define RES_VAUX1               1
488#define RES_VAUX2               2
489#define RES_VAUX3               3
490#define RES_VAUX4               4
491#define RES_VMMC1               5
492#define RES_VMMC2               6
493#define RES_VPLL1               7
494#define RES_VPLL2               8
495#define RES_VSIM                9
496#define RES_VDAC                10
497#define RES_VINTANA1            11
498#define RES_VINTANA2            12
499#define RES_VINTDIG             13
500#define RES_VIO                 14
501#define RES_VDD1                15
502#define RES_VDD2                16
503#define RES_VUSB_1V5            17
504#define RES_VUSB_1V8            18
505#define RES_VUSB_3V1            19
506#define RES_VUSBCP              20
507#define RES_REGEN               21
508/* Reset and control */
509#define RES_NRES_PWRON          22
510#define RES_CLKEN               23
511#define RES_SYSEN               24
512#define RES_HFCLKOUT            25
513#define RES_32KCLKOUT           26
514#define RES_RESET               27
515/* Power Reference */
516#define RES_MAIN_REF            28
517
518#define TOTAL_RESOURCES		28
519/*
520 * Power Bus Message Format ... these can be sent individually by Linux,
521 * but are usually part of downloaded scripts that are run when various
522 * power events are triggered.
523 *
524 *  Broadcast Message (16 Bits):
525 *    DEV_GRP[15:13] MT[12]  RES_GRP[11:9]  RES_TYPE2[8:7] RES_TYPE[6:4]
526 *    RES_STATE[3:0]
527 *
528 *  Singular Message (16 Bits):
529 *    DEV_GRP[15:13] MT[12]  RES_ID[11:4]  RES_STATE[3:0]
530 */
531
532#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
533	( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
534	| (type) << 4 | (state))
535
536#define MSG_SINGULAR(devgrp, id, state) \
537	((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
538
539#define MSG_BROADCAST_ALL(devgrp, state) \
540	((devgrp) << 5 | (state))
541
542#define MSG_BROADCAST_REF MSG_BROADCAST_ALL
543#define MSG_BROADCAST_PROV MSG_BROADCAST_ALL
544#define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL
545/*----------------------------------------------------------------------*/
546
547struct twl4030_clock_init_data {
548	bool ck32k_lowpwr_enable;
549};
550
551struct twl4030_bci_platform_data {
552	int *battery_tmp_tbl;
553	unsigned int tblsize;
554	int	bb_uvolt;	/* voltage to charge backup battery */
555	int	bb_uamp;	/* current for backup battery charging */
556};
557
558/* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */
559struct twl4030_gpio_platform_data {
560	/* package the two LED signals as output-only GPIOs? */
561	bool		use_leds;
562
563	/* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */
564	u8		mmc_cd;
565
566	/* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */
567	u32		debounce;
568
569	/* For gpio-N, bit (1 << N) in "pullups" is set if that pullup
570	 * should be enabled.  Else, if that bit is set in "pulldowns",
571	 * that pulldown is enabled.  Don't waste power by letting any
572	 * digital inputs float...
573	 */
574	u32		pullups;
575	u32		pulldowns;
576};
577
578struct twl4030_madc_platform_data {
579	int		irq_line;
580};
581
582/* Boards have unique mappings of {row, col} --> keycode.
583 * Column and row are 8 bits each, but range only from 0..7.
584 * a PERSISTENT_KEY is "always on" and never reported.
585 */
586#define PERSISTENT_KEY(r, c)	KEY((r), (c), KEY_RESERVED)
587
588struct twl4030_keypad_data {
589	const struct matrix_keymap_data *keymap_data;
590	unsigned rows;
591	unsigned cols;
592	bool rep;
593};
594
595enum twl4030_usb_mode {
596	T2_USB_MODE_ULPI = 1,
597	T2_USB_MODE_CEA2011_3PIN = 2,
598};
599
600struct twl4030_usb_data {
601	enum twl4030_usb_mode	usb_mode;
602	unsigned long		features;
603
604	int		(*phy_init)(struct device *dev);
605	int		(*phy_exit)(struct device *dev);
606	/* Power on/off the PHY */
607	int		(*phy_power)(struct device *dev, int iD, int on);
608	/* enable/disable  phy clocks */
609	int		(*phy_set_clock)(struct device *dev, int on);
610	/* suspend/resume of phy */
611	int		(*phy_suspend)(struct device *dev, int suspend);
612};
613
614struct twl4030_ins {
615	u16 pmb_message;
616	u8 delay;
617};
618
619struct twl4030_script {
620	struct twl4030_ins *script;
621	unsigned size;
622	u8 flags;
623#define TWL4030_WRST_SCRIPT	(1<<0)
624#define TWL4030_WAKEUP12_SCRIPT	(1<<1)
625#define TWL4030_WAKEUP3_SCRIPT	(1<<2)
626#define TWL4030_SLEEP_SCRIPT	(1<<3)
627};
628
629struct twl4030_resconfig {
630	u8 resource;
631	u8 devgroup;	/* Processor group that Power resource belongs to */
632	u8 type;	/* Power resource addressed, 6 / broadcast message */
633	u8 type2;	/* Power resource addressed, 3 / broadcast message */
634	u8 remap_off;	/* off state remapping */
635	u8 remap_sleep;	/* sleep state remapping */
636};
637
638struct twl4030_power_data {
639	struct twl4030_script **scripts;
640	unsigned num;
641	struct twl4030_resconfig *resource_config;
642	struct twl4030_resconfig *board_config;
643#define TWL4030_RESCONFIG_UNDEF	((u8)-1)
644	bool use_poweroff;	/* Board is wired for TWL poweroff */
645	bool ac_charger_quirk;	/* Disable AC charger on board */
646};
647
648extern int twl4030_remove_script(u8 flags);
649extern void twl4030_power_off(void);
650
651struct twl4030_codec_data {
652	unsigned int digimic_delay; /* in ms */
653	unsigned int ramp_delay_value;
654	unsigned int offset_cncl_path;
655	unsigned int hs_extmute:1;
656	int hs_extmute_gpio;
657};
658
659struct twl4030_vibra_data {
660	unsigned int	coexist;
661};
662
663struct twl4030_audio_data {
664	unsigned int	audio_mclk;
665	struct twl4030_codec_data *codec;
666	struct twl4030_vibra_data *vibra;
667
668	/* twl6040 */
669	int audpwron_gpio;	/* audio power-on gpio */
670	int naudint_irq;	/* audio interrupt */
671	unsigned int irq_base;
672};
673
674struct twl_regulator_driver_data {
675	int		(*set_voltage)(void *data, int target_uV);
676	int		(*get_voltage)(void *data);
677	void		*data;
678	unsigned long	features;
679};
680/* chip-specific feature flags, for twl_regulator_driver_data.features */
681#define TWL4030_VAUX2		BIT(0)	/* pre-5030 voltage ranges */
682#define TPS_SUBSET		BIT(1)	/* tps659[23]0 have fewer LDOs */
683#define TWL5031			BIT(2)  /* twl5031 has different registers */
684#define TWL6030_CLASS		BIT(3)	/* TWL6030 class */
685#define TWL6032_SUBCLASS	BIT(4)  /* TWL6032 has changed registers */
686#define TWL4030_ALLOW_UNSUPPORTED BIT(5) /* Some voltages are possible
687					  * but not officially supported.
688					  * This flag is necessary to
689					  * enable them.
690					  */
691
692/*----------------------------------------------------------------------*/
693
694int twl4030_sih_setup(struct device *dev, int module, int irq_base);
695
696/* Offsets to Power Registers */
697#define TWL4030_VDAC_DEV_GRP		0x3B
698#define TWL4030_VDAC_DEDICATED		0x3E
699#define TWL4030_VAUX1_DEV_GRP		0x17
700#define TWL4030_VAUX1_DEDICATED		0x1A
701#define TWL4030_VAUX2_DEV_GRP		0x1B
702#define TWL4030_VAUX2_DEDICATED		0x1E
703#define TWL4030_VAUX3_DEV_GRP		0x1F
704#define TWL4030_VAUX3_DEDICATED		0x22
705
706/*----------------------------------------------------------------------*/
707
708/* Linux-specific regulator identifiers ... for now, we only support
709 * the LDOs, and leave the three buck converters alone.  VDD1 and VDD2
710 * need to tie into hardware based voltage scaling (cpufreq etc), while
711 * VIO is generally fixed.
712 */
713
714/* TWL4030 SMPS/LDO's */
715/* EXTERNAL dc-to-dc buck converters */
716#define TWL4030_REG_VDD1	0
717#define TWL4030_REG_VDD2	1
718#define TWL4030_REG_VIO		2
719
720/* EXTERNAL LDOs */
721#define TWL4030_REG_VDAC	3
722#define TWL4030_REG_VPLL1	4
723#define TWL4030_REG_VPLL2	5	/* not on all chips */
724#define TWL4030_REG_VMMC1	6
725#define TWL4030_REG_VMMC2	7	/* not on all chips */
726#define TWL4030_REG_VSIM	8	/* not on all chips */
727#define TWL4030_REG_VAUX1	9	/* not on all chips */
728#define TWL4030_REG_VAUX2_4030	10	/* (twl4030-specific) */
729#define TWL4030_REG_VAUX2	11	/* (twl5030 and newer) */
730#define TWL4030_REG_VAUX3	12	/* not on all chips */
731#define TWL4030_REG_VAUX4	13	/* not on all chips */
732
733/* INTERNAL LDOs */
734#define TWL4030_REG_VINTANA1	14
735#define TWL4030_REG_VINTANA2	15
736#define TWL4030_REG_VINTDIG	16
737#define TWL4030_REG_VUSB1V5	17
738#define TWL4030_REG_VUSB1V8	18
739#define TWL4030_REG_VUSB3V1	19
740
741/* TWL6030 SMPS/LDO's */
742/* EXTERNAL dc-to-dc buck convertor controllable via SR */
743#define TWL6030_REG_VDD1	30
744#define TWL6030_REG_VDD2	31
745#define TWL6030_REG_VDD3	32
746
747/* Non SR compliant dc-to-dc buck convertors */
748#define TWL6030_REG_VMEM	33
749#define TWL6030_REG_V2V1	34
750#define TWL6030_REG_V1V29	35
751#define TWL6030_REG_V1V8	36
752
753/* EXTERNAL LDOs */
754#define TWL6030_REG_VAUX1_6030	37
755#define TWL6030_REG_VAUX2_6030	38
756#define TWL6030_REG_VAUX3_6030	39
757#define TWL6030_REG_VMMC	40
758#define TWL6030_REG_VPP		41
759#define TWL6030_REG_VUSIM	42
760#define TWL6030_REG_VANA	43
761#define TWL6030_REG_VCXIO	44
762#define TWL6030_REG_VDAC	45
763#define TWL6030_REG_VUSB	46
764
765/* INTERNAL LDOs */
766#define TWL6030_REG_VRTC	47
767#define TWL6030_REG_CLK32KG	48
768
769/* LDOs on 6025 have different names */
770#define TWL6032_REG_LDO2	49
771#define TWL6032_REG_LDO4	50
772#define TWL6032_REG_LDO3	51
773#define TWL6032_REG_LDO5	52
774#define TWL6032_REG_LDO1	53
775#define TWL6032_REG_LDO7	54
776#define TWL6032_REG_LDO6	55
777#define TWL6032_REG_LDOLN	56
778#define TWL6032_REG_LDOUSB	57
779
780/* 6025 DCDC supplies */
781#define TWL6032_REG_SMPS3	58
782#define TWL6032_REG_SMPS4	59
783#define TWL6032_REG_VIO		60
784
785
786#endif /* End of __TWL4030_H */