tps6594.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Functions to access TPS6594 Power Management IC
   4 *
   5 * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
   6 */
   7
   8#ifndef __LINUX_MFD_TPS6594_H
   9#define __LINUX_MFD_TPS6594_H
  10
  11#include <linux/device.h>
  12#include <linux/regmap.h>
  13
  14struct regmap_irq_chip_data;
  15
  16/* Chip id list */
  17enum pmic_id {
  18	TPS6594,
  19	TPS6593,
  20	LP8764,
  21	TPS65224,
  22	TPS652G1,
  23};
  24
  25/* Macro to get page index from register address */
  26#define TPS6594_REG_TO_PAGE(reg)	((reg) >> 8)
  27
  28/* Registers for page 0 */
  29#define TPS6594_REG_DEV_REV				0x01
  30
  31#define TPS6594_REG_NVM_CODE_1				0x02
  32#define TPS6594_REG_NVM_CODE_2				0x03
  33
  34#define TPS6594_REG_BUCKX_CTRL(buck_inst)		(0x04 + ((buck_inst) << 1))
  35#define TPS6594_REG_BUCKX_CONF(buck_inst)		(0x05 + ((buck_inst) << 1))
  36#define TPS6594_REG_BUCKX_VOUT_1(buck_inst)		(0x0e + ((buck_inst) << 1))
  37#define TPS6594_REG_BUCKX_VOUT_2(buck_inst)		(0x0f + ((buck_inst) << 1))
  38#define TPS6594_REG_BUCKX_PG_WINDOW(buck_inst)		(0x18 + (buck_inst))
  39
  40#define TPS6594_REG_LDOX_CTRL(ldo_inst)			(0x1d + (ldo_inst))
  41#define TPS6594_REG_LDORTC_CTRL				0x22
  42#define TPS6594_REG_LDOX_VOUT(ldo_inst)			(0x23 + (ldo_inst))
  43#define TPS6594_REG_LDOX_PG_WINDOW(ldo_inst)		(0x27 + (ldo_inst))
  44
  45#define TPS6594_REG_VCCA_VMON_CTRL			0x2b
  46#define TPS6594_REG_VCCA_PG_WINDOW			0x2c
  47#define TPS6594_REG_VMON1_PG_WINDOW			0x2d
  48#define TPS6594_REG_VMON1_PG_LEVEL			0x2e
  49#define TPS6594_REG_VMON2_PG_WINDOW			0x2f
  50#define TPS6594_REG_VMON2_PG_LEVEL			0x30
  51
  52#define TPS6594_REG_GPIOX_CONF(gpio_inst)		(0x31 + (gpio_inst))
  53#define TPS6594_REG_NPWRON_CONF				0x3c
  54#define TPS6594_REG_GPIO_OUT_1				0x3d
  55#define TPS6594_REG_GPIO_OUT_2				0x3e
  56#define TPS6594_REG_GPIO_IN_1				0x3f
  57#define TPS6594_REG_GPIO_IN_2				0x40
  58#define TPS6594_REG_GPIOX_OUT(gpio_inst)		(TPS6594_REG_GPIO_OUT_1 + (gpio_inst) / 8)
  59#define TPS6594_REG_GPIOX_IN(gpio_inst)			(TPS6594_REG_GPIO_IN_1 + (gpio_inst) / 8)
  60
  61#define TPS6594_REG_RAIL_SEL_1				0x41
  62#define TPS6594_REG_RAIL_SEL_2				0x42
  63#define TPS6594_REG_RAIL_SEL_3				0x43
  64
  65#define TPS6594_REG_FSM_TRIG_SEL_1			0x44
  66#define TPS6594_REG_FSM_TRIG_SEL_2			0x45
  67#define TPS6594_REG_FSM_TRIG_MASK_1			0x46
  68#define TPS6594_REG_FSM_TRIG_MASK_2			0x47
  69#define TPS6594_REG_FSM_TRIG_MASK_3			0x48
  70
  71#define TPS6594_REG_MASK_BUCK1_2			0x49
  72#define TPS65224_REG_MASK_BUCKS				0x49
  73#define TPS6594_REG_MASK_BUCK3_4			0x4a
  74#define TPS6594_REG_MASK_BUCK5				0x4b
  75#define TPS6594_REG_MASK_LDO1_2				0x4c
  76#define TPS65224_REG_MASK_LDOS				0x4c
  77#define TPS6594_REG_MASK_LDO3_4				0x4d
  78#define TPS6594_REG_MASK_VMON				0x4e
  79#define TPS6594_REG_MASK_GPIO_FALL			0x4f
  80#define TPS6594_REG_MASK_GPIO_RISE			0x50
  81#define TPS6594_REG_MASK_GPIO9_11			0x51
  82#define TPS6594_REG_MASK_STARTUP			0x52
  83#define TPS6594_REG_MASK_MISC				0x53
  84#define TPS6594_REG_MASK_MODERATE_ERR			0x54
  85#define TPS6594_REG_MASK_FSM_ERR			0x56
  86#define TPS6594_REG_MASK_COMM_ERR			0x57
  87#define TPS6594_REG_MASK_READBACK_ERR			0x58
  88#define TPS6594_REG_MASK_ESM				0x59
  89
  90#define TPS6594_REG_INT_TOP				0x5a
  91#define TPS6594_REG_INT_BUCK				0x5b
  92#define TPS6594_REG_INT_BUCK1_2				0x5c
  93#define TPS6594_REG_INT_BUCK3_4				0x5d
  94#define TPS6594_REG_INT_BUCK5				0x5e
  95#define TPS6594_REG_INT_LDO_VMON			0x5f
  96#define TPS6594_REG_INT_LDO1_2				0x60
  97#define TPS6594_REG_INT_LDO3_4				0x61
  98#define TPS6594_REG_INT_VMON				0x62
  99#define TPS6594_REG_INT_GPIO				0x63
 100#define TPS6594_REG_INT_GPIO1_8				0x64
 101#define TPS6594_REG_INT_STARTUP				0x65
 102#define TPS6594_REG_INT_MISC				0x66
 103#define TPS6594_REG_INT_MODERATE_ERR			0x67
 104#define TPS6594_REG_INT_SEVERE_ERR			0x68
 105#define TPS6594_REG_INT_FSM_ERR				0x69
 106#define TPS6594_REG_INT_COMM_ERR			0x6a
 107#define TPS6594_REG_INT_READBACK_ERR			0x6b
 108#define TPS6594_REG_INT_ESM				0x6c
 109
 110#define TPS6594_REG_STAT_BUCK1_2			0x6d
 111#define TPS6594_REG_STAT_BUCK3_4			0x6e
 112#define TPS6594_REG_STAT_BUCK5				0x6f
 113#define TPS6594_REG_STAT_LDO1_2				0x70
 114#define TPS6594_REG_STAT_LDO3_4				0x71
 115#define TPS6594_REG_STAT_VMON				0x72
 116#define TPS6594_REG_STAT_STARTUP			0x73
 117#define TPS6594_REG_STAT_MISC				0x74
 118#define TPS6594_REG_STAT_MODERATE_ERR			0x75
 119#define TPS6594_REG_STAT_SEVERE_ERR			0x76
 120#define TPS6594_REG_STAT_READBACK_ERR			0x77
 121
 122#define TPS6594_REG_PGOOD_SEL_1				0x78
 123#define TPS6594_REG_PGOOD_SEL_2				0x79
 124#define TPS6594_REG_PGOOD_SEL_3				0x7a
 125#define TPS6594_REG_PGOOD_SEL_4				0x7b
 126
 127#define TPS6594_REG_PLL_CTRL				0x7c
 128
 129#define TPS6594_REG_CONFIG_1				0x7d
 130#define TPS6594_REG_CONFIG_2				0x7e
 131
 132#define TPS6594_REG_ENABLE_DRV_REG			0x80
 133
 134#define TPS6594_REG_MISC_CTRL				0x81
 135
 136#define TPS6594_REG_ENABLE_DRV_STAT			0x82
 137
 138#define TPS6594_REG_RECOV_CNT_REG_1			0x83
 139#define TPS6594_REG_RECOV_CNT_REG_2			0x84
 140
 141#define TPS6594_REG_FSM_I2C_TRIGGERS			0x85
 142#define TPS6594_REG_FSM_NSLEEP_TRIGGERS			0x86
 143
 144#define TPS6594_REG_BUCK_RESET_REG			0x87
 145
 146#define TPS6594_REG_SPREAD_SPECTRUM_1			0x88
 147
 148#define TPS6594_REG_FREQ_SEL				0x8a
 149
 150#define TPS6594_REG_FSM_STEP_SIZE			0x8b
 151
 152#define TPS6594_REG_LDO_RV_TIMEOUT_REG_1		0x8c
 153#define TPS6594_REG_LDO_RV_TIMEOUT_REG_2		0x8d
 154
 155#define TPS6594_REG_USER_SPARE_REGS			0x8e
 156
 157#define TPS6594_REG_ESM_MCU_START_REG			0x8f
 158#define TPS6594_REG_ESM_MCU_DELAY1_REG			0x90
 159#define TPS6594_REG_ESM_MCU_DELAY2_REG			0x91
 160#define TPS6594_REG_ESM_MCU_MODE_CFG			0x92
 161#define TPS6594_REG_ESM_MCU_HMAX_REG			0x93
 162#define TPS6594_REG_ESM_MCU_HMIN_REG			0x94
 163#define TPS6594_REG_ESM_MCU_LMAX_REG			0x95
 164#define TPS6594_REG_ESM_MCU_LMIN_REG			0x96
 165#define TPS6594_REG_ESM_MCU_ERR_CNT_REG			0x97
 166#define TPS6594_REG_ESM_SOC_START_REG			0x98
 167#define TPS6594_REG_ESM_SOC_DELAY1_REG			0x99
 168#define TPS6594_REG_ESM_SOC_DELAY2_REG			0x9a
 169#define TPS6594_REG_ESM_SOC_MODE_CFG			0x9b
 170#define TPS6594_REG_ESM_SOC_HMAX_REG			0x9c
 171#define TPS6594_REG_ESM_SOC_HMIN_REG			0x9d
 172#define TPS6594_REG_ESM_SOC_LMAX_REG			0x9e
 173#define TPS6594_REG_ESM_SOC_LMIN_REG			0x9f
 174#define TPS6594_REG_ESM_SOC_ERR_CNT_REG			0xa0
 175
 176#define TPS6594_REG_REGISTER_LOCK			0xa1
 177
 178#define TPS65224_REG_SRAM_ACCESS_1			0xa2
 179#define TPS65224_REG_SRAM_ACCESS_2			0xa3
 180#define TPS65224_REG_SRAM_ADDR_CTRL			0xa4
 181#define TPS65224_REG_RECOV_CNT_PFSM_INCR		0xa5
 182#define TPS6594_REG_MANUFACTURING_VER			0xa6
 183
 184#define TPS6594_REG_CUSTOMER_NVM_ID_REG			0xa7
 185
 186#define TPS6594_REG_VMON_CONF_REG			0xa8
 187
 188#define TPS6594_REG_SOFT_REBOOT_REG			0xab
 189
 190#define TPS65224_REG_ADC_CTRL				0xac
 191#define TPS65224_REG_ADC_RESULT_REG_1			0xad
 192#define TPS65224_REG_ADC_RESULT_REG_2			0xae
 193#define TPS6594_REG_RTC_SECONDS				0xb5
 194#define TPS6594_REG_RTC_MINUTES				0xb6
 195#define TPS6594_REG_RTC_HOURS				0xb7
 196#define TPS6594_REG_RTC_DAYS				0xb8
 197#define TPS6594_REG_RTC_MONTHS				0xb9
 198#define TPS6594_REG_RTC_YEARS				0xba
 199#define TPS6594_REG_RTC_WEEKS				0xbb
 200
 201#define TPS6594_REG_ALARM_SECONDS			0xbc
 202#define TPS6594_REG_ALARM_MINUTES			0xbd
 203#define TPS6594_REG_ALARM_HOURS				0xbe
 204#define TPS6594_REG_ALARM_DAYS				0xbf
 205#define TPS6594_REG_ALARM_MONTHS			0xc0
 206#define TPS6594_REG_ALARM_YEARS				0xc1
 207
 208#define TPS6594_REG_RTC_CTRL_1				0xc2
 209#define TPS6594_REG_RTC_CTRL_2				0xc3
 210#define TPS65224_REG_STARTUP_CTRL			0xc3
 211#define TPS6594_REG_RTC_STATUS				0xc4
 212#define TPS6594_REG_RTC_INTERRUPTS			0xc5
 213#define TPS6594_REG_RTC_COMP_LSB			0xc6
 214#define TPS6594_REG_RTC_COMP_MSB			0xc7
 215#define TPS6594_REG_RTC_RESET_STATUS			0xc8
 216
 217#define TPS6594_REG_SCRATCH_PAD_REG_1			0xc9
 218#define TPS6594_REG_SCRATCH_PAD_REG_2			0xca
 219#define TPS6594_REG_SCRATCH_PAD_REG_3			0xcb
 220#define TPS6594_REG_SCRATCH_PAD_REG_4			0xcc
 221
 222#define TPS6594_REG_PFSM_DELAY_REG_1			0xcd
 223#define TPS6594_REG_PFSM_DELAY_REG_2			0xce
 224#define TPS6594_REG_PFSM_DELAY_REG_3			0xcf
 225#define TPS6594_REG_PFSM_DELAY_REG_4			0xd0
 226#define TPS65224_REG_ADC_GAIN_COMP_REG			0xd0
 227#define TPS65224_REG_CRC_CALC_CONTROL			0xef
 228#define TPS65224_REG_REGMAP_USER_CRC_LOW		0xf0
 229#define TPS65224_REG_REGMAP_USER_CRC_HIGH		0xf1
 230
 231/* Registers for page 1 */
 232#define TPS6594_REG_SERIAL_IF_CONFIG			0x11a
 233#define TPS6594_REG_I2C1_ID				0x122
 234#define TPS6594_REG_I2C2_ID				0x123
 235
 236/* Registers for page 4 */
 237#define TPS6594_REG_WD_ANSWER_REG			0x401
 238#define TPS6594_REG_WD_QUESTION_ANSW_CNT		0x402
 239#define TPS6594_REG_WD_WIN1_CFG				0x403
 240#define TPS6594_REG_WD_WIN2_CFG				0x404
 241#define TPS6594_REG_WD_LONGWIN_CFG			0x405
 242#define TPS6594_REG_WD_MODE_REG				0x406
 243#define TPS6594_REG_WD_QA_CFG				0x407
 244#define TPS6594_REG_WD_ERR_STATUS			0x408
 245#define TPS6594_REG_WD_THR_CFG				0x409
 246#define TPS6594_REG_DWD_FAIL_CNT_REG			0x40a
 247
 248/* BUCKX_CTRL register field definition */
 249#define TPS6594_BIT_BUCK_EN				BIT(0)
 250#define TPS6594_BIT_BUCK_FPWM				BIT(1)
 251#define TPS6594_BIT_BUCK_FPWM_MP			BIT(2)
 252#define TPS6594_BIT_BUCK_VSEL				BIT(3)
 253#define TPS6594_BIT_BUCK_VMON_EN			BIT(4)
 254#define TPS6594_BIT_BUCK_PLDN				BIT(5)
 255#define TPS6594_BIT_BUCK_RV_SEL				BIT(7)
 256
 257/* TPS6594 BUCKX_CONF register field definition */
 258#define TPS6594_MASK_BUCK_SLEW_RATE			GENMASK(2, 0)
 259#define TPS6594_MASK_BUCK_ILIM				GENMASK(5, 3)
 260
 261/* TPS65224 BUCKX_CONF register field definition */
 262#define TPS65224_MASK_BUCK_SLEW_RATE			GENMASK(1, 0)
 263
 264/* TPS6594 BUCKX_PG_WINDOW register field definition */
 265#define TPS6594_MASK_BUCK_OV_THR			GENMASK(2, 0)
 266#define TPS6594_MASK_BUCK_UV_THR			GENMASK(5, 3)
 267
 268/* TPS65224 BUCKX_PG_WINDOW register field definition */
 269#define TPS65224_MASK_BUCK_VMON_THR			GENMASK(1, 0)
 270
 271/* TPS6594 BUCKX_VOUT register field definition */
 272#define TPS6594_MASK_BUCKS_VSET				GENMASK(7, 0)
 273
 274/* TPS65224 BUCKX_VOUT register field definition */
 275#define TPS65224_MASK_BUCK1_VSET			GENMASK(7, 0)
 276#define TPS65224_MASK_BUCKS_VSET			GENMASK(6, 0)
 277
 278/* LDOX_CTRL register field definition */
 279#define TPS6594_BIT_LDO_EN				BIT(0)
 280#define TPS6594_BIT_LDO_SLOW_RAMP			BIT(1)
 281#define TPS6594_BIT_LDO_VMON_EN				BIT(4)
 282#define TPS6594_MASK_LDO_PLDN				GENMASK(6, 5)
 283#define TPS6594_BIT_LDO_RV_SEL				BIT(7)
 284#define TPS65224_BIT_LDO_DISCHARGE_EN			BIT(5)
 285
 286/* LDORTC_CTRL register field definition */
 287#define TPS6594_BIT_LDORTC_DIS				BIT(0)
 288
 289/* LDOX_VOUT register field definition */
 290#define TPS6594_MASK_LDO123_VSET			GENMASK(6, 1)
 291#define TPS6594_MASK_LDO4_VSET				GENMASK(6, 0)
 292#define TPS6594_BIT_LDO_BYPASS				BIT(7)
 293
 294/* LDOX_PG_WINDOW register field definition */
 295#define TPS6594_MASK_LDO_OV_THR				GENMASK(2, 0)
 296#define TPS6594_MASK_LDO_UV_THR				GENMASK(5, 3)
 297
 298/* LDOX_PG_WINDOW register field definition */
 299#define TPS65224_MASK_LDO_VMON_THR			GENMASK(1, 0)
 300
 301/* VCCA_VMON_CTRL register field definition */
 302#define TPS6594_BIT_VMON_EN				BIT(0)
 303#define TPS6594_BIT_VMON1_EN				BIT(1)
 304#define TPS6594_BIT_VMON1_RV_SEL			BIT(2)
 305#define TPS6594_BIT_VMON2_EN				BIT(3)
 306#define TPS6594_BIT_VMON2_RV_SEL			BIT(4)
 307#define TPS6594_BIT_VMON_DEGLITCH_SEL			BIT(5)
 308#define TPS65224_BIT_VMON_DEGLITCH_SEL			GENMASK(7, 5)
 309
 310/* VCCA_PG_WINDOW register field definition */
 311#define TPS6594_MASK_VCCA_OV_THR			GENMASK(2, 0)
 312#define TPS6594_MASK_VCCA_UV_THR			GENMASK(5, 3)
 313#define TPS65224_MASK_VCCA_VMON_THR			GENMASK(1, 0)
 314#define TPS6594_BIT_VCCA_PG_SET				BIT(6)
 315
 316/* VMONX_PG_WINDOW register field definition */
 317#define TPS6594_MASK_VMONX_OV_THR			GENMASK(2, 0)
 318#define TPS6594_MASK_VMONX_UV_THR			GENMASK(5, 3)
 319#define TPS6594_BIT_VMONX_RANGE				BIT(6)
 320
 321/* VMONX_PG_WINDOW register field definition */
 322#define TPS65224_MASK_VMONX_THR				GENMASK(1, 0)
 323
 324/* GPIOX_CONF register field definition */
 325#define TPS6594_BIT_GPIO_DIR				BIT(0)
 326#define TPS6594_BIT_GPIO_OD				BIT(1)
 327#define TPS6594_BIT_GPIO_PU_SEL				BIT(2)
 328#define TPS6594_BIT_GPIO_PU_PD_EN			BIT(3)
 329#define TPS6594_BIT_GPIO_DEGLITCH_EN			BIT(4)
 330#define TPS6594_MASK_GPIO_SEL				GENMASK(7, 5)
 331#define TPS65224_MASK_GPIO_SEL				GENMASK(6, 5)
 332#define TPS65224_MASK_GPIO_SEL_GPIO6			GENMASK(7, 5)
 333
 334/* NPWRON_CONF register field definition */
 335#define TPS6594_BIT_NRSTOUT_OD				BIT(0)
 336#define TPS6594_BIT_ENABLE_PU_SEL			BIT(2)
 337#define TPS6594_BIT_ENABLE_PU_PD_EN			BIT(3)
 338#define TPS6594_BIT_ENABLE_DEGLITCH_EN			BIT(4)
 339#define TPS6594_BIT_ENABLE_POL				BIT(5)
 340#define TPS6594_MASK_NPWRON_SEL				GENMASK(7, 6)
 341
 342/* POWER_ON_CONFIG register field definition */
 343#define TPS65224_BIT_NINT_ENDRV_PU_SEL			BIT(0)
 344#define TPS65224_BIT_NINT_ENDRV_SEL			BIT(1)
 345#define TPS65224_BIT_EN_PB_DEGL				BIT(5)
 346#define TPS65224_MASK_EN_PB_VSENSE_CONFIG		GENMASK(7, 6)
 347
 348/* GPIO_OUT_X register field definition */
 349#define TPS6594_BIT_GPIOX_OUT(gpio_inst)		BIT((gpio_inst) % 8)
 350
 351/* GPIO_IN_X register field definition */
 352#define TPS6594_BIT_GPIOX_IN(gpio_inst)			BIT((gpio_inst) % 8)
 353#define TPS6594_BIT_NPWRON_IN				BIT(3)
 354
 355/* GPIO_OUT_X register field definition */
 356#define TPS65224_BIT_GPIOX_OUT(gpio_inst)		BIT((gpio_inst))
 357
 358/* GPIO_IN_X register field definition */
 359#define TPS65224_BIT_GPIOX_IN(gpio_inst)		BIT((gpio_inst))
 360
 361/* RAIL_SEL_1 register field definition */
 362#define TPS6594_MASK_BUCK1_GRP_SEL			GENMASK(1, 0)
 363#define TPS6594_MASK_BUCK2_GRP_SEL			GENMASK(3, 2)
 364#define TPS6594_MASK_BUCK3_GRP_SEL			GENMASK(5, 4)
 365#define TPS6594_MASK_BUCK4_GRP_SEL			GENMASK(7, 6)
 366
 367/* RAIL_SEL_2 register field definition */
 368#define TPS6594_MASK_BUCK5_GRP_SEL			GENMASK(1, 0)
 369#define TPS6594_MASK_LDO1_GRP_SEL			GENMASK(3, 2)
 370#define TPS6594_MASK_LDO2_GRP_SEL			GENMASK(5, 4)
 371#define TPS6594_MASK_LDO3_GRP_SEL			GENMASK(7, 6)
 372
 373/* RAIL_SEL_3 register field definition */
 374#define TPS6594_MASK_LDO4_GRP_SEL			GENMASK(1, 0)
 375#define TPS6594_MASK_VCCA_GRP_SEL			GENMASK(3, 2)
 376#define TPS6594_MASK_VMON1_GRP_SEL			GENMASK(5, 4)
 377#define TPS6594_MASK_VMON2_GRP_SEL			GENMASK(7, 6)
 378
 379/* FSM_TRIG_SEL_1 register field definition */
 380#define TPS6594_MASK_MCU_RAIL_TRIG			GENMASK(1, 0)
 381#define TPS6594_MASK_SOC_RAIL_TRIG			GENMASK(3, 2)
 382#define TPS6594_MASK_OTHER_RAIL_TRIG			GENMASK(5, 4)
 383#define TPS6594_MASK_SEVERE_ERR_TRIG			GENMASK(7, 6)
 384
 385/* FSM_TRIG_SEL_2 register field definition */
 386#define TPS6594_MASK_MODERATE_ERR_TRIG			GENMASK(1, 0)
 387
 388/* FSM_TRIG_MASK_X register field definition */
 389#define TPS6594_BIT_GPIOX_FSM_MASK(gpio_inst)		BIT(((gpio_inst) << 1) % 8)
 390#define TPS6594_BIT_GPIOX_FSM_MASK_POL(gpio_inst)	BIT(((gpio_inst) << 1) % 8 + 1)
 391
 392#define TPS65224_BIT_GPIOX_FSM_MASK(gpio_inst)		BIT(((gpio_inst) << 1) % 6)
 393#define TPS65224_BIT_GPIOX_FSM_MASK_POL(gpio_inst)	BIT(((gpio_inst) << 1) % 6 + 1)
 394
 395/* MASK_BUCKX register field definition */
 396#define TPS6594_BIT_BUCKX_OV_MASK(buck_inst)		BIT(((buck_inst) << 2) % 8)
 397#define TPS6594_BIT_BUCKX_UV_MASK(buck_inst)		BIT(((buck_inst) << 2) % 8 + 1)
 398#define TPS6594_BIT_BUCKX_ILIM_MASK(buck_inst)		BIT(((buck_inst) << 2) % 8 + 3)
 399
 400/* MASK_LDOX register field definition */
 401#define TPS6594_BIT_LDOX_OV_MASK(ldo_inst)		BIT(((ldo_inst) << 2) % 8)
 402#define TPS6594_BIT_LDOX_UV_MASK(ldo_inst)		BIT(((ldo_inst) << 2) % 8 + 1)
 403#define TPS6594_BIT_LDOX_ILIM_MASK(ldo_inst)		BIT(((ldo_inst) << 2) % 8 + 3)
 404
 405/* MASK_VMON register field definition */
 406#define TPS6594_BIT_VCCA_OV_MASK			BIT(0)
 407#define TPS6594_BIT_VCCA_UV_MASK			BIT(1)
 408#define TPS6594_BIT_VMON1_OV_MASK			BIT(2)
 409#define TPS6594_BIT_VMON1_UV_MASK			BIT(3)
 410#define TPS6594_BIT_VMON2_OV_MASK			BIT(5)
 411#define TPS6594_BIT_VMON2_UV_MASK			BIT(6)
 412
 413/* MASK_BUCK Register field definition */
 414#define TPS65224_BIT_BUCK1_UVOV_MASK			BIT(0)
 415#define TPS65224_BIT_BUCK2_UVOV_MASK			BIT(1)
 416#define TPS65224_BIT_BUCK3_UVOV_MASK			BIT(2)
 417#define TPS65224_BIT_BUCK4_UVOV_MASK			BIT(4)
 418
 419/* MASK_LDO_VMON register field definition */
 420#define TPS65224_BIT_LDO1_UVOV_MASK			BIT(0)
 421#define TPS65224_BIT_LDO2_UVOV_MASK			BIT(1)
 422#define TPS65224_BIT_LDO3_UVOV_MASK			BIT(2)
 423#define TPS65224_BIT_VCCA_UVOV_MASK			BIT(4)
 424#define TPS65224_BIT_VMON1_UVOV_MASK			BIT(5)
 425#define TPS65224_BIT_VMON2_UVOV_MASK			BIT(6)
 426
 427/* MASK_GPIOX register field definition */
 428#define TPS6594_BIT_GPIOX_FALL_MASK(gpio_inst)		BIT((gpio_inst) < 8 ? \
 429							    (gpio_inst) : (gpio_inst) % 8)
 430#define TPS6594_BIT_GPIOX_RISE_MASK(gpio_inst)		BIT((gpio_inst) < 8 ? \
 431							    (gpio_inst) : (gpio_inst) % 8 + 3)
 432/* MASK_GPIOX register field definition */
 433#define TPS65224_BIT_GPIOX_FALL_MASK(gpio_inst)		BIT((gpio_inst))
 434#define TPS65224_BIT_GPIOX_RISE_MASK(gpio_inst)		BIT((gpio_inst))
 435
 436/* MASK_STARTUP register field definition */
 437#define TPS6594_BIT_NPWRON_START_MASK			BIT(0)
 438#define TPS6594_BIT_ENABLE_MASK				BIT(1)
 439#define TPS6594_BIT_FSD_MASK				BIT(4)
 440#define TPS6594_BIT_SOFT_REBOOT_MASK			BIT(5)
 441#define TPS65224_BIT_VSENSE_MASK			BIT(0)
 442#define TPS65224_BIT_PB_SHORT_MASK			BIT(2)
 443
 444/* MASK_MISC register field definition */
 445#define TPS6594_BIT_BIST_PASS_MASK			BIT(0)
 446#define TPS6594_BIT_EXT_CLK_MASK			BIT(1)
 447#define TPS65224_BIT_REG_UNLOCK_MASK			BIT(2)
 448#define TPS6594_BIT_TWARN_MASK				BIT(3)
 449#define TPS65224_BIT_PB_LONG_MASK			BIT(4)
 450#define TPS65224_BIT_PB_FALL_MASK			BIT(5)
 451#define TPS65224_BIT_PB_RISE_MASK			BIT(6)
 452#define TPS65224_BIT_ADC_CONV_READY_MASK		BIT(7)
 453
 454/* MASK_MODERATE_ERR register field definition */
 455#define TPS6594_BIT_BIST_FAIL_MASK			BIT(1)
 456#define TPS6594_BIT_REG_CRC_ERR_MASK			BIT(2)
 457#define TPS6594_BIT_SPMI_ERR_MASK			BIT(4)
 458#define TPS6594_BIT_NPWRON_LONG_MASK			BIT(5)
 459#define TPS6594_BIT_NINT_READBACK_MASK			BIT(6)
 460#define TPS6594_BIT_NRSTOUT_READBACK_MASK		BIT(7)
 461
 462/* MASK_FSM_ERR register field definition */
 463#define TPS6594_BIT_IMM_SHUTDOWN_MASK			BIT(0)
 464#define TPS6594_BIT_ORD_SHUTDOWN_MASK			BIT(1)
 465#define TPS6594_BIT_MCU_PWR_ERR_MASK			BIT(2)
 466#define TPS6594_BIT_SOC_PWR_ERR_MASK			BIT(3)
 467#define TPS65224_BIT_COMM_ERR_MASK			BIT(4)
 468#define TPS65224_BIT_I2C2_ERR_MASK			BIT(5)
 469
 470/* MASK_COMM_ERR register field definition */
 471#define TPS6594_BIT_COMM_FRM_ERR_MASK			BIT(0)
 472#define TPS6594_BIT_COMM_CRC_ERR_MASK			BIT(1)
 473#define TPS6594_BIT_COMM_ADR_ERR_MASK			BIT(3)
 474#define TPS6594_BIT_I2C2_CRC_ERR_MASK			BIT(5)
 475#define TPS6594_BIT_I2C2_ADR_ERR_MASK			BIT(7)
 476
 477/* MASK_READBACK_ERR register field definition */
 478#define TPS6594_BIT_EN_DRV_READBACK_MASK		BIT(0)
 479#define TPS6594_BIT_NRSTOUT_SOC_READBACK_MASK		BIT(3)
 480
 481/* MASK_ESM register field definition */
 482#define TPS6594_BIT_ESM_SOC_PIN_MASK			BIT(0)
 483#define TPS6594_BIT_ESM_SOC_FAIL_MASK			BIT(1)
 484#define TPS6594_BIT_ESM_SOC_RST_MASK			BIT(2)
 485#define TPS6594_BIT_ESM_MCU_PIN_MASK			BIT(3)
 486#define TPS6594_BIT_ESM_MCU_FAIL_MASK			BIT(4)
 487#define TPS6594_BIT_ESM_MCU_RST_MASK			BIT(5)
 488
 489/* INT_TOP register field definition */
 490#define TPS6594_BIT_BUCK_INT				BIT(0)
 491#define TPS6594_BIT_LDO_VMON_INT			BIT(1)
 492#define TPS6594_BIT_GPIO_INT				BIT(2)
 493#define TPS6594_BIT_STARTUP_INT				BIT(3)
 494#define TPS6594_BIT_MISC_INT				BIT(4)
 495#define TPS6594_BIT_MODERATE_ERR_INT			BIT(5)
 496#define TPS6594_BIT_SEVERE_ERR_INT			BIT(6)
 497#define TPS6594_BIT_FSM_ERR_INT				BIT(7)
 498
 499/* INT_BUCK register field definition */
 500#define TPS6594_BIT_BUCK1_2_INT				BIT(0)
 501#define TPS6594_BIT_BUCK3_4_INT				BIT(1)
 502#define TPS6594_BIT_BUCK5_INT				BIT(2)
 503
 504/* INT_BUCK register field definition */
 505#define TPS65224_BIT_BUCK1_UVOV_INT			BIT(0)
 506#define TPS65224_BIT_BUCK2_UVOV_INT			BIT(1)
 507#define TPS65224_BIT_BUCK3_UVOV_INT			BIT(2)
 508#define TPS65224_BIT_BUCK4_UVOV_INT			BIT(3)
 509
 510/* INT_BUCKX register field definition */
 511#define TPS6594_BIT_BUCKX_OV_INT(buck_inst)		BIT(((buck_inst) << 2) % 8)
 512#define TPS6594_BIT_BUCKX_UV_INT(buck_inst)		BIT(((buck_inst) << 2) % 8 + 1)
 513#define TPS6594_BIT_BUCKX_SC_INT(buck_inst)		BIT(((buck_inst) << 2) % 8 + 2)
 514#define TPS6594_BIT_BUCKX_ILIM_INT(buck_inst)		BIT(((buck_inst) << 2) % 8 + 3)
 515
 516/* INT_LDO_VMON register field definition */
 517#define TPS6594_BIT_LDO1_2_INT				BIT(0)
 518#define TPS6594_BIT_LDO3_4_INT				BIT(1)
 519#define TPS6594_BIT_VCCA_INT				BIT(4)
 520
 521/* INT_LDO_VMON register field definition */
 522#define TPS65224_BIT_LDO1_UVOV_INT			BIT(0)
 523#define TPS65224_BIT_LDO2_UVOV_INT			BIT(1)
 524#define TPS65224_BIT_LDO3_UVOV_INT			BIT(2)
 525#define TPS65224_BIT_VCCA_UVOV_INT			BIT(4)
 526#define TPS65224_BIT_VMON1_UVOV_INT			BIT(5)
 527#define TPS65224_BIT_VMON2_UVOV_INT			BIT(6)
 528
 529/* INT_LDOX register field definition */
 530#define TPS6594_BIT_LDOX_OV_INT(ldo_inst)		BIT(((ldo_inst) << 2) % 8)
 531#define TPS6594_BIT_LDOX_UV_INT(ldo_inst)		BIT(((ldo_inst) << 2) % 8 + 1)
 532#define TPS6594_BIT_LDOX_SC_INT(ldo_inst)		BIT(((ldo_inst) << 2) % 8 + 2)
 533#define TPS6594_BIT_LDOX_ILIM_INT(ldo_inst)		BIT(((ldo_inst) << 2) % 8 + 3)
 534
 535/* INT_VMON register field definition */
 536#define TPS6594_BIT_VCCA_OV_INT				BIT(0)
 537#define TPS6594_BIT_VCCA_UV_INT				BIT(1)
 538#define TPS6594_BIT_VMON1_OV_INT			BIT(2)
 539#define TPS6594_BIT_VMON1_UV_INT			BIT(3)
 540#define TPS6594_BIT_VMON1_RV_INT			BIT(4)
 541#define TPS6594_BIT_VMON2_OV_INT			BIT(5)
 542#define TPS6594_BIT_VMON2_UV_INT			BIT(6)
 543#define TPS6594_BIT_VMON2_RV_INT			BIT(7)
 544
 545/* INT_GPIO register field definition */
 546#define TPS6594_BIT_GPIO9_INT				BIT(0)
 547#define TPS6594_BIT_GPIO10_INT				BIT(1)
 548#define TPS6594_BIT_GPIO11_INT				BIT(2)
 549#define TPS6594_BIT_GPIO1_8_INT				BIT(3)
 550
 551/* INT_GPIOX register field definition */
 552#define TPS6594_BIT_GPIOX_INT(gpio_inst)		BIT(gpio_inst)
 553
 554/* INT_GPIO register field definition */
 555#define TPS65224_BIT_GPIO1_INT				BIT(0)
 556#define TPS65224_BIT_GPIO2_INT				BIT(1)
 557#define TPS65224_BIT_GPIO3_INT				BIT(2)
 558#define TPS65224_BIT_GPIO4_INT				BIT(3)
 559#define TPS65224_BIT_GPIO5_INT				BIT(4)
 560#define TPS65224_BIT_GPIO6_INT				BIT(5)
 561
 562/* INT_STARTUP register field definition */
 563#define TPS6594_BIT_NPWRON_START_INT			BIT(0)
 564#define TPS65224_BIT_VSENSE_INT				BIT(0)
 565#define TPS6594_BIT_ENABLE_INT				BIT(1)
 566#define TPS6594_BIT_RTC_INT				BIT(2)
 567#define TPS65224_BIT_PB_SHORT_INT			BIT(2)
 568#define TPS6594_BIT_FSD_INT				BIT(4)
 569#define TPS6594_BIT_SOFT_REBOOT_INT			BIT(5)
 570
 571/* INT_MISC register field definition */
 572#define TPS6594_BIT_BIST_PASS_INT			BIT(0)
 573#define TPS6594_BIT_EXT_CLK_INT				BIT(1)
 574#define TPS65224_BIT_REG_UNLOCK_INT			BIT(2)
 575#define TPS6594_BIT_TWARN_INT				BIT(3)
 576#define TPS65224_BIT_PB_LONG_INT			BIT(4)
 577#define TPS65224_BIT_PB_FALL_INT			BIT(5)
 578#define TPS65224_BIT_PB_RISE_INT			BIT(6)
 579#define TPS65224_BIT_ADC_CONV_READY_INT			BIT(7)
 580
 581/* INT_MODERATE_ERR register field definition */
 582#define TPS6594_BIT_TSD_ORD_INT				BIT(0)
 583#define TPS6594_BIT_BIST_FAIL_INT			BIT(1)
 584#define TPS6594_BIT_REG_CRC_ERR_INT			BIT(2)
 585#define TPS6594_BIT_RECOV_CNT_INT			BIT(3)
 586#define TPS6594_BIT_SPMI_ERR_INT			BIT(4)
 587#define TPS6594_BIT_NPWRON_LONG_INT			BIT(5)
 588#define TPS6594_BIT_NINT_READBACK_INT			BIT(6)
 589#define TPS6594_BIT_NRSTOUT_READBACK_INT		BIT(7)
 590
 591/* INT_SEVERE_ERR register field definition */
 592#define TPS6594_BIT_TSD_IMM_INT				BIT(0)
 593#define TPS6594_BIT_VCCA_OVP_INT			BIT(1)
 594#define TPS6594_BIT_PFSM_ERR_INT			BIT(2)
 595#define TPS65224_BIT_BG_XMON_INT			BIT(3)
 596
 597/* INT_FSM_ERR register field definition */
 598#define TPS6594_BIT_IMM_SHUTDOWN_INT			BIT(0)
 599#define TPS6594_BIT_ORD_SHUTDOWN_INT			BIT(1)
 600#define TPS6594_BIT_MCU_PWR_ERR_INT			BIT(2)
 601#define TPS6594_BIT_SOC_PWR_ERR_INT			BIT(3)
 602#define TPS6594_BIT_COMM_ERR_INT			BIT(4)
 603#define TPS6594_BIT_READBACK_ERR_INT			BIT(5)
 604#define TPS65224_BIT_I2C2_ERR_INT			BIT(5)
 605#define TPS6594_BIT_ESM_INT				BIT(6)
 606#define TPS6594_BIT_WD_INT				BIT(7)
 607
 608/* INT_COMM_ERR register field definition */
 609#define TPS6594_BIT_COMM_FRM_ERR_INT			BIT(0)
 610#define TPS6594_BIT_COMM_CRC_ERR_INT			BIT(1)
 611#define TPS6594_BIT_COMM_ADR_ERR_INT			BIT(3)
 612#define TPS6594_BIT_I2C2_CRC_ERR_INT			BIT(5)
 613#define TPS6594_BIT_I2C2_ADR_ERR_INT			BIT(7)
 614
 615/* INT_READBACK_ERR register field definition */
 616#define TPS6594_BIT_EN_DRV_READBACK_INT			BIT(0)
 617#define TPS6594_BIT_NRSTOUT_SOC_READBACK_INT		BIT(3)
 618
 619/* INT_ESM register field definition */
 620#define TPS6594_BIT_ESM_SOC_PIN_INT			BIT(0)
 621#define TPS6594_BIT_ESM_SOC_FAIL_INT			BIT(1)
 622#define TPS6594_BIT_ESM_SOC_RST_INT			BIT(2)
 623#define TPS6594_BIT_ESM_MCU_PIN_INT			BIT(3)
 624#define TPS6594_BIT_ESM_MCU_FAIL_INT			BIT(4)
 625#define TPS6594_BIT_ESM_MCU_RST_INT			BIT(5)
 626
 627/* STAT_BUCKX register field definition */
 628#define TPS6594_BIT_BUCKX_OV_STAT(buck_inst)		BIT(((buck_inst) << 2) % 8)
 629#define TPS6594_BIT_BUCKX_UV_STAT(buck_inst)		BIT(((buck_inst) << 2) % 8 + 1)
 630#define TPS6594_BIT_BUCKX_ILIM_STAT(buck_inst)		BIT(((buck_inst) << 2) % 8 + 3)
 631
 632/* STAT_LDOX register field definition */
 633#define TPS6594_BIT_LDOX_OV_STAT(ldo_inst)		BIT(((ldo_inst) << 2) % 8)
 634#define TPS6594_BIT_LDOX_UV_STAT(ldo_inst)		BIT(((ldo_inst) << 2) % 8 + 1)
 635#define TPS6594_BIT_LDOX_ILIM_STAT(ldo_inst)		BIT(((ldo_inst) << 2) % 8 + 3)
 636
 637/* STAT_VMON register field definition */
 638#define TPS6594_BIT_VCCA_OV_STAT			BIT(0)
 639#define TPS6594_BIT_VCCA_UV_STAT			BIT(1)
 640#define TPS6594_BIT_VMON1_OV_STAT			BIT(2)
 641#define TPS6594_BIT_VMON1_UV_STAT			BIT(3)
 642#define TPS6594_BIT_VMON2_OV_STAT			BIT(5)
 643#define TPS6594_BIT_VMON2_UV_STAT			BIT(6)
 644
 645/* STAT_LDO_VMON register field definition */
 646#define TPS65224_BIT_LDO1_UVOV_STAT			BIT(0)
 647#define TPS65224_BIT_LDO2_UVOV_STAT			BIT(1)
 648#define TPS65224_BIT_LDO3_UVOV_STAT			BIT(2)
 649#define TPS65224_BIT_VCCA_UVOV_STAT			BIT(4)
 650#define TPS65224_BIT_VMON1_UVOV_STAT			BIT(5)
 651#define TPS65224_BIT_VMON2_UVOV_STAT			BIT(6)
 652
 653/* STAT_STARTUP register field definition */
 654#define TPS65224_BIT_VSENSE_STAT			BIT(0)
 655#define TPS6594_BIT_ENABLE_STAT				BIT(1)
 656#define TPS65224_BIT_PB_LEVEL_STAT			BIT(2)
 657
 658/* STAT_MISC register field definition */
 659#define TPS6594_BIT_EXT_CLK_STAT			BIT(1)
 660#define TPS6594_BIT_TWARN_STAT				BIT(3)
 661
 662/* STAT_MODERATE_ERR register field definition */
 663#define TPS6594_BIT_TSD_ORD_STAT			BIT(0)
 664
 665/* STAT_SEVERE_ERR register field definition */
 666#define TPS6594_BIT_TSD_IMM_STAT			BIT(0)
 667#define TPS6594_BIT_VCCA_OVP_STAT			BIT(1)
 668#define TPS65224_BIT_BG_XMON_STAT			BIT(3)
 669
 670/* STAT_READBACK_ERR register field definition */
 671#define TPS6594_BIT_EN_DRV_READBACK_STAT		BIT(0)
 672#define TPS6594_BIT_NINT_READBACK_STAT			BIT(1)
 673#define TPS6594_BIT_NRSTOUT_READBACK_STAT		BIT(2)
 674#define TPS6594_BIT_NRSTOUT_SOC_READBACK_STAT		BIT(3)
 675
 676/* PGOOD_SEL_1 register field definition */
 677#define TPS6594_MASK_PGOOD_SEL_BUCK1			GENMASK(1, 0)
 678#define TPS6594_MASK_PGOOD_SEL_BUCK2			GENMASK(3, 2)
 679#define TPS6594_MASK_PGOOD_SEL_BUCK3			GENMASK(5, 4)
 680#define TPS6594_MASK_PGOOD_SEL_BUCK4			GENMASK(7, 6)
 681
 682/* PGOOD_SEL_2 register field definition */
 683#define TPS6594_MASK_PGOOD_SEL_BUCK5			GENMASK(1, 0)
 684
 685/* PGOOD_SEL_3 register field definition */
 686#define TPS6594_MASK_PGOOD_SEL_LDO1			GENMASK(1, 0)
 687#define TPS6594_MASK_PGOOD_SEL_LDO2			GENMASK(3, 2)
 688#define TPS6594_MASK_PGOOD_SEL_LDO3			GENMASK(5, 4)
 689#define TPS6594_MASK_PGOOD_SEL_LDO4			GENMASK(7, 6)
 690
 691/* PGOOD_SEL_4 register field definition */
 692#define TPS6594_BIT_PGOOD_SEL_VCCA			BIT(0)
 693#define TPS6594_BIT_PGOOD_SEL_VMON1			BIT(1)
 694#define TPS6594_BIT_PGOOD_SEL_VMON2			BIT(2)
 695#define TPS6594_BIT_PGOOD_SEL_TDIE_WARN			BIT(3)
 696#define TPS6594_BIT_PGOOD_SEL_NRSTOUT			BIT(4)
 697#define TPS6594_BIT_PGOOD_SEL_NRSTOUT_SOC		BIT(5)
 698#define TPS6594_BIT_PGOOD_POL				BIT(6)
 699#define TPS6594_BIT_PGOOD_WINDOW			BIT(7)
 700
 701/* PLL_CTRL register field definition */
 702#define TPS6594_MASK_EXT_CLK_FREQ			GENMASK(1, 0)
 703
 704/* CONFIG_1 register field definition */
 705#define TPS6594_BIT_TWARN_LEVEL				BIT(0)
 706#define TPS6594_BIT_TSD_ORD_LEVEL			BIT(1)
 707#define TPS6594_BIT_I2C1_HS				BIT(3)
 708#define TPS6594_BIT_I2C2_HS				BIT(4)
 709#define TPS6594_BIT_EN_ILIM_FSM_CTRL			BIT(5)
 710#define TPS6594_BIT_NSLEEP1_MASK			BIT(6)
 711#define TPS6594_BIT_NSLEEP2_MASK			BIT(7)
 712
 713/* CONFIG_2 register field definition */
 714#define TPS6594_BIT_BB_CHARGER_EN			BIT(0)
 715#define TPS6594_BIT_BB_ICHR				BIT(1)
 716#define TPS6594_MASK_BB_VEOC				GENMASK(3, 2)
 717#define TPS65224_BIT_I2C1_SPI_CRC_EN			BIT(4)
 718#define TPS65224_BIT_I2C2_CRC_EN			BIT(5)
 719#define TPS6594_BB_EOC_RDY				BIT(7)
 720
 721/* ENABLE_DRV_REG register field definition */
 722#define TPS6594_BIT_ENABLE_DRV				BIT(0)
 723
 724/* MISC_CTRL register field definition */
 725#define TPS6594_BIT_NRSTOUT				BIT(0)
 726#define TPS6594_BIT_NRSTOUT_SOC				BIT(1)
 727#define TPS6594_BIT_LPM_EN				BIT(2)
 728#define TPS6594_BIT_CLKMON_EN				BIT(3)
 729#define TPS6594_BIT_AMUXOUT_EN				BIT(4)
 730#define TPS6594_BIT_SEL_EXT_CLK				BIT(5)
 731#define TPS6594_MASK_SYNCCLKOUT_FREQ_SEL		GENMASK(7, 6)
 732
 733/* ENABLE_DRV_STAT register field definition */
 734#define TPS6594_BIT_EN_DRV_IN				BIT(0)
 735#define TPS6594_BIT_NRSTOUT_IN				BIT(1)
 736#define TPS6594_BIT_NRSTOUT_SOC_IN			BIT(2)
 737#define TPS6594_BIT_FORCE_EN_DRV_LOW			BIT(3)
 738#define TPS6594_BIT_SPMI_LPM_EN				BIT(4)
 739#define TPS65224_BIT_TSD_DISABLE			BIT(5)
 740
 741/* RECOV_CNT_REG_1 register field definition */
 742#define TPS6594_MASK_RECOV_CNT				GENMASK(3, 0)
 743
 744/* RECOV_CNT_REG_2 register field definition */
 745#define TPS6594_MASK_RECOV_CNT_THR			GENMASK(3, 0)
 746#define TPS6594_BIT_RECOV_CNT_CLR			BIT(4)
 747
 748/* FSM_I2C_TRIGGERS register field definition */
 749#define TPS6594_BIT_TRIGGER_I2C(bit)			BIT(bit)
 750
 751/* FSM_NSLEEP_TRIGGERS register field definition */
 752#define TPS6594_BIT_NSLEEP1B				BIT(0)
 753#define TPS6594_BIT_NSLEEP2B				BIT(1)
 754
 755/* BUCK_RESET_REG register field definition */
 756#define TPS6594_BIT_BUCKX_RESET(buck_inst)		BIT(buck_inst)
 757
 758/* SPREAD_SPECTRUM_1 register field definition */
 759#define TPS6594_MASK_SS_DEPTH				GENMASK(1, 0)
 760#define TPS6594_BIT_SS_EN				BIT(2)
 761
 762/* FREQ_SEL register field definition */
 763#define TPS6594_BIT_BUCKX_FREQ_SEL(buck_inst)		BIT(buck_inst)
 764
 765/* FSM_STEP_SIZE register field definition */
 766#define TPS6594_MASK_PFSM_DELAY_STEP			GENMASK(4, 0)
 767
 768/* LDO_RV_TIMEOUT_REG_1 register field definition */
 769#define TPS6594_MASK_LDO1_RV_TIMEOUT			GENMASK(3, 0)
 770#define TPS6594_MASK_LDO2_RV_TIMEOUT			GENMASK(7, 4)
 771
 772/* LDO_RV_TIMEOUT_REG_2 register field definition */
 773#define TPS6594_MASK_LDO3_RV_TIMEOUT			GENMASK(3, 0)
 774#define TPS6594_MASK_LDO4_RV_TIMEOUT			GENMASK(7, 4)
 775
 776/* USER_SPARE_REGS register field definition */
 777#define TPS6594_BIT_USER_SPARE(bit)			BIT(bit)
 778
 779/* ESM_MCU_START_REG register field definition */
 780#define TPS6594_BIT_ESM_MCU_START			BIT(0)
 781
 782/* ESM_MCU_MODE_CFG register field definition */
 783#define TPS6594_MASK_ESM_MCU_ERR_CNT_TH			GENMASK(3, 0)
 784#define TPS6594_BIT_ESM_MCU_ENDRV			BIT(5)
 785#define TPS6594_BIT_ESM_MCU_EN				BIT(6)
 786#define TPS6594_BIT_ESM_MCU_MODE			BIT(7)
 787
 788/* ESM_MCU_ERR_CNT_REG register field definition */
 789#define TPS6594_MASK_ESM_MCU_ERR_CNT			GENMASK(4, 0)
 790
 791/* ESM_SOC_START_REG register field definition */
 792#define TPS6594_BIT_ESM_SOC_START			BIT(0)
 793
 794/* ESM_MCU_START_REG register field definition */
 795#define TPS65224_BIT_ESM_MCU_START			BIT(0)
 796
 797/* ESM_SOC_MODE_CFG register field definition */
 798#define TPS6594_MASK_ESM_SOC_ERR_CNT_TH			GENMASK(3, 0)
 799#define TPS6594_BIT_ESM_SOC_ENDRV			BIT(5)
 800#define TPS6594_BIT_ESM_SOC_EN				BIT(6)
 801#define TPS6594_BIT_ESM_SOC_MODE			BIT(7)
 802
 803/* ESM_MCU_MODE_CFG register field definition */
 804#define TPS65224_MASK_ESM_MCU_ERR_CNT_TH		GENMASK(3, 0)
 805#define TPS65224_BIT_ESM_MCU_ENDRV			BIT(5)
 806#define TPS65224_BIT_ESM_MCU_EN				BIT(6)
 807#define TPS65224_BIT_ESM_MCU_MODE			BIT(7)
 808
 809/* ESM_SOC_ERR_CNT_REG register field definition */
 810#define TPS6594_MASK_ESM_SOC_ERR_CNT			GENMASK(4, 0)
 811
 812/* ESM_MCU_ERR_CNT_REG register field definition */
 813#define TPS6594_MASK_ESM_MCU_ERR_CNT			GENMASK(4, 0)
 814
 815/* REGISTER_LOCK register field definition */
 816#define TPS6594_BIT_REGISTER_LOCK_STATUS		BIT(0)
 817
 818/* VMON_CONF register field definition */
 819#define TPS6594_MASK_VMON1_SLEW_RATE			GENMASK(2, 0)
 820#define TPS6594_MASK_VMON2_SLEW_RATE			GENMASK(5, 3)
 821
 822/* SRAM_ACCESS_1 Register field definition */
 823#define TPS65224_MASk_SRAM_UNLOCK_SEQ			GENMASK(7, 0)
 824
 825/* SRAM_ACCESS_2 Register field definition */
 826#define TPS65224_BIT_SRAM_WRITE_MODE			BIT(0)
 827#define TPS65224_BIT_OTP_PROG_USER			BIT(1)
 828#define TPS65224_BIT_OTP_PROG_PFSM			BIT(2)
 829#define TPS65224_BIT_OTP_PROG_STATUS			BIT(3)
 830#define TPS65224_BIT_SRAM_UNLOCKED			BIT(6)
 831#define TPS65224_USER_PROG_ALLOWED			BIT(7)
 832
 833/* SRAM_ADDR_CTRL Register field definition */
 834#define TPS65224_MASk_SRAM_SEL				GENMASK(1, 0)
 835
 836/* RECOV_CNT_PFSM_INCR Register field definition */
 837#define TPS65224_BIT_INCREMENT_RECOV_CNT		BIT(0)
 838
 839/* MANUFACTURING_VER Register field definition */
 840#define TPS65224_MASK_SILICON_REV			GENMASK(7, 0)
 841
 842/* CUSTOMER_NVM_ID_REG Register field definition */
 843#define TPS65224_MASK_CUSTOMER_NVM_ID			GENMASK(7, 0)
 844
 845/* SOFT_REBOOT_REG register field definition */
 846#define TPS6594_BIT_SOFT_REBOOT				BIT(0)
 847
 848/* RTC_SECONDS & ALARM_SECONDS register field definition */
 849#define TPS6594_MASK_SECOND_0				GENMASK(3, 0)
 850#define TPS6594_MASK_SECOND_1				GENMASK(6, 4)
 851
 852/* RTC_MINUTES & ALARM_MINUTES register field definition */
 853#define TPS6594_MASK_MINUTE_0				GENMASK(3, 0)
 854#define TPS6594_MASK_MINUTE_1				GENMASK(6, 4)
 855
 856/* RTC_HOURS & ALARM_HOURS register field definition */
 857#define TPS6594_MASK_HOUR_0				GENMASK(3, 0)
 858#define TPS6594_MASK_HOUR_1				GENMASK(5, 4)
 859#define TPS6594_BIT_PM_NAM				BIT(7)
 860
 861/* RTC_DAYS & ALARM_DAYS register field definition */
 862#define TPS6594_MASK_DAY_0				GENMASK(3, 0)
 863#define TPS6594_MASK_DAY_1				GENMASK(5, 4)
 864
 865/* RTC_MONTHS & ALARM_MONTHS register field definition */
 866#define TPS6594_MASK_MONTH_0				GENMASK(3, 0)
 867#define TPS6594_BIT_MONTH_1				BIT(4)
 868
 869/* RTC_YEARS & ALARM_YEARS register field definition */
 870#define TPS6594_MASK_YEAR_0				GENMASK(3, 0)
 871#define TPS6594_MASK_YEAR_1				GENMASK(7, 4)
 872
 873/* RTC_WEEKS register field definition */
 874#define TPS6594_MASK_WEEK				GENMASK(2, 0)
 875
 876/* RTC_CTRL_1 register field definition */
 877#define TPS6594_BIT_STOP_RTC				BIT(0)
 878#define TPS6594_BIT_ROUND_30S				BIT(1)
 879#define TPS6594_BIT_AUTO_COMP				BIT(2)
 880#define TPS6594_BIT_MODE_12_24				BIT(3)
 881#define TPS6594_BIT_SET_32_COUNTER			BIT(5)
 882#define TPS6594_BIT_GET_TIME				BIT(6)
 883#define TPS6594_BIT_RTC_V_OPT				BIT(7)
 884
 885/* RTC_CTRL_2 register field definition */
 886#define TPS6594_BIT_XTAL_EN				BIT(0)
 887#define TPS6594_MASK_XTAL_SEL				GENMASK(2, 1)
 888#define TPS6594_BIT_LP_STANDBY_SEL			BIT(3)
 889#define TPS6594_BIT_FAST_BIST				BIT(4)
 890#define TPS6594_MASK_STARTUP_DEST			GENMASK(6, 5)
 891#define TPS6594_BIT_FIRST_STARTUP_DONE			BIT(7)
 892
 893/* RTC_STATUS register field definition */
 894#define TPS6594_BIT_RUN					BIT(1)
 895#define TPS6594_BIT_TIMER				BIT(5)
 896#define TPS6594_BIT_ALARM				BIT(6)
 897#define TPS6594_BIT_POWER_UP				BIT(7)
 898
 899/* RTC_INTERRUPTS register field definition */
 900#define TPS6594_MASK_EVERY				GENMASK(1, 0)
 901#define TPS6594_BIT_IT_TIMER				BIT(2)
 902#define TPS6594_BIT_IT_ALARM				BIT(3)
 903
 904/* RTC_RESET_STATUS register field definition */
 905#define TPS6594_BIT_RESET_STATUS_RTC			BIT(0)
 906
 907/* SERIAL_IF_CONFIG register field definition */
 908#define TPS6594_BIT_I2C_SPI_SEL				BIT(0)
 909#define TPS6594_BIT_I2C1_SPI_CRC_EN			BIT(1)
 910#define TPS6594_BIT_I2C2_CRC_EN				BIT(2)
 911#define TPS6594_MASK_T_CRC				GENMASK(7, 3)
 912
 913/* ADC_CTRL Register field definition */
 914#define TPS65224_BIT_ADC_START				BIT(0)
 915#define TPS65224_BIT_ADC_CONT_CONV			BIT(1)
 916#define TPS65224_BIT_ADC_THERMAL_SEL			BIT(2)
 917#define TPS65224_BIT_ADC_RDIV_EN			BIT(3)
 918#define TPS65224_BIT_ADC_STATUS				BIT(7)
 919
 920/* ADC_RESULT_REG_1 Register field definition */
 921#define TPS65224_MASK_ADC_RESULT_11_4			GENMASK(7, 0)
 922
 923/* ADC_RESULT_REG_2 Register field definition */
 924#define TPS65224_MASK_ADC_RESULT_3_0			GENMASK(7, 4)
 925
 926/* STARTUP_CTRL Register field definition */
 927#define TPS65224_MASK_STARTUP_DEST			GENMASK(6, 5)
 928#define TPS65224_BIT_FIRST_STARTUP_DONE			BIT(7)
 929
 930/* SCRATCH_PAD_REG_1 Register field definition */
 931#define TPS6594_MASK_SCRATCH_PAD_1			GENMASK(7, 0)
 932
 933/* SCRATCH_PAD_REG_2 Register field definition */
 934#define TPS6594_MASK_SCRATCH_PAD_2			GENMASK(7, 0)
 935
 936/* SCRATCH_PAD_REG_3 Register field definition */
 937#define TPS6594_MASK_SCRATCH_PAD_3			GENMASK(7, 0)
 938
 939/* SCRATCH_PAD_REG_4 Register field definition */
 940#define TPS6594_MASK_SCRATCH_PAD_4			GENMASK(7, 0)
 941
 942/* PFSM_DELAY_REG_1 Register field definition */
 943#define TPS6594_MASK_PFSM_DELAY1			GENMASK(7, 0)
 944
 945/* PFSM_DELAY_REG_2 Register field definition */
 946#define TPS6594_MASK_PFSM_DELAY2			GENMASK(7, 0)
 947
 948/* PFSM_DELAY_REG_3 Register field definition */
 949#define TPS6594_MASK_PFSM_DELAY3			GENMASK(7, 0)
 950
 951/* PFSM_DELAY_REG_4 Register field definition */
 952#define TPS6594_MASK_PFSM_DELAY4			GENMASK(7, 0)
 953
 954/* CRC_CALC_CONTROL Register field definition */
 955#define TPS65224_BIT_RUN_CRC_BIST			BIT(0)
 956#define TPS65224_BIT_RUN_CRC_UPDATE			BIT(1)
 957
 958/* ADC_GAIN_COMP_REG Register field definition */
 959#define TPS65224_MASK_ADC_GAIN_COMP			GENMASK(7, 0)
 960
 961/* REGMAP_USER_CRC_LOW Register field definition */
 962#define TPS65224_MASK_REGMAP_USER_CRC16_LOW		GENMASK(7, 0)
 963
 964/* REGMAP_USER_CRC_HIGH Register field definition */
 965#define TPS65224_MASK_REGMAP_USER_CRC16_HIGH		GENMASK(7, 0)
 966
 967/* WD_ANSWER_REG Register field definition */
 968#define TPS6594_MASK_WD_ANSWER				GENMASK(7, 0)
 969
 970/* WD_QUESTION_ANSW_CNT register field definition */
 971#define TPS6594_MASK_WD_QUESTION			GENMASK(3, 0)
 972#define TPS6594_MASK_WD_ANSW_CNT			GENMASK(5, 4)
 973#define TPS65224_BIT_INT_TOP_STATUS			BIT(7)
 974
 975/* WD WIN1_CFG register field definition */
 976#define TPS6594_MASK_WD_WIN1_CFG			GENMASK(6, 0)
 977
 978/* WD WIN2_CFG register field definition */
 979#define TPS6594_MASK_WD_WIN2_CFG			GENMASK(6, 0)
 980
 981/* WD LongWin register field definition */
 982#define TPS6594_MASK_WD_LONGWIN_CFG			GENMASK(7, 0)
 983
 984/* WD_MODE_REG register field definition */
 985#define TPS6594_BIT_WD_RETURN_LONGWIN			BIT(0)
 986#define TPS6594_BIT_WD_MODE_SELECT			BIT(1)
 987#define TPS6594_BIT_WD_PWRHOLD				BIT(2)
 988#define TPS65224_BIT_WD_ENDRV_SEL			BIT(6)
 989#define TPS65224_BIT_WD_CNT_SEL				BIT(7)
 990
 991/* WD_QA_CFG register field definition */
 992#define TPS6594_MASK_WD_QUESTION_SEED			GENMASK(3, 0)
 993#define TPS6594_MASK_WD_QA_LFSR				GENMASK(5, 4)
 994#define TPS6594_MASK_WD_QA_FDBK				GENMASK(7, 6)
 995
 996/* WD_ERR_STATUS register field definition */
 997#define TPS6594_BIT_WD_LONGWIN_TIMEOUT_INT		BIT(0)
 998#define TPS6594_BIT_WD_TIMEOUT				BIT(1)
 999#define TPS6594_BIT_WD_TRIG_EARLY			BIT(2)
1000#define TPS6594_BIT_WD_ANSW_EARLY			BIT(3)
1001#define TPS6594_BIT_WD_SEQ_ERR				BIT(4)
1002#define TPS6594_BIT_WD_ANSW_ERR				BIT(5)
1003#define TPS6594_BIT_WD_FAIL_INT				BIT(6)
1004#define TPS6594_BIT_WD_RST_INT				BIT(7)
1005
1006/* WD_THR_CFG register field definition */
1007#define TPS6594_MASK_WD_RST_TH				GENMASK(2, 0)
1008#define TPS6594_MASK_WD_FAIL_TH				GENMASK(5, 3)
1009#define TPS6594_BIT_WD_EN				BIT(6)
1010#define TPS6594_BIT_WD_RST_EN				BIT(7)
1011
1012/* WD_FAIL_CNT_REG register field definition */
1013#define TPS6594_MASK_WD_FAIL_CNT			GENMASK(3, 0)
1014#define TPS6594_BIT_WD_FIRST_OK				BIT(5)
1015#define TPS6594_BIT_WD_BAD_EVENT			BIT(6)
1016
1017/* CRC8 polynomial for I2C & SPI protocols */
1018#define TPS6594_CRC8_POLYNOMIAL	0x07
1019
1020/* IRQs */
1021enum tps6594_irqs {
1022	/* INT_BUCK1_2 register */
1023	TPS6594_IRQ_BUCK1_OV,
1024	TPS6594_IRQ_BUCK1_UV,
1025	TPS6594_IRQ_BUCK1_SC,
1026	TPS6594_IRQ_BUCK1_ILIM,
1027	TPS6594_IRQ_BUCK2_OV,
1028	TPS6594_IRQ_BUCK2_UV,
1029	TPS6594_IRQ_BUCK2_SC,
1030	TPS6594_IRQ_BUCK2_ILIM,
1031	/* INT_BUCK3_4 register */
1032	TPS6594_IRQ_BUCK3_OV,
1033	TPS6594_IRQ_BUCK3_UV,
1034	TPS6594_IRQ_BUCK3_SC,
1035	TPS6594_IRQ_BUCK3_ILIM,
1036	TPS6594_IRQ_BUCK4_OV,
1037	TPS6594_IRQ_BUCK4_UV,
1038	TPS6594_IRQ_BUCK4_SC,
1039	TPS6594_IRQ_BUCK4_ILIM,
1040	/* INT_BUCK5 register */
1041	TPS6594_IRQ_BUCK5_OV,
1042	TPS6594_IRQ_BUCK5_UV,
1043	TPS6594_IRQ_BUCK5_SC,
1044	TPS6594_IRQ_BUCK5_ILIM,
1045	/* INT_LDO1_2 register */
1046	TPS6594_IRQ_LDO1_OV,
1047	TPS6594_IRQ_LDO1_UV,
1048	TPS6594_IRQ_LDO1_SC,
1049	TPS6594_IRQ_LDO1_ILIM,
1050	TPS6594_IRQ_LDO2_OV,
1051	TPS6594_IRQ_LDO2_UV,
1052	TPS6594_IRQ_LDO2_SC,
1053	TPS6594_IRQ_LDO2_ILIM,
1054	/* INT_LDO3_4 register */
1055	TPS6594_IRQ_LDO3_OV,
1056	TPS6594_IRQ_LDO3_UV,
1057	TPS6594_IRQ_LDO3_SC,
1058	TPS6594_IRQ_LDO3_ILIM,
1059	TPS6594_IRQ_LDO4_OV,
1060	TPS6594_IRQ_LDO4_UV,
1061	TPS6594_IRQ_LDO4_SC,
1062	TPS6594_IRQ_LDO4_ILIM,
1063	/* INT_VMON register */
1064	TPS6594_IRQ_VCCA_OV,
1065	TPS6594_IRQ_VCCA_UV,
1066	TPS6594_IRQ_VMON1_OV,
1067	TPS6594_IRQ_VMON1_UV,
1068	TPS6594_IRQ_VMON1_RV,
1069	TPS6594_IRQ_VMON2_OV,
1070	TPS6594_IRQ_VMON2_UV,
1071	TPS6594_IRQ_VMON2_RV,
1072	/* INT_GPIO register */
1073	TPS6594_IRQ_GPIO9,
1074	TPS6594_IRQ_GPIO10,
1075	TPS6594_IRQ_GPIO11,
1076	/* INT_GPIO1_8 register */
1077	TPS6594_IRQ_GPIO1,
1078	TPS6594_IRQ_GPIO2,
1079	TPS6594_IRQ_GPIO3,
1080	TPS6594_IRQ_GPIO4,
1081	TPS6594_IRQ_GPIO5,
1082	TPS6594_IRQ_GPIO6,
1083	TPS6594_IRQ_GPIO7,
1084	TPS6594_IRQ_GPIO8,
1085	/* INT_STARTUP register */
1086	TPS6594_IRQ_NPWRON_START,
1087	TPS6594_IRQ_ENABLE,
1088	TPS6594_IRQ_FSD,
1089	TPS6594_IRQ_SOFT_REBOOT,
1090	/* INT_MISC register */
1091	TPS6594_IRQ_BIST_PASS,
1092	TPS6594_IRQ_EXT_CLK,
1093	TPS6594_IRQ_TWARN,
1094	/* INT_MODERATE_ERR register */
1095	TPS6594_IRQ_TSD_ORD,
1096	TPS6594_IRQ_BIST_FAIL,
1097	TPS6594_IRQ_REG_CRC_ERR,
1098	TPS6594_IRQ_RECOV_CNT,
1099	TPS6594_IRQ_SPMI_ERR,
1100	TPS6594_IRQ_NPWRON_LONG,
1101	TPS6594_IRQ_NINT_READBACK,
1102	TPS6594_IRQ_NRSTOUT_READBACK,
1103	/* INT_SEVERE_ERR register */
1104	TPS6594_IRQ_TSD_IMM,
1105	TPS6594_IRQ_VCCA_OVP,
1106	TPS6594_IRQ_PFSM_ERR,
1107	/* INT_FSM_ERR register */
1108	TPS6594_IRQ_IMM_SHUTDOWN,
1109	TPS6594_IRQ_ORD_SHUTDOWN,
1110	TPS6594_IRQ_MCU_PWR_ERR,
1111	TPS6594_IRQ_SOC_PWR_ERR,
1112	/* INT_COMM_ERR register */
1113	TPS6594_IRQ_COMM_FRM_ERR,
1114	TPS6594_IRQ_COMM_CRC_ERR,
1115	TPS6594_IRQ_COMM_ADR_ERR,
1116	TPS6594_IRQ_I2C2_CRC_ERR,
1117	TPS6594_IRQ_I2C2_ADR_ERR,
1118	/* INT_READBACK_ERR register */
1119	TPS6594_IRQ_EN_DRV_READBACK,
1120	TPS6594_IRQ_NRSTOUT_SOC_READBACK,
1121	/* INT_ESM register */
1122	TPS6594_IRQ_ESM_SOC_PIN,
1123	TPS6594_IRQ_ESM_SOC_FAIL,
1124	TPS6594_IRQ_ESM_SOC_RST,
1125	/* RTC_STATUS register */
1126	TPS6594_IRQ_TIMER,
1127	TPS6594_IRQ_ALARM,
1128	TPS6594_IRQ_POWER_UP,
1129};
1130
1131#define TPS6594_IRQ_NAME_BUCK1_OV		"buck1_ov"
1132#define TPS6594_IRQ_NAME_BUCK1_UV		"buck1_uv"
1133#define TPS6594_IRQ_NAME_BUCK1_SC		"buck1_sc"
1134#define TPS6594_IRQ_NAME_BUCK1_ILIM		"buck1_ilim"
1135#define TPS6594_IRQ_NAME_BUCK2_OV		"buck2_ov"
1136#define TPS6594_IRQ_NAME_BUCK2_UV		"buck2_uv"
1137#define TPS6594_IRQ_NAME_BUCK2_SC		"buck2_sc"
1138#define TPS6594_IRQ_NAME_BUCK2_ILIM		"buck2_ilim"
1139#define TPS6594_IRQ_NAME_BUCK3_OV		"buck3_ov"
1140#define TPS6594_IRQ_NAME_BUCK3_UV		"buck3_uv"
1141#define TPS6594_IRQ_NAME_BUCK3_SC		"buck3_sc"
1142#define TPS6594_IRQ_NAME_BUCK3_ILIM		"buck3_ilim"
1143#define TPS6594_IRQ_NAME_BUCK4_OV		"buck4_ov"
1144#define TPS6594_IRQ_NAME_BUCK4_UV		"buck4_uv"
1145#define TPS6594_IRQ_NAME_BUCK4_SC		"buck4_sc"
1146#define TPS6594_IRQ_NAME_BUCK4_ILIM		"buck4_ilim"
1147#define TPS6594_IRQ_NAME_BUCK5_OV		"buck5_ov"
1148#define TPS6594_IRQ_NAME_BUCK5_UV		"buck5_uv"
1149#define TPS6594_IRQ_NAME_BUCK5_SC		"buck5_sc"
1150#define TPS6594_IRQ_NAME_BUCK5_ILIM		"buck5_ilim"
1151#define TPS6594_IRQ_NAME_LDO1_OV		"ldo1_ov"
1152#define TPS6594_IRQ_NAME_LDO1_UV		"ldo1_uv"
1153#define TPS6594_IRQ_NAME_LDO1_SC		"ldo1_sc"
1154#define TPS6594_IRQ_NAME_LDO1_ILIM		"ldo1_ilim"
1155#define TPS6594_IRQ_NAME_LDO2_OV		"ldo2_ov"
1156#define TPS6594_IRQ_NAME_LDO2_UV		"ldo2_uv"
1157#define TPS6594_IRQ_NAME_LDO2_SC		"ldo2_sc"
1158#define TPS6594_IRQ_NAME_LDO2_ILIM		"ldo2_ilim"
1159#define TPS6594_IRQ_NAME_LDO3_OV		"ldo3_ov"
1160#define TPS6594_IRQ_NAME_LDO3_UV		"ldo3_uv"
1161#define TPS6594_IRQ_NAME_LDO3_SC		"ldo3_sc"
1162#define TPS6594_IRQ_NAME_LDO3_ILIM		"ldo3_ilim"
1163#define TPS6594_IRQ_NAME_LDO4_OV		"ldo4_ov"
1164#define TPS6594_IRQ_NAME_LDO4_UV		"ldo4_uv"
1165#define TPS6594_IRQ_NAME_LDO4_SC		"ldo4_sc"
1166#define TPS6594_IRQ_NAME_LDO4_ILIM		"ldo4_ilim"
1167#define TPS6594_IRQ_NAME_VCCA_OV		"vcca_ov"
1168#define TPS6594_IRQ_NAME_VCCA_UV		"vcca_uv"
1169#define TPS6594_IRQ_NAME_VMON1_OV		"vmon1_ov"
1170#define TPS6594_IRQ_NAME_VMON1_UV		"vmon1_uv"
1171#define TPS6594_IRQ_NAME_VMON1_RV		"vmon1_rv"
1172#define TPS6594_IRQ_NAME_VMON2_OV		"vmon2_ov"
1173#define TPS6594_IRQ_NAME_VMON2_UV		"vmon2_uv"
1174#define TPS6594_IRQ_NAME_VMON2_RV		"vmon2_rv"
1175#define TPS6594_IRQ_NAME_GPIO9			"gpio9"
1176#define TPS6594_IRQ_NAME_GPIO10			"gpio10"
1177#define TPS6594_IRQ_NAME_GPIO11			"gpio11"
1178#define TPS6594_IRQ_NAME_GPIO1			"gpio1"
1179#define TPS6594_IRQ_NAME_GPIO2			"gpio2"
1180#define TPS6594_IRQ_NAME_GPIO3			"gpio3"
1181#define TPS6594_IRQ_NAME_GPIO4			"gpio4"
1182#define TPS6594_IRQ_NAME_GPIO5			"gpio5"
1183#define TPS6594_IRQ_NAME_GPIO6			"gpio6"
1184#define TPS6594_IRQ_NAME_GPIO7			"gpio7"
1185#define TPS6594_IRQ_NAME_GPIO8			"gpio8"
1186#define TPS6594_IRQ_NAME_NPWRON_START		"npwron_start"
1187#define TPS6594_IRQ_NAME_ENABLE			"enable"
1188#define TPS6594_IRQ_NAME_FSD			"fsd"
1189#define TPS6594_IRQ_NAME_SOFT_REBOOT		"soft_reboot"
1190#define TPS6594_IRQ_NAME_BIST_PASS		"bist_pass"
1191#define TPS6594_IRQ_NAME_EXT_CLK		"ext_clk"
1192#define TPS6594_IRQ_NAME_TWARN			"twarn"
1193#define TPS6594_IRQ_NAME_TSD_ORD		"tsd_ord"
1194#define TPS6594_IRQ_NAME_BIST_FAIL		"bist_fail"
1195#define TPS6594_IRQ_NAME_REG_CRC_ERR		"reg_crc_err"
1196#define TPS6594_IRQ_NAME_RECOV_CNT		"recov_cnt"
1197#define TPS6594_IRQ_NAME_SPMI_ERR		"spmi_err"
1198#define TPS6594_IRQ_NAME_NPWRON_LONG		"npwron_long"
1199#define TPS6594_IRQ_NAME_NINT_READBACK		"nint_readback"
1200#define TPS6594_IRQ_NAME_NRSTOUT_READBACK	"nrstout_readback"
1201#define TPS6594_IRQ_NAME_TSD_IMM		"tsd_imm"
1202#define TPS6594_IRQ_NAME_VCCA_OVP		"vcca_ovp"
1203#define TPS6594_IRQ_NAME_PFSM_ERR		"pfsm_err"
1204#define TPS6594_IRQ_NAME_IMM_SHUTDOWN		"imm_shutdown"
1205#define TPS6594_IRQ_NAME_ORD_SHUTDOWN		"ord_shutdown"
1206#define TPS6594_IRQ_NAME_MCU_PWR_ERR		"mcu_pwr_err"
1207#define TPS6594_IRQ_NAME_SOC_PWR_ERR		"soc_pwr_err"
1208#define TPS6594_IRQ_NAME_COMM_FRM_ERR		"comm_frm_err"
1209#define TPS6594_IRQ_NAME_COMM_CRC_ERR		"comm_crc_err"
1210#define TPS6594_IRQ_NAME_COMM_ADR_ERR		"comm_adr_err"
1211#define TPS6594_IRQ_NAME_EN_DRV_READBACK	"en_drv_readback"
1212#define TPS6594_IRQ_NAME_NRSTOUT_SOC_READBACK	"nrstout_soc_readback"
1213#define TPS6594_IRQ_NAME_ESM_SOC_PIN		"esm_soc_pin"
1214#define TPS6594_IRQ_NAME_ESM_SOC_FAIL		"esm_soc_fail"
1215#define TPS6594_IRQ_NAME_ESM_SOC_RST		"esm_soc_rst"
1216#define TPS6594_IRQ_NAME_TIMER			"timer"
1217#define TPS6594_IRQ_NAME_ALARM			"alarm"
1218#define TPS6594_IRQ_NAME_POWERUP		"powerup"
1219
1220/* IRQs */
1221enum tps65224_irqs {
1222	/* INT_BUCK register */
1223	TPS65224_IRQ_BUCK1_UVOV,
1224	TPS65224_IRQ_BUCK2_UVOV,
1225	TPS65224_IRQ_BUCK3_UVOV,
1226	TPS65224_IRQ_BUCK4_UVOV,
1227	/* INT_LDO_VMON register */
1228	TPS65224_IRQ_LDO1_UVOV,
1229	TPS65224_IRQ_LDO2_UVOV,
1230	TPS65224_IRQ_LDO3_UVOV,
1231	TPS65224_IRQ_VCCA_UVOV,
1232	TPS65224_IRQ_VMON1_UVOV,
1233	TPS65224_IRQ_VMON2_UVOV,
1234	/* INT_GPIO register */
1235	TPS65224_IRQ_GPIO1,
1236	TPS65224_IRQ_GPIO2,
1237	TPS65224_IRQ_GPIO3,
1238	TPS65224_IRQ_GPIO4,
1239	TPS65224_IRQ_GPIO5,
1240	TPS65224_IRQ_GPIO6,
1241	/* INT_STARTUP register */
1242	TPS65224_IRQ_VSENSE,
1243	TPS65224_IRQ_ENABLE,
1244	TPS65224_IRQ_PB_SHORT,
1245	TPS65224_IRQ_FSD,
1246	TPS65224_IRQ_SOFT_REBOOT,
1247	/* INT_MISC register */
1248	TPS65224_IRQ_BIST_PASS,
1249	TPS65224_IRQ_EXT_CLK,
1250	TPS65224_IRQ_REG_UNLOCK,
1251	TPS65224_IRQ_TWARN,
1252	TPS65224_IRQ_PB_LONG,
1253	TPS65224_IRQ_PB_FALL,
1254	TPS65224_IRQ_PB_RISE,
1255	TPS65224_IRQ_ADC_CONV_READY,
1256	/* INT_MODERATE_ERR register */
1257	TPS65224_IRQ_TSD_ORD,
1258	TPS65224_IRQ_BIST_FAIL,
1259	TPS65224_IRQ_REG_CRC_ERR,
1260	TPS65224_IRQ_RECOV_CNT,
1261	/* INT_SEVERE_ERR register */
1262	TPS65224_IRQ_TSD_IMM,
1263	TPS65224_IRQ_VCCA_OVP,
1264	TPS65224_IRQ_PFSM_ERR,
1265	TPS65224_IRQ_BG_XMON,
1266	/* INT_FSM_ERR register */
1267	TPS65224_IRQ_IMM_SHUTDOWN,
1268	TPS65224_IRQ_ORD_SHUTDOWN,
1269	TPS65224_IRQ_MCU_PWR_ERR,
1270	TPS65224_IRQ_SOC_PWR_ERR,
1271	TPS65224_IRQ_COMM_ERR,
1272	TPS65224_IRQ_I2C2_ERR,
1273};
1274
1275#define TPS65224_IRQ_NAME_BUCK1_UVOV		"buck1_uvov"
1276#define TPS65224_IRQ_NAME_BUCK2_UVOV		"buck2_uvov"
1277#define TPS65224_IRQ_NAME_BUCK3_UVOV		"buck3_uvov"
1278#define TPS65224_IRQ_NAME_BUCK4_UVOV		"buck4_uvov"
1279#define TPS65224_IRQ_NAME_LDO1_UVOV		"ldo1_uvov"
1280#define TPS65224_IRQ_NAME_LDO2_UVOV		"ldo2_uvov"
1281#define TPS65224_IRQ_NAME_LDO3_UVOV		"ldo3_uvov"
1282#define TPS65224_IRQ_NAME_VCCA_UVOV		"vcca_uvov"
1283#define TPS65224_IRQ_NAME_VMON1_UVOV		"vmon1_uvov"
1284#define TPS65224_IRQ_NAME_VMON2_UVOV		"vmon2_uvov"
1285#define TPS65224_IRQ_NAME_GPIO1			"gpio1"
1286#define TPS65224_IRQ_NAME_GPIO2			"gpio2"
1287#define TPS65224_IRQ_NAME_GPIO3			"gpio3"
1288#define TPS65224_IRQ_NAME_GPIO4			"gpio4"
1289#define TPS65224_IRQ_NAME_GPIO5			"gpio5"
1290#define TPS65224_IRQ_NAME_GPIO6			"gpio6"
1291#define TPS65224_IRQ_NAME_VSENSE	        "vsense"
1292#define TPS65224_IRQ_NAME_ENABLE		"enable"
1293#define TPS65224_IRQ_NAME_PB_SHORT		"pb_short"
1294#define TPS65224_IRQ_NAME_FSD			"fsd"
1295#define TPS65224_IRQ_NAME_SOFT_REBOOT		"soft_reboot"
1296#define TPS65224_IRQ_NAME_BIST_PASS		"bist_pass"
1297#define TPS65224_IRQ_NAME_EXT_CLK		"ext_clk"
1298#define TPS65224_IRQ_NAME_REG_UNLOCK		"reg_unlock"
1299#define TPS65224_IRQ_NAME_TWARN			"twarn"
1300#define TPS65224_IRQ_NAME_PB_LONG		"pb_long"
1301#define TPS65224_IRQ_NAME_PB_FALL		"pb_fall"
1302#define TPS65224_IRQ_NAME_PB_RISE		"pb_rise"
1303#define TPS65224_IRQ_NAME_ADC_CONV_READY	"adc_conv_ready"
1304#define TPS65224_IRQ_NAME_TSD_ORD		"tsd_ord"
1305#define TPS65224_IRQ_NAME_BIST_FAIL		"bist_fail"
1306#define TPS65224_IRQ_NAME_REG_CRC_ERR		"reg_crc_err"
1307#define TPS65224_IRQ_NAME_RECOV_CNT		"recov_cnt"
1308#define TPS65224_IRQ_NAME_TSD_IMM		"tsd_imm"
1309#define TPS65224_IRQ_NAME_VCCA_OVP		"vcca_ovp"
1310#define TPS65224_IRQ_NAME_PFSM_ERR		"pfsm_err"
1311#define TPS65224_IRQ_NAME_BG_XMON		"bg_xmon"
1312#define TPS65224_IRQ_NAME_IMM_SHUTDOWN		"imm_shutdown"
1313#define TPS65224_IRQ_NAME_ORD_SHUTDOWN		"ord_shutdown"
1314#define TPS65224_IRQ_NAME_MCU_PWR_ERR		"mcu_pwr_err"
1315#define TPS65224_IRQ_NAME_SOC_PWR_ERR		"soc_pwr_err"
1316#define TPS65224_IRQ_NAME_COMM_ERR		"comm_err"
1317#define TPS65224_IRQ_NAME_I2C2_ERR		"i2c2_err"
1318#define TPS65224_IRQ_NAME_POWERUP		"powerup"
1319
1320/**
1321 * struct tps6594 - device private data structure
1322 *
1323 * @dev:      MFD parent device
1324 * @chip_id:  chip ID
1325 * @reg:      I2C slave address or SPI chip select number
1326 * @use_crc:  if true, use CRC for I2C and SPI interface protocols
1327 * @regmap:   regmap for accessing the device registers
1328 * @irq:      irq generated by the device
1329 * @irq_data: regmap irq data used for the irq chip
1330 */
1331struct tps6594 {
1332	struct device *dev;
1333	unsigned long chip_id;
1334	unsigned short reg;
1335	bool use_crc;
1336	struct regmap *regmap;
1337	int irq;
1338	struct regmap_irq_chip_data *irq_data;
1339};
1340
1341extern const struct regmap_access_table tps6594_volatile_table;
1342extern const struct regmap_access_table tps65224_volatile_table;
1343
1344int tps6594_device_init(struct tps6594 *tps, bool enable_crc);
1345
1346#endif /*  __LINUX_MFD_TPS6594_H */