stm32-timers.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Copyright (C) STMicroelectronics 2016
  4 * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
  5 */
  6
  7#ifndef _LINUX_STM32_GPTIMER_H_
  8#define _LINUX_STM32_GPTIMER_H_
  9
 10#include <linux/clk.h>
 11#include <linux/dmaengine.h>
 12#include <linux/dma-mapping.h>
 13#include <linux/regmap.h>
 14
 15#define TIM_CR1		0x00			/* Control Register 1			*/
 16#define TIM_CR2		0x04			/* Control Register 2			*/
 17#define TIM_SMCR	0x08			/* Slave mode control reg		*/
 18#define TIM_DIER	0x0C			/* DMA/interrupt register		*/
 19#define TIM_SR		0x10			/* Status register			*/
 20#define TIM_EGR		0x14			/* Event Generation Reg			*/
 21#define TIM_CCMR1	0x18			/* Capt/Comp 1 Mode Reg			*/
 22#define TIM_CCMR2	0x1C			/* Capt/Comp 2 Mode Reg			*/
 23#define TIM_CCER	0x20			/* Capt/Comp Enable Reg			*/
 24#define TIM_CNT		0x24			/* Counter				*/
 25#define TIM_PSC		0x28			/* Prescaler				*/
 26#define TIM_ARR		0x2c			/* Auto-Reload Register			*/
 27#define TIM_CCRx(x)	(0x34 + 4 * ((x) - 1))	/* Capt/Comp Register x (x ∈ {1, .. 4})	*/
 28#define TIM_CCR1	TIM_CCRx(1)		/* Capt/Comp Register 1			*/
 29#define TIM_CCR2	TIM_CCRx(2)		/* Capt/Comp Register 2			*/
 30#define TIM_CCR3	TIM_CCRx(3)		/* Capt/Comp Register 3			*/
 31#define TIM_CCR4	TIM_CCRx(4)		/* Capt/Comp Register 4			*/
 32#define TIM_BDTR	0x44			/* Break and Dead-Time Reg		*/
 33#define TIM_DCR		0x48			/* DMA control register			*/
 34#define TIM_DMAR	0x4C			/* DMA register for transfer		*/
 35#define TIM_TISEL	0x68			/* Input Selection			*/
 36#define TIM_HWCFGR2	0x3EC			/* hardware configuration 2 Reg (MP25)	*/
 37#define TIM_HWCFGR1	0x3F0			/* hardware configuration 1 Reg (MP25)	*/
 38#define TIM_IPIDR	0x3F8			/* IP identification Reg (MP25)		*/
 39
 40#define TIM_CR1_CEN		BIT(0)					/* Counter Enable				*/
 41#define TIM_CR1_DIR		BIT(4)					/* Counter Direction				*/
 42#define TIM_CR1_ARPE		BIT(7)					/* Auto-reload Preload Ena			*/
 43#define TIM_CR2_MMS		(BIT(4) | BIT(5) | BIT(6))		/* Master mode selection			*/
 44#define TIM_CR2_MMS2		GENMASK(23, 20)				/* Master mode selection 2			*/
 45#define TIM_SMCR_SMS		(BIT(0) | BIT(1) | BIT(2))		/* Slave mode selection				*/
 46#define TIM_SMCR_TS		(BIT(4) | BIT(5) | BIT(6))		/* Trigger selection				*/
 47#define TIM_DIER_UIE		BIT(0)					/* Update interrupt				*/
 48#define TIM_DIER_CCxIE(x)	BIT(1 + ((x) - 1))			/* CCx Interrupt Enable	(x ∈ {1, .. 4})		*/
 49#define TIM_DIER_CC1IE		TIM_DIER_CCxIE(1)			/* CC1 Interrupt Enable				*/
 50#define TIM_DIER_CC2IE		TIM_DIER_CCxIE(2)			/* CC2 Interrupt Enable				*/
 51#define TIM_DIER_CC3IE		TIM_DIER_CCxIE(3)			/* CC3 Interrupt Enable				*/
 52#define TIM_DIER_CC4IE		TIM_DIER_CCxIE(4)			/* CC4 Interrupt Enable				*/
 53#define TIM_DIER_UDE		BIT(8)					/* Update DMA request Enable			*/
 54#define TIM_DIER_CCxDE(x)	BIT(9 + ((x) - 1))			/* CCx DMA request Enable (x ∈ {1, .. 4})	*/
 55#define TIM_DIER_CC1DE		TIM_DIER_CCxDE(1)			/* CC1 DMA request Enable			*/
 56#define TIM_DIER_CC2DE		TIM_DIER_CCxDE(2)			/* CC2 DMA request Enable			*/
 57#define TIM_DIER_CC3DE		TIM_DIER_CCxDE(3)			/* CC3 DMA request Enable			*/
 58#define TIM_DIER_CC4DE		TIM_DIER_CCxDE(4)			/* CC4 DMA request Enable			*/
 59#define TIM_DIER_COMDE		BIT(13)					/* COM DMA request Enable			*/
 60#define TIM_DIER_TDE		BIT(14)					/* Trigger DMA request Enable			*/
 61#define TIM_SR_UIF		BIT(0)					/* Update interrupt flag			*/
 62#define TIM_SR_CC_IF(x)		BIT((x) + 1)				/* CC1, CC2, CC3, CC4 interrupt flag		*/
 63#define TIM_EGR_UG		BIT(0)					/* Update Generation				*/
 64#define TIM_CCMR_PE		BIT(3)					/* Channel Preload Enable			*/
 65#define TIM_CCMR_M1		(BIT(6) | BIT(5))			/* Channel PWM Mode 1				*/
 66#define TIM_CCMR_CC1S		(BIT(0) | BIT(1))			/* Capture/compare 1 sel			*/
 67#define TIM_CCMR_IC1PSC		GENMASK(3, 2)				/* Input capture 1 prescaler			*/
 68#define TIM_CCMR_CC2S		(BIT(8) | BIT(9))			/* Capture/compare 2 sel			*/
 69#define TIM_CCMR_IC2PSC		GENMASK(11, 10)				/* Input capture 2 prescaler			*/
 70#define TIM_CCMR_CC1S_TI1	BIT(0)					/* IC1/IC3 selects TI1/TI3			*/
 71#define TIM_CCMR_CC1S_TI2	BIT(1)					/* IC1/IC3 selects TI2/TI4			*/
 72#define TIM_CCMR_CC2S_TI2	BIT(8)					/* IC2/IC4 selects TI2/TI4			*/
 73#define TIM_CCMR_CC2S_TI1	BIT(9)					/* IC2/IC4 selects TI1/TI3			*/
 74#define TIM_CCMR_CC3S		(BIT(0) | BIT(1))			/* Capture/compare 3 sel			*/
 75#define TIM_CCMR_CC4S		(BIT(8) | BIT(9))			/* Capture/compare 4 sel			*/
 76#define TIM_CCMR_CC3S_TI3	BIT(0)					/* IC3 selects TI3				*/
 77#define TIM_CCMR_CC4S_TI4	BIT(8)					/* IC4 selects TI4				*/
 78#define TIM_CCER_CCxE(x)	BIT(0 + 4 * ((x) - 1))			/* Capt/Comp x  out Ena (x ∈ {1, .. 4})		*/
 79#define TIM_CCER_CCxP(x)	BIT(1 + 4 * ((x) - 1))			/* Capt/Comp x  Polarity (x ∈ {1, .. 4})	*/
 80#define TIM_CCER_CCxNE(x)	BIT(2 + 4 * ((x) - 1))			/* Capt/Comp xN out Ena (x ∈ {1, .. 4})		*/
 81#define TIM_CCER_CCxNP(x)	BIT(3 + 4 * ((x) - 1))			/* Capt/Comp xN Polarity (x ∈ {1, .. 4})	*/
 82#define TIM_CCER_CC1E		TIM_CCER_CCxE(1)			/* Capt/Comp 1  out Ena				*/
 83#define TIM_CCER_CC1P		TIM_CCER_CCxP(1)			/* Capt/Comp 1  Polarity			*/
 84#define TIM_CCER_CC1NE		TIM_CCER_CCxNE(1)			/* Capt/Comp 1N out Ena				*/
 85#define TIM_CCER_CC1NP		TIM_CCER_CCxNP(1)			/* Capt/Comp 1N Polarity			*/
 86#define TIM_CCER_CC2E		TIM_CCER_CCxE(2)			/* Capt/Comp 2  out Ena				*/
 87#define TIM_CCER_CC2P		TIM_CCER_CCxP(2)			/* Capt/Comp 2  Polarity			*/
 88#define TIM_CCER_CC2NE		TIM_CCER_CCxNE(2)			/* Capt/Comp 2N out Ena				*/
 89#define TIM_CCER_CC2NP		TIM_CCER_CCxNP(2)			/* Capt/Comp 2N Polarity			*/
 90#define TIM_CCER_CC3E		TIM_CCER_CCxE(3)			/* Capt/Comp 3  out Ena				*/
 91#define TIM_CCER_CC3P		TIM_CCER_CCxP(3)			/* Capt/Comp 3  Polarity			*/
 92#define TIM_CCER_CC3NE		TIM_CCER_CCxNE(3)			/* Capt/Comp 3N out Ena				*/
 93#define TIM_CCER_CC3NP		TIM_CCER_CCxNP(3)			/* Capt/Comp 3N Polarity			*/
 94#define TIM_CCER_CC4E		TIM_CCER_CCxE(4)			/* Capt/Comp 4  out Ena				*/
 95#define TIM_CCER_CC4P		TIM_CCER_CCxP(4)			/* Capt/Comp 4  Polarity			*/
 96#define TIM_CCER_CC4NE		TIM_CCER_CCxNE(4)			/* Capt/Comp 4N out Ena				*/
 97#define TIM_CCER_CC4NP		TIM_CCER_CCxNP(4)			/* Capt/Comp 4N Polarity			*/
 98#define TIM_CCER_CCXE		(BIT(0) | BIT(4) | BIT(8) | BIT(12))
 99#define TIM_BDTR_BKE(x)		BIT(12 + (x) * 12)			/* Break input enable				*/
100#define TIM_BDTR_BKP(x)		BIT(13 + (x) * 12)			/* Break input polarity				*/
101#define TIM_BDTR_AOE		BIT(14)					/* Automatic Output Enable			*/
102#define TIM_BDTR_MOE		BIT(15)					/* Main Output Enable				*/
103#define TIM_BDTR_BKF(x)		(0xf << (16 + (x) * 4))
104#define TIM_DCR_DBA		GENMASK(4, 0)				/* DMA base addr				*/
105#define TIM_DCR_DBL		GENMASK(12, 8)				/* DMA burst len				*/
106#define TIM_HWCFGR1_NB_OF_CC	GENMASK(3, 0)				/* Capture/compare channels			*/
107#define TIM_HWCFGR1_NB_OF_DT	GENMASK(7, 4)				/* Complementary outputs & dead-time generators */
108#define TIM_HWCFGR2_CNT_WIDTH	GENMASK(15, 8)				/* Counter width				*/
109
110#define MAX_TIM_PSC				0xFFFF
111#define MAX_TIM_ICPSC				0x3
112#define TIM_CR2_MMS_SHIFT			4
113#define TIM_CR2_MMS2_SHIFT			20
114#define TIM_SMCR_SMS_SLAVE_MODE_DISABLED	0 /* counts on internal clock when CEN=1 */
115#define TIM_SMCR_SMS_ENCODER_MODE_1		1 /* counts TI1FP1 edges, depending on TI2FP2 level */
116#define TIM_SMCR_SMS_ENCODER_MODE_2		2 /* counts TI2FP2 edges, depending on TI1FP1 level */
117#define TIM_SMCR_SMS_ENCODER_MODE_3		3 /* counts on both TI1FP1 and TI2FP2 edges */
118#define TIM_SMCR_TS_SHIFT			4
119#define TIM_BDTR_BKF_MASK			0xF
120#define TIM_BDTR_BKF_SHIFT(x)			(16 + (x) * 4)
121
122#define STM32MP25_TIM_IPIDR	0x00120002
123
124enum stm32_timers_dmas {
125	STM32_TIMERS_DMA_CH1,
126	STM32_TIMERS_DMA_CH2,
127	STM32_TIMERS_DMA_CH3,
128	STM32_TIMERS_DMA_CH4,
129	STM32_TIMERS_DMA_UP,
130	STM32_TIMERS_DMA_TRIG,
131	STM32_TIMERS_DMA_COM,
132	STM32_TIMERS_MAX_DMAS,
133};
134
135/* STM32 Timer may have either a unique global interrupt or 4 interrupt lines */
136enum stm32_timers_irqs {
137	STM32_TIMERS_IRQ_GLOBAL_BRK, /* global or brk IRQ */
138	STM32_TIMERS_IRQ_UP,
139	STM32_TIMERS_IRQ_TRG_COM,
140	STM32_TIMERS_IRQ_CC,
141	STM32_TIMERS_MAX_IRQS,
142};
143
144/**
145 * struct stm32_timers_dma - STM32 timer DMA handling.
146 * @completion:		end of DMA transfer completion
147 * @phys_base:		control registers physical base address
148 * @lock:		protect DMA access
149 * @chan:		DMA channel in use
150 * @chans:		DMA channels available for this timer instance
151 */
152struct stm32_timers_dma {
153	struct completion completion;
154	phys_addr_t phys_base;
155	struct mutex lock;
156	struct dma_chan *chan;
157	struct dma_chan *chans[STM32_TIMERS_MAX_DMAS];
158};
159
160struct stm32_timers {
161	struct clk *clk;
162	u32 ipidr;
163	struct regmap *regmap;
164	u32 max_arr;
165	struct stm32_timers_dma dma; /* Only to be used by the parent */
166	unsigned int nr_irqs;
167	int irq[STM32_TIMERS_MAX_IRQS];
168};
169
170#if IS_REACHABLE(CONFIG_MFD_STM32_TIMERS)
171int stm32_timers_dma_burst_read(struct device *dev, u32 *buf,
172				enum stm32_timers_dmas id, u32 reg,
173				unsigned int num_reg, unsigned int bursts,
174				unsigned long tmo_ms);
175#else
176static inline int stm32_timers_dma_burst_read(struct device *dev, u32 *buf,
177					      enum stm32_timers_dmas id,
178					      u32 reg,
179					      unsigned int num_reg,
180					      unsigned int bursts,
181					      unsigned long tmo_ms)
182{
183	return -ENODEV;
184}
185#endif
186#endif