s2mpu05.h

  1/* SPDX-License-Identifier: GPL-2.0+ */
  2/*
  3 * Copyright (c) 2015 Samsung Electronics Co., Ltd
  4 * Copyright (c) 2025 Kaustabh Chakraborty <kauschluss@disroot.org>
  5 */
  6
  7#ifndef __LINUX_MFD_S2MPU05_H
  8#define __LINUX_MFD_S2MPU05_H
  9
 10/* S2MPU05 registers */
 11enum S2MPU05_reg {
 12	S2MPU05_REG_ID,
 13	S2MPU05_REG_INT1,
 14	S2MPU05_REG_INT2,
 15	S2MPU05_REG_INT3,
 16	S2MPU05_REG_INT1M,
 17	S2MPU05_REG_INT2M,
 18	S2MPU05_REG_INT3M,
 19	S2MPU05_REG_ST1,
 20	S2MPU05_REG_ST2,
 21	S2MPU05_REG_PWRONSRC,
 22	S2MPU05_REG_OFFSRC,
 23	S2MPU05_REG_BU_CHG,
 24	S2MPU05_REG_RTC_BUF,
 25	S2MPU05_REG_CTRL1,
 26	S2MPU05_REG_CTRL2,
 27	S2MPU05_REG_ETC_TEST,
 28	S2MPU05_REG_OTP_ADRL,
 29	S2MPU05_REG_OTP_ADRH,
 30	S2MPU05_REG_OTP_DATA,
 31	S2MPU05_REG_MON1SEL,
 32	S2MPU05_REG_MON2SEL,
 33	S2MPU05_REG_CTRL3,
 34	S2MPU05_REG_ETC_OTP,
 35	S2MPU05_REG_UVLO,
 36	S2MPU05_REG_TIME_CTRL1,
 37	S2MPU05_REG_TIME_CTRL2,
 38	S2MPU05_REG_B1CTRL1,
 39	S2MPU05_REG_B1CTRL2,
 40	S2MPU05_REG_B2CTRL1,
 41	S2MPU05_REG_B2CTRL2,
 42	S2MPU05_REG_B2CTRL3,
 43	S2MPU05_REG_B2CTRL4,
 44	S2MPU05_REG_B3CTRL1,
 45	S2MPU05_REG_B3CTRL2,
 46	S2MPU05_REG_B3CTRL3,
 47	S2MPU05_REG_B4CTRL1,
 48	S2MPU05_REG_B4CTRL2,
 49	S2MPU05_REG_B5CTRL1,
 50	S2MPU05_REG_B5CTRL2,
 51	S2MPU05_REG_BUCK_RAMP,
 52	S2MPU05_REG_LDO_DVS1,
 53	S2MPU05_REG_LDO_DVS9,
 54	S2MPU05_REG_LDO_DVS10,
 55	S2MPU05_REG_L1CTRL,
 56	S2MPU05_REG_L2CTRL,
 57	S2MPU05_REG_L3CTRL,
 58	S2MPU05_REG_L4CTRL,
 59	S2MPU05_REG_L5CTRL,
 60	S2MPU05_REG_L6CTRL,
 61	S2MPU05_REG_L7CTRL,
 62	S2MPU05_REG_L8CTRL,
 63	S2MPU05_REG_L9CTRL1,
 64	S2MPU05_REG_L9CTRL2,
 65	S2MPU05_REG_L10CTRL,
 66	S2MPU05_REG_L11CTRL1,
 67	S2MPU05_REG_L11CTRL2,
 68	S2MPU05_REG_L12CTRL,
 69	S2MPU05_REG_L13CTRL,
 70	S2MPU05_REG_L14CTRL,
 71	S2MPU05_REG_L15CTRL,
 72	S2MPU05_REG_L16CTRL,
 73	S2MPU05_REG_L17CTRL1,
 74	S2MPU05_REG_L17CTRL2,
 75	S2MPU05_REG_L18CTRL1,
 76	S2MPU05_REG_L18CTRL2,
 77	S2MPU05_REG_L19CTRL,
 78	S2MPU05_REG_L20CTRL,
 79	S2MPU05_REG_L21CTRL,
 80	S2MPU05_REG_L22CTRL,
 81	S2MPU05_REG_L23CTRL,
 82	S2MPU05_REG_L24CTRL,
 83	S2MPU05_REG_L25CTRL,
 84	S2MPU05_REG_L26CTRL,
 85	S2MPU05_REG_L27CTRL,
 86	S2MPU05_REG_L28CTRL,
 87	S2MPU05_REG_L29CTRL,
 88	S2MPU05_REG_L30CTRL,
 89	S2MPU05_REG_L31CTRL,
 90	S2MPU05_REG_L32CTRL,
 91	S2MPU05_REG_L33CTRL,
 92	S2MPU05_REG_L34CTRL,
 93	S2MPU05_REG_L35CTRL,
 94	S2MPU05_REG_LDO_DSCH1,
 95	S2MPU05_REG_LDO_DSCH2,
 96	S2MPU05_REG_LDO_DSCH3,
 97	S2MPU05_REG_LDO_DSCH4,
 98	S2MPU05_REG_LDO_DSCH5,
 99	S2MPU05_REG_LDO_CTRL1,
100	S2MPU05_REG_LDO_CTRL2,
101	S2MPU05_REG_TCXO_CTRL,
102	S2MPU05_REG_SELMIF,
103};
104
105/* S2MPU05 regulator ids */
106enum S2MPU05_regulators {
107	S2MPU05_LDO1,
108	S2MPU05_LDO2,
109	S2MPU05_LDO3,
110	S2MPU05_LDO4,
111	S2MPU05_LDO5,
112	S2MPU05_LDO6,
113	S2MPU05_LDO7,
114	S2MPU05_LDO8,
115	S2MPU05_LDO9,
116	S2MPU05_LDO10,
117	S2MPU05_LDO11,
118	S2MPU05_LDO12,
119	S2MPU05_LDO13,
120	S2MPU05_LDO14,
121	S2MPU05_LDO15,
122	S2MPU05_LDO16,
123	S2MPU05_LDO17,
124	S2MPU05_LDO18,
125	S2MPU05_LDO19,
126	S2MPU05_LDO20,
127	S2MPU05_LDO21,
128	S2MPU05_LDO22,
129	S2MPU05_LDO23,
130	S2MPU05_LDO24,
131	S2MPU05_LDO25,
132	S2MPU05_LDO26,
133	S2MPU05_LDO27,
134	S2MPU05_LDO28,
135	S2MPU05_LDO29,
136	S2MPU05_LDO30,
137	S2MPU05_LDO31,
138	S2MPU05_LDO32,
139	S2MPU05_LDO33,
140	S2MPU05_LDO34,
141	S2MPU05_LDO35,
142	S2MPU05_BUCK1,
143	S2MPU05_BUCK2,
144	S2MPU05_BUCK3,
145	S2MPU05_BUCK4,
146	S2MPU05_BUCK5,
147
148	S2MPU05_REGULATOR_MAX,
149};
150
151#define S2MPU05_SW_ENABLE_MASK	0x03
152
153#define S2MPU05_ENABLE_TIME_LDO		128
154#define S2MPU05_ENABLE_TIME_BUCK1	110
155#define S2MPU05_ENABLE_TIME_BUCK2	110
156#define S2MPU05_ENABLE_TIME_BUCK3	110
157#define S2MPU05_ENABLE_TIME_BUCK4	150
158#define S2MPU05_ENABLE_TIME_BUCK5	150
159
160#define S2MPU05_LDO_MIN1	800000
161#define S2MPU05_LDO_MIN2	1800000
162#define S2MPU05_LDO_MIN3	400000
163#define S2MPU05_LDO_STEP1	12500
164#define S2MPU05_LDO_STEP2	25000
165
166#define S2MPU05_BUCK_MIN1	400000
167#define S2MPU05_BUCK_MIN2	600000
168#define S2MPU05_BUCK_STEP1	6250
169#define S2MPU05_BUCK_STEP2	12500
170
171#define S2MPU05_RAMP_DELAY	12000	/* uV/uS */
172
173#define S2MPU05_ENABLE_SHIFT	6
174#define S2MPU05_ENABLE_MASK	(0x03 << S2MPU05_ENABLE_SHIFT)
175
176#define S2MPU05_LDO_VSEL_MASK	0x3F
177#define S2MPU05_BUCK_VSEL_MASK	0xFF
178#define S2MPU05_LDO_N_VOLTAGES	(S2MPU05_LDO_VSEL_MASK + 1)
179#define S2MPU05_BUCK_N_VOLTAGES (S2MPU05_BUCK_VSEL_MASK + 1)
180
181#define S2MPU05_PMIC_EN_SHIFT	6
182
183#endif /*  __LINUX_MFD_S2MPU05_H */