s2mps14.h

  1/* SPDX-License-Identifier: GPL-2.0+ */
  2/*
  3 * Copyright (c) 2014 Samsung Electronics Co., Ltd
  4 *              http://www.samsung.com
  5 */
  6
  7#ifndef __LINUX_MFD_S2MPS14_H
  8#define __LINUX_MFD_S2MPS14_H
  9
 10/* S2MPS14 registers */
 11enum s2mps14_reg {
 12	S2MPS14_REG_ID,
 13	S2MPS14_REG_INT1,
 14	S2MPS14_REG_INT2,
 15	S2MPS14_REG_INT3,
 16	S2MPS14_REG_INT1M,
 17	S2MPS14_REG_INT2M,
 18	S2MPS14_REG_INT3M,
 19	S2MPS14_REG_ST1,
 20	S2MPS14_REG_ST2,
 21	S2MPS14_REG_PWRONSRC,
 22	S2MPS14_REG_OFFSRC,
 23	S2MPS14_REG_BU_CHG,
 24	S2MPS14_REG_RTCCTRL,
 25	S2MPS14_REG_CTRL1,
 26	S2MPS14_REG_CTRL2,
 27	S2MPS14_REG_RSVD1,
 28	S2MPS14_REG_RSVD2,
 29	S2MPS14_REG_RSVD3,
 30	S2MPS14_REG_RSVD4,
 31	S2MPS14_REG_RSVD5,
 32	S2MPS14_REG_RSVD6,
 33	S2MPS14_REG_CTRL3,
 34	S2MPS14_REG_RSVD7,
 35	S2MPS14_REG_RSVD8,
 36	S2MPS14_REG_WRSTBI,
 37	S2MPS14_REG_B1CTRL1,
 38	S2MPS14_REG_B1CTRL2,
 39	S2MPS14_REG_B2CTRL1,
 40	S2MPS14_REG_B2CTRL2,
 41	S2MPS14_REG_B3CTRL1,
 42	S2MPS14_REG_B3CTRL2,
 43	S2MPS14_REG_B4CTRL1,
 44	S2MPS14_REG_B4CTRL2,
 45	S2MPS14_REG_B5CTRL1,
 46	S2MPS14_REG_B5CTRL2,
 47	S2MPS14_REG_L1CTRL,
 48	S2MPS14_REG_L2CTRL,
 49	S2MPS14_REG_L3CTRL,
 50	S2MPS14_REG_L4CTRL,
 51	S2MPS14_REG_L5CTRL,
 52	S2MPS14_REG_L6CTRL,
 53	S2MPS14_REG_L7CTRL,
 54	S2MPS14_REG_L8CTRL,
 55	S2MPS14_REG_L9CTRL,
 56	S2MPS14_REG_L10CTRL,
 57	S2MPS14_REG_L11CTRL,
 58	S2MPS14_REG_L12CTRL,
 59	S2MPS14_REG_L13CTRL,
 60	S2MPS14_REG_L14CTRL,
 61	S2MPS14_REG_L15CTRL,
 62	S2MPS14_REG_L16CTRL,
 63	S2MPS14_REG_L17CTRL,
 64	S2MPS14_REG_L18CTRL,
 65	S2MPS14_REG_L19CTRL,
 66	S2MPS14_REG_L20CTRL,
 67	S2MPS14_REG_L21CTRL,
 68	S2MPS14_REG_L22CTRL,
 69	S2MPS14_REG_L23CTRL,
 70	S2MPS14_REG_L24CTRL,
 71	S2MPS14_REG_L25CTRL,
 72	S2MPS14_REG_LDODSCH1,
 73	S2MPS14_REG_LDODSCH2,
 74	S2MPS14_REG_LDODSCH3,
 75};
 76
 77/* S2MPS14 regulator ids */
 78enum s2mps14_regulators {
 79	S2MPS14_LDO1,
 80	S2MPS14_LDO2,
 81	S2MPS14_LDO3,
 82	S2MPS14_LDO4,
 83	S2MPS14_LDO5,
 84	S2MPS14_LDO6,
 85	S2MPS14_LDO7,
 86	S2MPS14_LDO8,
 87	S2MPS14_LDO9,
 88	S2MPS14_LDO10,
 89	S2MPS14_LDO11,
 90	S2MPS14_LDO12,
 91	S2MPS14_LDO13,
 92	S2MPS14_LDO14,
 93	S2MPS14_LDO15,
 94	S2MPS14_LDO16,
 95	S2MPS14_LDO17,
 96	S2MPS14_LDO18,
 97	S2MPS14_LDO19,
 98	S2MPS14_LDO20,
 99	S2MPS14_LDO21,
100	S2MPS14_LDO22,
101	S2MPS14_LDO23,
102	S2MPS14_LDO24,
103	S2MPS14_LDO25,
104	S2MPS14_BUCK1,
105	S2MPS14_BUCK2,
106	S2MPS14_BUCK3,
107	S2MPS14_BUCK4,
108	S2MPS14_BUCK5,
109
110	S2MPS14_REGULATOR_MAX,
111};
112
113/* Regulator constraints for BUCKx */
114#define S2MPS14_BUCK1235_START_SEL	0x20
115#define S2MPS14_BUCK4_START_SEL		0x40
116/*
117 * Default ramp delay in uv/us. Datasheet says that ramp delay can be
118 * controlled however it does not specify which register is used for that.
119 * Let's assume that default value will be set.
120 */
121#define S2MPS14_BUCK_RAMP_DELAY		12500
122
123#define S2MPS14_LDO_VSEL_MASK		0x3F
124#define S2MPS14_BUCK_VSEL_MASK		0xFF
125#define S2MPS14_ENABLE_MASK		(0x03 << S2MPS14_ENABLE_SHIFT)
126#define S2MPS14_ENABLE_SHIFT		6
127/* On/Off controlled by PWREN */
128#define S2MPS14_ENABLE_SUSPEND		(0x01 << S2MPS14_ENABLE_SHIFT)
129/* On/Off controlled by LDO10EN or EMMCEN */
130#define S2MPS14_ENABLE_EXT_CONTROL	(0x00 << S2MPS14_ENABLE_SHIFT)
131#define S2MPS14_LDO_N_VOLTAGES		(S2MPS14_LDO_VSEL_MASK + 1)
132#define S2MPS14_BUCK_N_VOLTAGES		(S2MPS14_BUCK_VSEL_MASK + 1)
133
134#endif /*  __LINUX_MFD_S2MPS14_H */