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pf1550.h

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linux-6.19.14/include/linux/mfd/pf1550.h C 
  1/* SPDX-License-Identifier: GPL-2.0
  2 *
  3 * Declarations for the PF1550 PMIC
  4 *
  5 * Copyright (C) 2016 Freescale Semiconductor, Inc.
  6 * Robin Gong <yibin.gong@freescale.com>
  7 *
  8 * Portions Copyright (c) 2025 Savoir-faire Linux Inc.
  9 * Samuel Kayode <samuel.kayode@savoirfairelinux.com>
 10 */
 11
 12#ifndef __LINUX_MFD_PF1550_H
 13#define __LINUX_MFD_PF1550_H
 14
 15#include <linux/i2c.h>
 16#include <linux/regmap.h>
 17
 18enum pf1550_pmic_reg {
 19	/* PMIC regulator part */
 20	PF1550_PMIC_REG_DEVICE_ID		= 0x00,
 21	PF1550_PMIC_REG_OTP_FLAVOR		= 0x01,
 22	PF1550_PMIC_REG_SILICON_REV		= 0x02,
 23
 24	PF1550_PMIC_REG_INT_CATEGORY		= 0x06,
 25	PF1550_PMIC_REG_SW_INT_STAT0		= 0x08,
 26	PF1550_PMIC_REG_SW_INT_MASK0		= 0x09,
 27	PF1550_PMIC_REG_SW_INT_SENSE0		= 0x0a,
 28	PF1550_PMIC_REG_SW_INT_STAT1		= 0x0b,
 29	PF1550_PMIC_REG_SW_INT_MASK1		= 0x0c,
 30	PF1550_PMIC_REG_SW_INT_SENSE1		= 0x0d,
 31	PF1550_PMIC_REG_SW_INT_STAT2		= 0x0e,
 32	PF1550_PMIC_REG_SW_INT_MASK2		= 0x0f,
 33	PF1550_PMIC_REG_SW_INT_SENSE2		= 0x10,
 34	PF1550_PMIC_REG_LDO_INT_STAT0		= 0x18,
 35	PF1550_PMIC_REG_LDO_INT_MASK0		= 0x19,
 36	PF1550_PMIC_REG_LDO_INT_SENSE0		= 0x1a,
 37	PF1550_PMIC_REG_TEMP_INT_STAT0		= 0x20,
 38	PF1550_PMIC_REG_TEMP_INT_MASK0		= 0x21,
 39	PF1550_PMIC_REG_TEMP_INT_SENSE0		= 0x22,
 40	PF1550_PMIC_REG_ONKEY_INT_STAT0		= 0x24,
 41	PF1550_PMIC_REG_ONKEY_INT_MASK0		= 0x25,
 42	PF1550_PMIC_REG_ONKEY_INT_SENSE0	= 0x26,
 43	PF1550_PMIC_REG_MISC_INT_STAT0		= 0x28,
 44	PF1550_PMIC_REG_MISC_INT_MASK0		= 0x29,
 45	PF1550_PMIC_REG_MISC_INT_SENSE0		= 0x2a,
 46
 47	PF1550_PMIC_REG_COINCELL_CONTROL	= 0x30,
 48
 49	PF1550_PMIC_REG_SW1_VOLT		= 0x32,
 50	PF1550_PMIC_REG_SW1_STBY_VOLT		= 0x33,
 51	PF1550_PMIC_REG_SW1_SLP_VOLT		= 0x34,
 52	PF1550_PMIC_REG_SW1_CTRL		= 0x35,
 53	PF1550_PMIC_REG_SW1_CTRL1		= 0x36,
 54	PF1550_PMIC_REG_SW2_VOLT		= 0x38,
 55	PF1550_PMIC_REG_SW2_STBY_VOLT		= 0x39,
 56	PF1550_PMIC_REG_SW2_SLP_VOLT		= 0x3a,
 57	PF1550_PMIC_REG_SW2_CTRL		= 0x3b,
 58	PF1550_PMIC_REG_SW2_CTRL1		= 0x3c,
 59	PF1550_PMIC_REG_SW3_VOLT		= 0x3e,
 60	PF1550_PMIC_REG_SW3_STBY_VOLT		= 0x3f,
 61	PF1550_PMIC_REG_SW3_SLP_VOLT		= 0x40,
 62	PF1550_PMIC_REG_SW3_CTRL		= 0x41,
 63	PF1550_PMIC_REG_SW3_CTRL1		= 0x42,
 64	PF1550_PMIC_REG_VSNVS_CTRL		= 0x48,
 65	PF1550_PMIC_REG_VREFDDR_CTRL		= 0x4a,
 66	PF1550_PMIC_REG_LDO1_VOLT		= 0x4c,
 67	PF1550_PMIC_REG_LDO1_CTRL		= 0x4d,
 68	PF1550_PMIC_REG_LDO2_VOLT		= 0x4f,
 69	PF1550_PMIC_REG_LDO2_CTRL		= 0x50,
 70	PF1550_PMIC_REG_LDO3_VOLT		= 0x52,
 71	PF1550_PMIC_REG_LDO3_CTRL		= 0x53,
 72	PF1550_PMIC_REG_PWRCTRL0		= 0x58,
 73	PF1550_PMIC_REG_PWRCTRL1		= 0x59,
 74	PF1550_PMIC_REG_PWRCTRL2		= 0x5a,
 75	PF1550_PMIC_REG_PWRCTRL3		= 0x5b,
 76	PF1550_PMIC_REG_SW1_PWRDN_SEQ		= 0x5f,
 77	PF1550_PMIC_REG_SW2_PWRDN_SEQ		= 0x60,
 78	PF1550_PMIC_REG_SW3_PWRDN_SEQ		= 0x61,
 79	PF1550_PMIC_REG_LDO1_PWRDN_SEQ		= 0x62,
 80	PF1550_PMIC_REG_LDO2_PWRDN_SEQ		= 0x63,
 81	PF1550_PMIC_REG_LDO3_PWRDN_SEQ		= 0x64,
 82	PF1550_PMIC_REG_VREFDDR_PWRDN_SEQ	= 0x65,
 83
 84	PF1550_PMIC_REG_STATE_INFO		= 0x67,
 85	PF1550_PMIC_REG_I2C_ADDR		= 0x68,
 86	PF1550_PMIC_REG_IO_DRV0			= 0x69,
 87	PF1550_PMIC_REG_IO_DRV1			= 0x6a,
 88	PF1550_PMIC_REG_RC_16MHZ		= 0x6b,
 89	PF1550_PMIC_REG_KEY			= 0x6f,
 90
 91	/* Charger part */
 92	PF1550_CHARG_REG_CHG_INT		= 0x80,
 93	PF1550_CHARG_REG_CHG_INT_MASK		= 0x82,
 94	PF1550_CHARG_REG_CHG_INT_OK		= 0x84,
 95	PF1550_CHARG_REG_VBUS_SNS		= 0x86,
 96	PF1550_CHARG_REG_CHG_SNS		= 0x87,
 97	PF1550_CHARG_REG_BATT_SNS		= 0x88,
 98	PF1550_CHARG_REG_CHG_OPER		= 0x89,
 99	PF1550_CHARG_REG_CHG_TMR		= 0x8a,
100	PF1550_CHARG_REG_CHG_EOC_CNFG		= 0x8d,
101	PF1550_CHARG_REG_CHG_CURR_CNFG		= 0x8e,
102	PF1550_CHARG_REG_BATT_REG		= 0x8f,
103	PF1550_CHARG_REG_BATFET_CNFG		= 0x91,
104	PF1550_CHARG_REG_THM_REG_CNFG		= 0x92,
105	PF1550_CHARG_REG_VBUS_INLIM_CNFG	= 0x94,
106	PF1550_CHARG_REG_VBUS_LIN_DPM		= 0x95,
107	PF1550_CHARG_REG_USB_PHY_LDO_CNFG	= 0x96,
108	PF1550_CHARG_REG_DBNC_DELAY_TIME	= 0x98,
109	PF1550_CHARG_REG_CHG_INT_CNFG		= 0x99,
110	PF1550_CHARG_REG_THM_ADJ_SETTING	= 0x9a,
111	PF1550_CHARG_REG_VBUS2SYS_CNFG		= 0x9b,
112	PF1550_CHARG_REG_LED_PWM		= 0x9c,
113	PF1550_CHARG_REG_FAULT_BATFET_CNFG	= 0x9d,
114	PF1550_CHARG_REG_LED_CNFG		= 0x9e,
115	PF1550_CHARG_REG_CHGR_KEY2		= 0x9f,
116
117	PF1550_TEST_REG_FMRADDR			= 0xc4,
118	PF1550_TEST_REG_FMRDATA			= 0xc5,
119	PF1550_TEST_REG_KEY3			= 0xdf,
120
121	PF1550_PMIC_REG_END			= 0xff,
122};
123
124/* One-Time Programmable(OTP) memory */
125enum pf1550_otp_reg {
126	PF1550_OTP_SW1_SW2			= 0x1e,
127	PF1550_OTP_SW2_SW3			= 0x1f,
128};
129
130#define PF1550_DEVICE_ID		0x7c
131
132/* Keys for reading OTP */
133#define PF1550_OTP_PMIC_KEY		0x15
134#define PF1550_OTP_CHGR_KEY		0x50
135#define PF1550_OTP_TEST_KEY		0xab
136
137/* Supported charger modes */
138#define PF1550_CHG_BAT_OFF		1
139#define PF1550_CHG_BAT_ON		2
140
141#define PF1550_CHG_PRECHARGE		0
142#define PF1550_CHG_CONSTANT_CURRENT	1
143#define PF1550_CHG_CONSTANT_VOL		2
144#define PF1550_CHG_EOC			3
145#define PF1550_CHG_DONE			4
146#define PF1550_CHG_TIMER_FAULT		6
147#define PF1550_CHG_SUSPEND		7
148#define PF1550_CHG_OFF_INV		8
149#define PF1550_CHG_BAT_OVER		9
150#define PF1550_CHG_OFF_TEMP		10
151#define PF1550_CHG_LINEAR_ONLY		12
152#define PF1550_CHG_SNS_MASK		0xf
153#define PF1550_CHG_INT_MASK		0x51
154
155#define PF1550_BAT_NO_VBUS		0
156#define PF1550_BAT_LOW_THAN_PRECHARG	1
157#define PF1550_BAT_CHARG_FAIL		2
158#define PF1550_BAT_HIGH_THAN_PRECHARG	4
159#define PF1550_BAT_OVER_VOL		5
160#define PF1550_BAT_NO_DETECT		6
161#define PF1550_BAT_SNS_MASK		0x7
162
163#define PF1550_VBUS_UVLO		BIT(2)
164#define PF1550_VBUS_IN2SYS		BIT(3)
165#define PF1550_VBUS_OVLO		BIT(4)
166#define PF1550_VBUS_VALID		BIT(5)
167
168#define PF1550_CHARG_REG_BATT_REG_CHGCV_MASK		0x3f
169#define PF1550_CHARG_REG_BATT_REG_VMINSYS_SHIFT		6
170#define PF1550_CHARG_REG_BATT_REG_VMINSYS_MASK		GENMASK(7, 6)
171#define PF1550_CHARG_REG_THM_REG_CNFG_REGTEMP_SHIFT	2
172#define PF1550_CHARG_REG_THM_REG_CNFG_REGTEMP_MASK	GENMASK(3, 2)
173
174#define PF1550_ONKEY_RST_EN		BIT(7)
175
176/* DVS enable masks */
177#define OTP_SW1_DVS_ENB		BIT(1)
178#define OTP_SW2_DVS_ENB		BIT(3)
179
180/* Top level interrupt masks */
181#define IRQ_REGULATOR		(BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(6))
182#define IRQ_ONKEY		BIT(5)
183#define IRQ_CHG			BIT(0)
184
185/* Regulator interrupt masks */
186#define PMIC_IRQ_SW1_LS		BIT(0)
187#define PMIC_IRQ_SW2_LS		BIT(1)
188#define PMIC_IRQ_SW3_LS		BIT(2)
189#define PMIC_IRQ_SW1_HS		BIT(0)
190#define PMIC_IRQ_SW2_HS		BIT(1)
191#define PMIC_IRQ_SW3_HS		BIT(2)
192#define PMIC_IRQ_LDO1_FAULT	BIT(0)
193#define PMIC_IRQ_LDO2_FAULT	BIT(1)
194#define PMIC_IRQ_LDO3_FAULT	BIT(2)
195#define PMIC_IRQ_TEMP_110	BIT(0)
196#define PMIC_IRQ_TEMP_125	BIT(1)
197
198/* Onkey interrupt masks */
199#define ONKEY_IRQ_PUSHI		BIT(0)
200#define ONKEY_IRQ_1SI		BIT(1)
201#define ONKEY_IRQ_2SI		BIT(2)
202#define ONKEY_IRQ_3SI		BIT(3)
203#define ONKEY_IRQ_4SI		BIT(4)
204#define ONKEY_IRQ_8SI		BIT(5)
205
206/* Charger interrupt masks */
207#define CHARG_IRQ_BAT2SOCI	BIT(1)
208#define CHARG_IRQ_BATI		BIT(2)
209#define CHARG_IRQ_CHGI		BIT(3)
210#define CHARG_IRQ_VBUSI		BIT(5)
211#define CHARG_IRQ_DPMI		BIT(6)
212#define CHARG_IRQ_THMI		BIT(7)
213
214enum pf1550_irq {
215	PF1550_IRQ_CHG,
216	PF1550_IRQ_REGULATOR,
217	PF1550_IRQ_ONKEY,
218};
219
220enum pf1550_pmic_irq {
221	PF1550_PMIC_IRQ_SW1_LS,
222	PF1550_PMIC_IRQ_SW2_LS,
223	PF1550_PMIC_IRQ_SW3_LS,
224	PF1550_PMIC_IRQ_SW1_HS,
225	PF1550_PMIC_IRQ_SW2_HS,
226	PF1550_PMIC_IRQ_SW3_HS,
227	PF1550_PMIC_IRQ_LDO1_FAULT,
228	PF1550_PMIC_IRQ_LDO2_FAULT,
229	PF1550_PMIC_IRQ_LDO3_FAULT,
230	PF1550_PMIC_IRQ_TEMP_110,
231	PF1550_PMIC_IRQ_TEMP_125,
232};
233
234enum pf1550_onkey_irq {
235	PF1550_ONKEY_IRQ_PUSHI,
236	PF1550_ONKEY_IRQ_1SI,
237	PF1550_ONKEY_IRQ_2SI,
238	PF1550_ONKEY_IRQ_3SI,
239	PF1550_ONKEY_IRQ_4SI,
240	PF1550_ONKEY_IRQ_8SI,
241};
242
243enum pf1550_charg_irq {
244	PF1550_CHARG_IRQ_BAT2SOCI,
245	PF1550_CHARG_IRQ_BATI,
246	PF1550_CHARG_IRQ_CHGI,
247	PF1550_CHARG_IRQ_VBUSI,
248	PF1550_CHARG_IRQ_THMI,
249};
250
251enum pf1550_regulators {
252	PF1550_SW1,
253	PF1550_SW2,
254	PF1550_SW3,
255	PF1550_VREFDDR,
256	PF1550_LDO1,
257	PF1550_LDO2,
258	PF1550_LDO3,
259};
260
261struct pf1550_ddata {
262	struct regmap_irq_chip_data *irq_data_regulator;
263	struct regmap_irq_chip_data *irq_data_charger;
264	struct regmap_irq_chip_data *irq_data_onkey;
265	struct regmap_irq_chip_data *irq_data;
266	struct regmap *regmap;
267	struct device *dev;
268	bool dvs1_enable;
269	bool dvs2_enable;
270	int irq;
271};
272
273#endif /* __LINUX_MFD_PF1550_H */
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