idt82p33_reg.h

  1/* SPDX-License-Identifier: GPL-2.0+ */
  2/*
  3 * Register Map - Based on AN888_SMUforIEEE_SynchEther_82P33xxx_RevH.pdf
  4 *
  5 * Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company.
  6 */
  7#ifndef HAVE_IDT82P33_REG
  8#define HAVE_IDT82P33_REG
  9
 10#define REG_ADDR(page, offset) (((page) << 0x7) | ((offset) & 0x7f))
 11
 12/* Register address */
 13#define DPLL1_TOD_CNFG 0x134
 14#define DPLL2_TOD_CNFG 0x1B4
 15
 16#define DPLL1_TOD_STS 0x10B
 17#define DPLL2_TOD_STS 0x18B
 18
 19#define DPLL1_TOD_TRIGGER 0x115
 20#define DPLL2_TOD_TRIGGER 0x195
 21
 22#define DPLL1_OPERATING_MODE_CNFG 0x120
 23#define DPLL2_OPERATING_MODE_CNFG 0x1A0
 24
 25#define DPLL1_HOLDOVER_FREQ_CNFG 0x12C
 26#define DPLL2_HOLDOVER_FREQ_CNFG 0x1AC
 27
 28#define DPLL1_PHASE_OFFSET_CNFG 0x143
 29#define DPLL2_PHASE_OFFSET_CNFG 0x1C3
 30
 31#define DPLL1_SYNC_EDGE_CNFG 0x140
 32#define DPLL2_SYNC_EDGE_CNFG 0x1C0
 33
 34#define DPLL1_INPUT_MODE_CNFG 0x116
 35#define DPLL2_INPUT_MODE_CNFG 0x196
 36
 37#define DPLL1_OPERATING_STS 0x102
 38#define DPLL2_OPERATING_STS 0x182
 39
 40#define DPLL1_CURRENT_FREQ_STS 0x103
 41#define DPLL2_CURRENT_FREQ_STS 0x183
 42
 43#define REG_SOFT_RESET 0X381
 44
 45#define OUT_MUX_CNFG(outn) REG_ADDR(0x6, (0xC * (outn)))
 46#define TOD_TRIGGER(wr_trig, rd_trig) ((wr_trig & 0xf) << 4 | (rd_trig & 0xf))
 47
 48/* Register bit definitions */
 49#define SYNC_TOD BIT(1)
 50#define PH_OFFSET_EN BIT(7)
 51#define SQUELCH_ENABLE BIT(5)
 52
 53/* Bit definitions for the DPLL_MODE register */
 54#define PLL_MODE_SHIFT		(0)
 55#define PLL_MODE_MASK		(0x1F)
 56#define COMBO_MODE_EN		BIT(5)
 57#define COMBO_MODE_SHIFT	(6)
 58#define COMBO_MODE_MASK		(0x3)
 59
 60/* Bit definitions for DPLL_OPERATING_STS register */
 61#define OPERATING_STS_MASK	(0x7)
 62#define OPERATING_STS_SHIFT	(0x0)
 63
 64/* Bit definitions for DPLL_TOD_TRIGGER register */
 65#define READ_TRIGGER_MASK	(0xF)
 66#define READ_TRIGGER_SHIFT	(0x0)
 67#define WRITE_TRIGGER_MASK	(0xF0)
 68#define WRITE_TRIGGER_SHIFT	(0x4)
 69
 70/* Bit definitions for REG_SOFT_RESET register */
 71#define SOFT_RESET_EN		BIT(7)
 72
 73enum pll_mode {
 74	PLL_MODE_MIN = 0,
 75	PLL_MODE_AUTOMATIC = PLL_MODE_MIN,
 76	PLL_MODE_FORCE_FREERUN = 1,
 77	PLL_MODE_FORCE_HOLDOVER = 2,
 78	PLL_MODE_FORCE_LOCKED = 4,
 79	PLL_MODE_FORCE_PRE_LOCKED2 = 5,
 80	PLL_MODE_FORCE_PRE_LOCKED = 6,
 81	PLL_MODE_FORCE_LOST_PHASE = 7,
 82	PLL_MODE_DCO = 10,
 83	PLL_MODE_WPH = 18,
 84	PLL_MODE_MAX = PLL_MODE_WPH,
 85};
 86
 87enum hw_tod_trig_sel {
 88	HW_TOD_TRIG_SEL_MIN = 0,
 89	HW_TOD_TRIG_SEL_NO_WRITE = HW_TOD_TRIG_SEL_MIN,
 90	HW_TOD_TRIG_SEL_NO_READ = HW_TOD_TRIG_SEL_MIN,
 91	HW_TOD_TRIG_SEL_SYNC_SEL = 1,
 92	HW_TOD_TRIG_SEL_IN12 = 2,
 93	HW_TOD_TRIG_SEL_IN13 = 3,
 94	HW_TOD_TRIG_SEL_IN14 = 4,
 95	HW_TOD_TRIG_SEL_TOD_PPS = 5,
 96	HW_TOD_TRIG_SEL_TIMER_INTERVAL = 6,
 97	HW_TOD_TRIG_SEL_MSB_PHASE_OFFSET_CNFG = 7,
 98	HW_TOD_TRIG_SEL_MSB_HOLDOVER_FREQ_CNFG = 8,
 99	HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG = 9,
100	HW_TOD_RD_TRIG_SEL_LSB_TOD_STS = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
101	WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
102};
103
104/** @brief Enumerated type listing DPLL operational modes */
105enum dpll_state {
106	DPLL_STATE_FREERUN = 1,
107	DPLL_STATE_HOLDOVER = 2,
108	DPLL_STATE_LOCKED = 4,
109	DPLL_STATE_PRELOCKED2 = 5,
110	DPLL_STATE_PRELOCKED = 6,
111	DPLL_STATE_LOSTPHASE = 7,
112	DPLL_STATE_MAX
113};
114
115#endif