davinci_voicecodec.h

  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 * DaVinci Voice Codec Core Interface for TI platforms
  4 *
  5 * Copyright (C) 2010 Texas Instruments, Inc
  6 *
  7 * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
  8 */
  9
 10#ifndef __LINUX_MFD_DAVINCI_VOICECODEC_H_
 11#define __LINUX_MFD_DAVINCI_VOICECODEC_H_
 12
 13#include <linux/bits.h>
 14#include <linux/mfd/core.h>
 15#include <linux/types.h>
 16
 17struct clk;
 18struct device;
 19struct platform_device;
 20struct regmap;
 21
 22/*
 23 * Register values.
 24 */
 25#define DAVINCI_VC_PID			0x00
 26#define DAVINCI_VC_CTRL			0x04
 27#define DAVINCI_VC_INTEN		0x08
 28#define DAVINCI_VC_INTSTATUS		0x0c
 29#define DAVINCI_VC_INTCLR		0x10
 30#define DAVINCI_VC_EMUL_CTRL		0x14
 31#define DAVINCI_VC_RFIFO		0x20
 32#define DAVINCI_VC_WFIFO		0x24
 33#define DAVINCI_VC_FIFOSTAT		0x28
 34#define DAVINCI_VC_TST_CTRL		0x2C
 35#define DAVINCI_VC_REG05		0x94
 36#define DAVINCI_VC_REG09		0xA4
 37#define DAVINCI_VC_REG12		0xB0
 38
 39/* DAVINCI_VC_CTRL bit fields */
 40#define DAVINCI_VC_CTRL_MASK		0x5500
 41#define DAVINCI_VC_CTRL_RSTADC		BIT(0)
 42#define DAVINCI_VC_CTRL_RSTDAC		BIT(1)
 43#define DAVINCI_VC_CTRL_RD_BITS_8	BIT(4)
 44#define DAVINCI_VC_CTRL_RD_UNSIGNED	BIT(5)
 45#define DAVINCI_VC_CTRL_WD_BITS_8	BIT(6)
 46#define DAVINCI_VC_CTRL_WD_UNSIGNED	BIT(7)
 47#define DAVINCI_VC_CTRL_RFIFOEN		BIT(8)
 48#define DAVINCI_VC_CTRL_RFIFOCL		BIT(9)
 49#define DAVINCI_VC_CTRL_RFIFOMD_WORD_1	BIT(10)
 50#define DAVINCI_VC_CTRL_WFIFOEN		BIT(12)
 51#define DAVINCI_VC_CTRL_WFIFOCL		BIT(13)
 52#define DAVINCI_VC_CTRL_WFIFOMD_WORD_1	BIT(14)
 53
 54/* DAVINCI_VC_INT bit fields */
 55#define DAVINCI_VC_INT_MASK		0x3F
 56#define DAVINCI_VC_INT_RDRDY_MASK	BIT(0)
 57#define DAVINCI_VC_INT_RERROVF_MASK	BIT(1)
 58#define DAVINCI_VC_INT_RERRUDR_MASK	BIT(2)
 59#define DAVINCI_VC_INT_WDREQ_MASK	BIT(3)
 60#define DAVINCI_VC_INT_WERROVF_MASKBIT	BIT(4)
 61#define DAVINCI_VC_INT_WERRUDR_MASK	BIT(5)
 62
 63/* DAVINCI_VC_REG05 bit fields */
 64#define DAVINCI_VC_REG05_PGA_GAIN	0x07
 65
 66/* DAVINCI_VC_REG09 bit fields */
 67#define DAVINCI_VC_REG09_MUTE		0x40
 68#define DAVINCI_VC_REG09_DIG_ATTEN	0x3F
 69
 70/* DAVINCI_VC_REG12 bit fields */
 71#define DAVINCI_VC_REG12_POWER_ALL_ON	0xFD
 72#define DAVINCI_VC_REG12_POWER_ALL_OFF	0x00
 73
 74#define DAVINCI_VC_CELLS		2
 75
 76enum davinci_vc_cells {
 77	DAVINCI_VC_VCIF_CELL,
 78	DAVINCI_VC_CQ93VC_CELL,
 79};
 80
 81struct davinci_vcif {
 82	struct platform_device	*pdev;
 83	u32 dma_tx_channel;
 84	u32 dma_rx_channel;
 85	dma_addr_t dma_tx_addr;
 86	dma_addr_t dma_rx_addr;
 87};
 88
 89struct davinci_vc {
 90	/* Device data */
 91	struct device *dev;
 92	struct platform_device *pdev;
 93	struct clk *clk;
 94
 95	/* Memory resources */
 96	void __iomem *base;
 97	struct regmap *regmap;
 98
 99	/* MFD cells */
100	struct mfd_cell cells[DAVINCI_VC_CELLS];
101
102	/* Client devices */
103	struct davinci_vcif davinci_vcif;
104};
105
106#endif