arm-gic-v3-prio.h

 1/* SPDX-License-Identifier: GPL-2.0-only */
 2
 3#ifndef __LINUX_IRQCHIP_ARM_GIC_V3_PRIO_H
 4#define __LINUX_IRQCHIP_ARM_GIC_V3_PRIO_H
 5
 6/*
 7 * GIC priorities from the view of the PMR/RPR.
 8 *
 9 * These values are chosen to be valid in either the absolute priority space or
10 * the NS view of the priority space. The value programmed into the distributor
11 * and ITS will be chosen at boot time such that these values appear in the
12 * PMR/RPR.
13 *
14 * GICV3_PRIO_UNMASKED is the PMR view of the priority to use to permit both
15 * IRQs and pseudo-NMIs.
16 *
17 * GICV3_PRIO_IRQ is the PMR view of the priority of regular interrupts. This
18 * can be written to the PMR to mask regular IRQs.
19 *
20 * GICV3_PRIO_NMI is the PMR view of the priority of pseudo-NMIs. This can be
21 * written to the PMR to mask pseudo-NMIs.
22 *
23 * On arm64 some code sections either automatically switch back to PSR.I or
24 * explicitly require to not use priority masking. If bit GICV3_PRIO_PSR_I_SET
25 * is included in the priority mask, it indicates that PSR.I should be set and
26 * interrupt disabling temporarily does not rely on IRQ priorities.
27 */
28#define GICV3_PRIO_UNMASKED	0xe0
29#define GICV3_PRIO_IRQ		0xc0
30#define GICV3_PRIO_NMI		0x80
31
32#define GICV3_PRIO_PSR_I_SET	(1 << 4)
33
34#ifndef __ASSEMBLER__
35
36#define __gicv3_prio_to_ns(p)	(0xff & ((p) << 1))
37#define __gicv3_ns_to_prio(ns)	(0x80 | ((ns) >> 1))
38
39#define __gicv3_prio_valid_ns(p) \
40	(__gicv3_ns_to_prio(__gicv3_prio_to_ns(p)) == (p))
41
42static_assert(__gicv3_prio_valid_ns(GICV3_PRIO_NMI));
43static_assert(__gicv3_prio_valid_ns(GICV3_PRIO_IRQ));
44
45static_assert(GICV3_PRIO_NMI < GICV3_PRIO_IRQ);
46static_assert(GICV3_PRIO_IRQ < GICV3_PRIO_UNMASKED);
47
48static_assert(GICV3_PRIO_IRQ < (GICV3_PRIO_IRQ | GICV3_PRIO_PSR_I_SET));
49
50#endif /* __ASSEMBLER */
51
52#endif /* __LINUX_IRQCHIP_ARM_GIC_V3_PRIO_H */