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cpucp_if.h
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linux-6.19.14/include/linux/habanalabs/cpucp_if.h
1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2020-2023 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8#ifndef CPUCP_IF_H 9#define CPUCP_IF_H 10 11#include <linux/types.h> 12#include <linux/if_ether.h> 13 14#include "hl_boot_if.h" 15 16#define NUM_HBM_PSEUDO_CH 2 17#define NUM_HBM_CH_PER_DEV 8 18#define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_SHIFT 0 19#define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_MASK 0x00000001 20#define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_SHIFT 1 21#define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_MASK 0x00000002 22#define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_SHIFT 2 23#define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_MASK 0x00000004 24#define CPUCP_PKT_HBM_ECC_INFO_DERR_SHIFT 3 25#define CPUCP_PKT_HBM_ECC_INFO_DERR_MASK 0x00000008 26#define CPUCP_PKT_HBM_ECC_INFO_SERR_SHIFT 4 27#define CPUCP_PKT_HBM_ECC_INFO_SERR_MASK 0x00000010 28#define CPUCP_PKT_HBM_ECC_INFO_TYPE_SHIFT 5 29#define CPUCP_PKT_HBM_ECC_INFO_TYPE_MASK 0x00000020 30#define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_SHIFT 6 31#define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_MASK 0x000007C0 32 33#define PLL_MAP_MAX_BITS 128 34#define PLL_MAP_LEN (PLL_MAP_MAX_BITS / 8) 35 36enum eq_event_id { 37 EQ_EVENT_NIC_STS_REQUEST = 0, 38 EQ_EVENT_PWR_MODE_0, 39 EQ_EVENT_PWR_MODE_1, 40 EQ_EVENT_PWR_MODE_2, 41 EQ_EVENT_PWR_MODE_3, 42 EQ_EVENT_PWR_BRK_ENTRY, 43 EQ_EVENT_PWR_BRK_EXIT, 44 EQ_EVENT_HEARTBEAT, 45 EQ_EVENT_CPLD_RESET_REASON, 46 EQ_EVENT_CPLD_SHUTDOWN, 47 EQ_EVENT_POWER_EVT_START, 48 EQ_EVENT_POWER_EVT_END, 49 EQ_EVENT_THERMAL_EVT_START, 50 EQ_EVENT_THERMAL_EVT_END, 51}; 52 53/* 54 * info of the pkt queue pointers in the first async occurrence 55 */ 56struct cpucp_pkt_sync_err { 57 __le32 pi; 58 __le32 ci; 59}; 60 61struct hl_eq_hbm_ecc_data { 62 /* SERR counter */ 63 __le32 sec_cnt; 64 /* DERR counter */ 65 __le32 dec_cnt; 66 /* Supplemental Information according to the mask bits */ 67 __le32 hbm_ecc_info; 68 /* Address in hbm where the ecc happened */ 69 __le32 first_addr; 70 /* SERR continuous address counter */ 71 __le32 sec_cont_cnt; 72 __le32 pad; 73}; 74 75/* 76 * EVENT QUEUE 77 */ 78 79struct hl_eq_header { 80 __le32 reserved; 81 __le32 ctl; 82}; 83 84struct hl_eq_ecc_data { 85 __le64 ecc_address; 86 __le64 ecc_syndrom; 87 __u8 memory_wrapper_idx; 88 __u8 is_critical; 89 __le16 block_id; 90 __u8 pad[4]; 91}; 92 93enum hl_sm_sei_cause { 94 SM_SEI_SO_OVERFLOW, 95 SM_SEI_LBW_4B_UNALIGNED, 96 SM_SEI_AXI_RESPONSE_ERR 97}; 98 99struct hl_eq_sm_sei_data { 100 __le32 sei_log; 101 /* enum hl_sm_sei_cause */ 102 __u8 sei_cause; 103 __u8 pad[3]; 104}; 105 106enum hl_fw_alive_severity { 107 FW_ALIVE_SEVERITY_MINOR, 108 FW_ALIVE_SEVERITY_CRITICAL 109}; 110 111struct hl_eq_fw_alive { 112 __le64 uptime_seconds; 113 __le32 process_id; 114 __le32 thread_id; 115 /* enum hl_fw_alive_severity */ 116 __u8 severity; 117 __u8 pad[7]; 118}; 119 120struct hl_eq_intr_cause { 121 __le64 intr_cause_data; 122}; 123 124struct hl_eq_pcie_drain_ind_data { 125 struct hl_eq_intr_cause intr_cause; 126 __le64 drain_wr_addr_lbw; 127 __le64 drain_rd_addr_lbw; 128 __le64 drain_wr_addr_hbw; 129 __le64 drain_rd_addr_hbw; 130}; 131 132struct hl_eq_razwi_lbw_info_regs { 133 __le32 rr_aw_razwi_reg; 134 __le32 rr_aw_razwi_id_reg; 135 __le32 rr_ar_razwi_reg; 136 __le32 rr_ar_razwi_id_reg; 137}; 138 139struct hl_eq_razwi_hbw_info_regs { 140 __le32 rr_aw_razwi_hi_reg; 141 __le32 rr_aw_razwi_lo_reg; 142 __le32 rr_aw_razwi_id_reg; 143 __le32 rr_ar_razwi_hi_reg; 144 __le32 rr_ar_razwi_lo_reg; 145 __le32 rr_ar_razwi_id_reg; 146}; 147 148/* razwi_happened masks */ 149#define RAZWI_HAPPENED_HBW 0x1 150#define RAZWI_HAPPENED_LBW 0x2 151#define RAZWI_HAPPENED_AW 0x4 152#define RAZWI_HAPPENED_AR 0x8 153 154struct hl_eq_razwi_info { 155 __le32 razwi_happened_mask; 156 union { 157 struct hl_eq_razwi_lbw_info_regs lbw; 158 struct hl_eq_razwi_hbw_info_regs hbw; 159 }; 160 __le32 pad; 161}; 162 163struct hl_eq_razwi_with_intr_cause { 164 struct hl_eq_razwi_info razwi_info; 165 struct hl_eq_intr_cause intr_cause; 166}; 167 168#define HBM_CA_ERR_CMD_LIFO_LEN 8 169#define HBM_RD_ERR_DATA_LIFO_LEN 8 170#define HBM_WR_PAR_CMD_LIFO_LEN 11 171 172enum hl_hbm_sei_cause { 173 /* Command/address parity error event is split into 2 events due to 174 * size limitation: ODD suffix for odd HBM CK_t cycles and EVEN suffix 175 * for even HBM CK_t cycles 176 */ 177 HBM_SEI_CMD_PARITY_EVEN, 178 HBM_SEI_CMD_PARITY_ODD, 179 /* Read errors can be reflected as a combination of SERR/DERR/parity 180 * errors. Therefore, we define one event for all read error types. 181 * LKD will perform further proccessing. 182 */ 183 HBM_SEI_READ_ERR, 184 HBM_SEI_WRITE_DATA_PARITY_ERR, 185 HBM_SEI_CATTRIP, 186 HBM_SEI_MEM_BIST_FAIL, 187 HBM_SEI_DFI, 188 HBM_SEI_INV_TEMP_READ_OUT, 189 HBM_SEI_BIST_FAIL, 190}; 191 192/* Masks for parsing hl_hbm_sei_headr fields */ 193#define HBM_ECC_SERR_CNTR_MASK 0xFF 194#define HBM_ECC_DERR_CNTR_MASK 0xFF00 195#define HBM_RD_PARITY_CNTR_MASK 0xFF0000 196 197/* HBM index and MC index are known by the event_id */ 198struct hl_hbm_sei_header { 199 union { 200 /* relevant only in case of HBM read error */ 201 struct { 202 __u8 ecc_serr_cnt; 203 __u8 ecc_derr_cnt; 204 __u8 read_par_cnt; 205 __u8 reserved; 206 }; 207 /* All other cases */ 208 __le32 cnt; 209 }; 210 __u8 sei_cause; /* enum hl_hbm_sei_cause */ 211 __u8 mc_channel; /* range: 0-3 */ 212 __u8 mc_pseudo_channel; /* range: 0-7 */ 213 __u8 is_critical; 214}; 215 216#define HBM_RD_ADDR_SID_SHIFT 0 217#define HBM_RD_ADDR_SID_MASK 0x1 218#define HBM_RD_ADDR_BG_SHIFT 1 219#define HBM_RD_ADDR_BG_MASK 0x6 220#define HBM_RD_ADDR_BA_SHIFT 3 221#define HBM_RD_ADDR_BA_MASK 0x18 222#define HBM_RD_ADDR_COL_SHIFT 5 223#define HBM_RD_ADDR_COL_MASK 0x7E0 224#define HBM_RD_ADDR_ROW_SHIFT 11 225#define HBM_RD_ADDR_ROW_MASK 0x3FFF800 226 227struct hbm_rd_addr { 228 union { 229 /* bit fields are only for FW use */ 230 struct { 231 u32 dbg_rd_err_addr_sid:1; 232 u32 dbg_rd_err_addr_bg:2; 233 u32 dbg_rd_err_addr_ba:2; 234 u32 dbg_rd_err_addr_col:6; 235 u32 dbg_rd_err_addr_row:15; 236 u32 reserved:6; 237 }; 238 __le32 rd_addr_val; 239 }; 240}; 241 242#define HBM_RD_ERR_BEAT_SHIFT 2 243/* dbg_rd_err_misc fields: */ 244/* Read parity is calculated per DW on every beat */ 245#define HBM_RD_ERR_PAR_ERR_BEAT0_SHIFT 0 246#define HBM_RD_ERR_PAR_ERR_BEAT0_MASK 0x3 247#define HBM_RD_ERR_PAR_DATA_BEAT0_SHIFT 8 248#define HBM_RD_ERR_PAR_DATA_BEAT0_MASK 0x300 249/* ECC is calculated per PC on every beat */ 250#define HBM_RD_ERR_SERR_BEAT0_SHIFT 16 251#define HBM_RD_ERR_SERR_BEAT0_MASK 0x10000 252#define HBM_RD_ERR_DERR_BEAT0_SHIFT 24 253#define HBM_RD_ERR_DERR_BEAT0_MASK 0x100000 254 255struct hl_eq_hbm_sei_read_err_intr_info { 256 /* DFI_RD_ERR_REP_ADDR */ 257 struct hbm_rd_addr dbg_rd_err_addr; 258 /* DFI_RD_ERR_REP_ERR */ 259 union { 260 struct { 261 /* bit fields are only for FW use */ 262 u32 dbg_rd_err_par:8; 263 u32 dbg_rd_err_par_data:8; 264 u32 dbg_rd_err_serr:4; 265 u32 dbg_rd_err_derr:4; 266 u32 reserved:8; 267 }; 268 __le32 dbg_rd_err_misc; 269 }; 270 /* DFI_RD_ERR_REP_DM */ 271 __le32 dbg_rd_err_dm; 272 /* DFI_RD_ERR_REP_SYNDROME */ 273 __le32 dbg_rd_err_syndrome; 274 /* DFI_RD_ERR_REP_DATA */ 275 __le32 dbg_rd_err_data[HBM_RD_ERR_DATA_LIFO_LEN]; 276}; 277 278struct hl_eq_hbm_sei_ca_par_intr_info { 279 /* 14 LSBs */ 280 __le16 dbg_row[HBM_CA_ERR_CMD_LIFO_LEN]; 281 /* 18 LSBs */ 282 __le32 dbg_col[HBM_CA_ERR_CMD_LIFO_LEN]; 283}; 284 285#define WR_PAR_LAST_CMD_COL_SHIFT 0 286#define WR_PAR_LAST_CMD_COL_MASK 0x3F 287#define WR_PAR_LAST_CMD_BG_SHIFT 6 288#define WR_PAR_LAST_CMD_BG_MASK 0xC0 289#define WR_PAR_LAST_CMD_BA_SHIFT 8 290#define WR_PAR_LAST_CMD_BA_MASK 0x300 291#define WR_PAR_LAST_CMD_SID_SHIFT 10 292#define WR_PAR_LAST_CMD_SID_MASK 0x400 293 294/* Row address isn't latched */ 295struct hbm_sei_wr_cmd_address { 296 /* DFI_DERR_LAST_CMD */ 297 union { 298 struct { 299 /* bit fields are only for FW use */ 300 u32 col:6; 301 u32 bg:2; 302 u32 ba:2; 303 u32 sid:1; 304 u32 reserved:21; 305 }; 306 __le32 dbg_wr_cmd_addr; 307 }; 308}; 309 310struct hl_eq_hbm_sei_wr_par_intr_info { 311 /* entry 0: WR command address from the 1st cycle prior to the error 312 * entry 1: WR command address from the 2nd cycle prior to the error 313 * and so on... 314 */ 315 struct hbm_sei_wr_cmd_address dbg_last_wr_cmds[HBM_WR_PAR_CMD_LIFO_LEN]; 316 /* derr[0:1] - 1st HBM cycle DERR output 317 * derr[2:3] - 2nd HBM cycle DERR output 318 */ 319 __u8 dbg_derr; 320 /* extend to reach 8B */ 321 __u8 pad[3]; 322}; 323 324/* 325 * this struct represents the following sei causes: 326 * command parity, ECC double error, ECC single error, dfi error, cattrip, 327 * temperature read-out, read parity error and write parity error. 328 * some only use the header while some have extra data. 329 */ 330struct hl_eq_hbm_sei_data { 331 struct hl_hbm_sei_header hdr; 332 union { 333 struct hl_eq_hbm_sei_ca_par_intr_info ca_parity_even_info; 334 struct hl_eq_hbm_sei_ca_par_intr_info ca_parity_odd_info; 335 struct hl_eq_hbm_sei_read_err_intr_info read_err_info; 336 struct hl_eq_hbm_sei_wr_par_intr_info wr_parity_info; 337 }; 338}; 339 340/* Engine/farm arc interrupt type */ 341enum hl_engine_arc_interrupt_type { 342 /* Qman/farm ARC DCCM QUEUE FULL interrupt type */ 343 ENGINE_ARC_DCCM_QUEUE_FULL_IRQ = 1 344}; 345 346/* Data structure specifies details of payload of DCCM QUEUE FULL interrupt */ 347struct hl_engine_arc_dccm_queue_full_irq { 348 /* Queue index value which caused DCCM QUEUE FULL */ 349 __le32 queue_index; 350 __le32 pad; 351}; 352 353/* Data structure specifies details of QM/FARM ARC interrupt */ 354struct hl_eq_engine_arc_intr_data { 355 /* ARC engine id e.g. DCORE0_TPC0_QM_ARC, DCORE0_TCP1_QM_ARC */ 356 __le32 engine_id; 357 __le32 intr_type; /* enum hl_engine_arc_interrupt_type */ 358 /* More info related to the interrupt e.g. queue index 359 * incase of DCCM_QUEUE_FULL interrupt. 360 */ 361 __le64 payload; 362 __le64 pad[5]; 363}; 364 365#define ADDR_DEC_ADDRESS_COUNT_MAX 4 366 367/* Data structure specifies details of ADDR_DEC interrupt */ 368struct hl_eq_addr_dec_intr_data { 369 struct hl_eq_intr_cause intr_cause; 370 __le64 addr[ADDR_DEC_ADDRESS_COUNT_MAX]; 371 __u8 addr_cnt; 372 __u8 pad[7]; 373}; 374 375struct hl_eq_entry { 376 struct hl_eq_header hdr; 377 union { 378 __le64 data_placeholder; 379 struct hl_eq_ecc_data ecc_data; 380 struct hl_eq_hbm_ecc_data hbm_ecc_data; /* Obsolete */ 381 struct hl_eq_sm_sei_data sm_sei_data; 382 struct cpucp_pkt_sync_err pkt_sync_err; 383 struct hl_eq_fw_alive fw_alive; 384 struct hl_eq_intr_cause intr_cause; 385 struct hl_eq_pcie_drain_ind_data pcie_drain_ind_data; 386 struct hl_eq_razwi_info razwi_info; 387 struct hl_eq_razwi_with_intr_cause razwi_with_intr_cause; 388 struct hl_eq_hbm_sei_data sei_data; /* Gaudi2 HBM */ 389 struct hl_eq_engine_arc_intr_data arc_data; 390 struct hl_eq_addr_dec_intr_data addr_dec; 391 __le64 data[7]; 392 }; 393}; 394 395#define HL_EQ_ENTRY_SIZE sizeof(struct hl_eq_entry) 396 397#define EQ_CTL_READY_SHIFT 31 398#define EQ_CTL_READY_MASK 0x80000000 399 400#define EQ_CTL_EVENT_MODE_SHIFT 28 401#define EQ_CTL_EVENT_MODE_MASK 0x70000000 402 403#define EQ_CTL_EVENT_TYPE_SHIFT 16 404#define EQ_CTL_EVENT_TYPE_MASK 0x0FFF0000 405 406#define EQ_CTL_INDEX_SHIFT 0 407#define EQ_CTL_INDEX_MASK 0x0000FFFF 408 409enum pq_init_status { 410 PQ_INIT_STATUS_NA = 0, 411 PQ_INIT_STATUS_READY_FOR_CP, 412 PQ_INIT_STATUS_READY_FOR_HOST, 413 PQ_INIT_STATUS_READY_FOR_CP_SINGLE_MSI, 414 PQ_INIT_STATUS_LEN_NOT_POWER_OF_TWO_ERR, 415 PQ_INIT_STATUS_ILLEGAL_Q_ADDR_ERR 416}; 417 418/* 419 * CpuCP Primary Queue Packets 420 * 421 * During normal operation, the host's kernel driver needs to send various 422 * messages to CpuCP, usually either to SET some value into a H/W periphery or 423 * to GET the current value of some H/W periphery. For example, SET the 424 * frequency of MME/TPC and GET the value of the thermal sensor. 425 * 426 * These messages can be initiated either by the User application or by the 427 * host's driver itself, e.g. power management code. In either case, the 428 * communication from the host's driver to CpuCP will *always* be in 429 * synchronous mode, meaning that the host will send a single message and poll 430 * until the message was acknowledged and the results are ready (if results are 431 * needed). 432 * 433 * This means that only a single message can be sent at a time and the host's 434 * driver must wait for its result before sending the next message. Having said 435 * that, because these are control messages which are sent in a relatively low 436 * frequency, this limitation seems acceptable. It's important to note that 437 * in case of multiple devices, messages to different devices *can* be sent 438 * at the same time. 439 * 440 * The message, inputs/outputs (if relevant) and fence object will be located 441 * on the device DDR at an address that will be determined by the host's driver. 442 * During device initialization phase, the host will pass to CpuCP that address. 443 * Most of the message types will contain inputs/outputs inside the message 444 * itself. The common part of each message will contain the opcode of the 445 * message (its type) and a field representing a fence object. 446 * 447 * When the host's driver wishes to send a message to CPU CP, it will write the 448 * message contents to the device DDR, clear the fence object and then write to 449 * the PSOC_ARC1_AUX_SW_INTR, to issue interrupt 121 to ARC Management CPU. 450 * 451 * Upon receiving the interrupt (#121), CpuCP will read the message from the 452 * DDR. In case the message is a SET operation, CpuCP will first perform the 453 * operation and then write to the fence object on the device DDR. In case the 454 * message is a GET operation, CpuCP will first fill the results section on the 455 * device DDR and then write to the fence object. If an error occurred, CpuCP 456 * will fill the rc field with the right error code. 457 * 458 * In the meantime, the host's driver will poll on the fence object. Once the 459 * host sees that the fence object is signaled, it will read the results from 460 * the device DDR (if relevant) and resume the code execution in the host's 461 * driver. 462 * 463 * To use QMAN packets, the opcode must be the QMAN opcode, shifted by 8 464 * so the value being put by the host's driver matches the value read by CpuCP 465 * 466 * Non-QMAN packets should be limited to values 1 through (2^8 - 1) 467 * 468 * Detailed description: 469 * 470 * CPUCP_PACKET_DISABLE_PCI_ACCESS - 471 * After receiving this packet the embedded CPU must NOT issue PCI 472 * transactions (read/write) towards the Host CPU. This also include 473 * sending MSI-X interrupts. 474 * This packet is usually sent before the device is moved to D3Hot state. 475 * 476 * CPUCP_PACKET_ENABLE_PCI_ACCESS - 477 * After receiving this packet the embedded CPU is allowed to issue PCI 478 * transactions towards the Host CPU, including sending MSI-X interrupts. 479 * This packet is usually send after the device is moved to D0 state. 480 * 481 * CPUCP_PACKET_TEMPERATURE_GET - 482 * Fetch the current temperature / Max / Max Hyst / Critical / 483 * Critical Hyst of a specified thermal sensor. The packet's 484 * arguments specify the desired sensor and the field to get. 485 * 486 * CPUCP_PACKET_VOLTAGE_GET - 487 * Fetch the voltage / Max / Min of a specified sensor. The packet's 488 * arguments specify the sensor and type. 489 * 490 * CPUCP_PACKET_CURRENT_GET - 491 * Fetch the current / Max / Min of a specified sensor. The packet's 492 * arguments specify the sensor and type. 493 * 494 * CPUCP_PACKET_FAN_SPEED_GET - 495 * Fetch the speed / Max / Min of a specified fan. The packet's 496 * arguments specify the sensor and type. 497 * 498 * CPUCP_PACKET_PWM_GET - 499 * Fetch the pwm value / mode of a specified pwm. The packet's 500 * arguments specify the sensor and type. 501 * 502 * CPUCP_PACKET_PWM_SET - 503 * Set the pwm value / mode of a specified pwm. The packet's 504 * arguments specify the sensor, type and value. 505 * 506 * CPUCP_PACKET_FREQUENCY_SET - 507 * Set the frequency of a specified PLL. The packet's arguments specify 508 * the PLL and the desired frequency. The actual frequency in the device 509 * might differ from the requested frequency. 510 * 511 * CPUCP_PACKET_FREQUENCY_GET - 512 * Fetch the frequency of a specified PLL. The packet's arguments specify 513 * the PLL. 514 * 515 * CPUCP_PACKET_LED_SET - 516 * Set the state of a specified led. The packet's arguments 517 * specify the led and the desired state. 518 * 519 * CPUCP_PACKET_I2C_WR - 520 * Write 32-bit value to I2C device. The packet's arguments specify the 521 * I2C bus, address and value. 522 * 523 * CPUCP_PACKET_I2C_RD - 524 * Read 32-bit value from I2C device. The packet's arguments specify the 525 * I2C bus and address. 526 * 527 * CPUCP_PACKET_INFO_GET - 528 * Fetch information from the device as specified in the packet's 529 * structure. The host's driver passes the max size it allows the CpuCP to 530 * write to the structure, to prevent data corruption in case of 531 * mismatched driver/FW versions. 532 * 533 * CPUCP_PACKET_FLASH_PROGRAM_REMOVED - this packet was removed 534 * 535 * CPUCP_PACKET_UNMASK_RAZWI_IRQ - 536 * Unmask the given IRQ. The IRQ number is specified in the value field. 537 * The packet is sent after receiving an interrupt and printing its 538 * relevant information. 539 * 540 * CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY - 541 * Unmask the given IRQs. The IRQs numbers are specified in an array right 542 * after the cpucp_packet structure, where its first element is the array 543 * length. The packet is sent after a soft reset was done in order to 544 * handle any interrupts that were sent during the reset process. 545 * 546 * CPUCP_PACKET_TEST - 547 * Test packet for CpuCP connectivity. The CPU will put the fence value 548 * in the result field. 549 * 550 * CPUCP_PACKET_FREQUENCY_CURR_GET - 551 * Fetch the current frequency of a specified PLL. The packet's arguments 552 * specify the PLL. 553 * 554 * CPUCP_PACKET_MAX_POWER_GET - 555 * Fetch the maximal power of the device. 556 * 557 * CPUCP_PACKET_MAX_POWER_SET - 558 * Set the maximal power of the device. The packet's arguments specify 559 * the power. 560 * 561 * CPUCP_PACKET_EEPROM_DATA_GET - 562 * Get EEPROM data from the CpuCP kernel. The buffer is specified in the 563 * addr field. The CPU will put the returned data size in the result 564 * field. In addition, the host's driver passes the max size it allows the 565 * CpuCP to write to the structure, to prevent data corruption in case of 566 * mismatched driver/FW versions. 567 * 568 * CPUCP_PACKET_NIC_INFO_GET - 569 * Fetch information from the device regarding the NIC. the host's driver 570 * passes the max size it allows the CpuCP to write to the structure, to 571 * prevent data corruption in case of mismatched driver/FW versions. 572 * 573 * CPUCP_PACKET_TEMPERATURE_SET - 574 * Set the value of the offset property of a specified thermal sensor. 575 * The packet's arguments specify the desired sensor and the field to 576 * set. 577 * 578 * CPUCP_PACKET_VOLTAGE_SET - 579 * Trigger the reset_history property of a specified voltage sensor. 580 * The packet's arguments specify the desired sensor and the field to 581 * set. 582 * 583 * CPUCP_PACKET_CURRENT_SET - 584 * Trigger the reset_history property of a specified current sensor. 585 * The packet's arguments specify the desired sensor and the field to 586 * set. 587 * 588 * CPUCP_PACKET_PCIE_THROUGHPUT_GET - 589 * Get throughput of PCIe. 590 * The packet's arguments specify the transaction direction (TX/RX). 591 * The window measurement is 10[msec], and the return value is in KB/sec. 592 * 593 * CPUCP_PACKET_PCIE_REPLAY_CNT_GET 594 * Replay count measures number of "replay" events, which is basicly 595 * number of retries done by PCIe. 596 * 597 * CPUCP_PACKET_TOTAL_ENERGY_GET - 598 * Total Energy is measurement of energy from the time FW Linux 599 * is loaded. It is calculated by multiplying the average power 600 * by time (passed from armcp start). The units are in MilliJouls. 601 * 602 * CPUCP_PACKET_PLL_INFO_GET - 603 * Fetch frequencies of PLL from the required PLL IP. 604 * The packet's arguments specify the device PLL type 605 * Pll type is the PLL from device pll_index enum. 606 * The result is composed of 4 outputs, each is 16-bit 607 * frequency in MHz. 608 * 609 * CPUCP_PACKET_POWER_GET - 610 * Fetch the present power consumption of the device (Current * Voltage). 611 * 612 * CPUCP_PACKET_NIC_PFC_SET - 613 * Enable/Disable the NIC PFC feature. The packet's arguments specify the 614 * NIC port, relevant lanes to configure and one bit indication for 615 * enable/disable. 616 * 617 * CPUCP_PACKET_NIC_FAULT_GET - 618 * Fetch the current indication for local/remote faults from the NIC MAC. 619 * The result is 32-bit value of the relevant register. 620 * 621 * CPUCP_PACKET_NIC_LPBK_SET - 622 * Enable/Disable the MAC loopback feature. The packet's arguments specify 623 * the NIC port, relevant lanes to configure and one bit indication for 624 * enable/disable. 625 * 626 * CPUCP_PACKET_NIC_MAC_INIT - 627 * Configure the NIC MAC channels. The packet's arguments specify the 628 * NIC port and the speed. 629 * 630 * CPUCP_PACKET_MSI_INFO_SET - 631 * set the index number for each supported msi type going from 632 * host to device 633 * 634 * CPUCP_PACKET_NIC_XPCS91_REGS_GET - 635 * Fetch the un/correctable counters values from the NIC MAC. 636 * 637 * CPUCP_PACKET_NIC_STAT_REGS_GET - 638 * Fetch various NIC MAC counters from the NIC STAT. 639 * 640 * CPUCP_PACKET_NIC_STAT_REGS_CLR - 641 * Clear the various NIC MAC counters in the NIC STAT. 642 * 643 * CPUCP_PACKET_NIC_STAT_REGS_ALL_GET - 644 * Fetch all NIC MAC counters from the NIC STAT. 645 * 646 * CPUCP_PACKET_IS_IDLE_CHECK - 647 * Check if the device is IDLE in regard to the DMA/compute engines 648 * and QMANs. The f/w will return a bitmask where each bit represents 649 * a different engine or QMAN according to enum cpucp_idle_mask. 650 * The bit will be 1 if the engine is NOT idle. 651 * 652 * CPUCP_PACKET_HBM_REPLACED_ROWS_INFO_GET - 653 * Fetch all HBM replaced-rows and prending to be replaced rows data. 654 * 655 * CPUCP_PACKET_HBM_PENDING_ROWS_STATUS - 656 * Fetch status of HBM rows pending replacement and need a reboot to 657 * be replaced. 658 * 659 * CPUCP_PACKET_POWER_SET - 660 * Resets power history of device to 0 661 * 662 * CPUCP_PACKET_ENGINE_CORE_ASID_SET - 663 * Packet to perform engine core ASID configuration 664 * 665 * CPUCP_PACKET_SEC_ATTEST_GET - 666 * Get the attestaion data that is collected during various stages of the 667 * boot sequence. the attestation data is also hashed with some unique 668 * number (nonce) provided by the host to prevent replay attacks. 669 * public key and certificate also provided as part of the FW response. 670 * 671 * CPUCP_PACKET_INFO_SIGNED_GET - 672 * Get the device information signed by the Trusted Platform device. 673 * device info data is also hashed with some unique number (nonce) provided 674 * by the host to prevent replay attacks. public key and certificate also 675 * provided as part of the FW response. 676 * 677 * CPUCP_PACKET_MONITOR_DUMP_GET - 678 * Get monitors registers dump from the CpuCP kernel. 679 * The CPU will put the registers dump in the a buffer allocated by the driver 680 * which address is passed via the CpuCp packet. In addition, the host's driver 681 * passes the max size it allows the CpuCP to write to the structure, to prevent 682 * data corruption in case of mismatched driver/FW versions. 683 * Obsolete. 684 * 685 * CPUCP_PACKET_GENERIC_PASSTHROUGH - 686 * Generic opcode for all firmware info that is only passed to host 687 * through the LKD, without getting parsed there. 688 * 689 * CPUCP_PACKET_ACTIVE_STATUS_SET - 690 * LKD sends FW indication whether device is free or in use, this indication is reported 691 * also to the BMC. 692 * 693 * CPUCP_PACKET_SOFT_RESET - 694 * Packet to perform soft-reset. 695 * 696 * CPUCP_PACKET_INTS_REGISTER - 697 * Packet to inform FW that queues have been established and LKD is ready to receive 698 * EQ events. 699 */ 700 701enum cpucp_packet_id { 702 CPUCP_PACKET_DISABLE_PCI_ACCESS = 1, /* internal */ 703 CPUCP_PACKET_ENABLE_PCI_ACCESS, /* internal */ 704 CPUCP_PACKET_TEMPERATURE_GET, /* sysfs */ 705 CPUCP_PACKET_VOLTAGE_GET, /* sysfs */ 706 CPUCP_PACKET_CURRENT_GET, /* sysfs */ 707 CPUCP_PACKET_FAN_SPEED_GET, /* sysfs */ 708 CPUCP_PACKET_PWM_GET, /* sysfs */ 709 CPUCP_PACKET_PWM_SET, /* sysfs */ 710 CPUCP_PACKET_FREQUENCY_SET, /* sysfs */ 711 CPUCP_PACKET_FREQUENCY_GET, /* sysfs */ 712 CPUCP_PACKET_LED_SET, /* debugfs */ 713 CPUCP_PACKET_I2C_WR, /* debugfs */ 714 CPUCP_PACKET_I2C_RD, /* debugfs */ 715 CPUCP_PACKET_INFO_GET, /* IOCTL */ 716 CPUCP_PACKET_FLASH_PROGRAM_REMOVED, 717 CPUCP_PACKET_UNMASK_RAZWI_IRQ, /* internal */ 718 CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY, /* internal */ 719 CPUCP_PACKET_TEST, /* internal */ 720 CPUCP_PACKET_FREQUENCY_CURR_GET, /* sysfs */ 721 CPUCP_PACKET_MAX_POWER_GET, /* sysfs */ 722 CPUCP_PACKET_MAX_POWER_SET, /* sysfs */ 723 CPUCP_PACKET_EEPROM_DATA_GET, /* sysfs */ 724 CPUCP_PACKET_NIC_INFO_GET, /* internal */ 725 CPUCP_PACKET_TEMPERATURE_SET, /* sysfs */ 726 CPUCP_PACKET_VOLTAGE_SET, /* sysfs */ 727 CPUCP_PACKET_CURRENT_SET, /* sysfs */ 728 CPUCP_PACKET_PCIE_THROUGHPUT_GET, /* internal */ 729 CPUCP_PACKET_PCIE_REPLAY_CNT_GET, /* internal */ 730 CPUCP_PACKET_TOTAL_ENERGY_GET, /* internal */ 731 CPUCP_PACKET_PLL_INFO_GET, /* internal */ 732 CPUCP_PACKET_NIC_STATUS, /* internal */ 733 CPUCP_PACKET_POWER_GET, /* internal */ 734 CPUCP_PACKET_NIC_PFC_SET, /* internal */ 735 CPUCP_PACKET_NIC_FAULT_GET, /* internal */ 736 CPUCP_PACKET_NIC_LPBK_SET, /* internal */ 737 CPUCP_PACKET_NIC_MAC_CFG, /* internal */ 738 CPUCP_PACKET_MSI_INFO_SET, /* internal */ 739 CPUCP_PACKET_NIC_XPCS91_REGS_GET, /* internal */ 740 CPUCP_PACKET_NIC_STAT_REGS_GET, /* internal */ 741 CPUCP_PACKET_NIC_STAT_REGS_CLR, /* internal */ 742 CPUCP_PACKET_NIC_STAT_REGS_ALL_GET, /* internal */ 743 CPUCP_PACKET_IS_IDLE_CHECK, /* internal */ 744 CPUCP_PACKET_HBM_REPLACED_ROWS_INFO_GET,/* internal */ 745 CPUCP_PACKET_HBM_PENDING_ROWS_STATUS, /* internal */ 746 CPUCP_PACKET_POWER_SET, /* internal */ 747 CPUCP_PACKET_RESERVED, /* not used */ 748 CPUCP_PACKET_ENGINE_CORE_ASID_SET, /* internal */ 749 CPUCP_PACKET_RESERVED2, /* not used */ 750 CPUCP_PACKET_SEC_ATTEST_GET, /* internal */ 751 CPUCP_PACKET_INFO_SIGNED_GET, /* internal */ 752 CPUCP_PACKET_RESERVED4, /* not used */ 753 CPUCP_PACKET_MONITOR_DUMP_GET, /* debugfs */ 754 CPUCP_PACKET_RESERVED5, /* not used */ 755 CPUCP_PACKET_RESERVED6, /* not used */ 756 CPUCP_PACKET_RESERVED7, /* not used */ 757 CPUCP_PACKET_GENERIC_PASSTHROUGH, /* IOCTL */ 758 CPUCP_PACKET_RESERVED8, /* not used */ 759 CPUCP_PACKET_ACTIVE_STATUS_SET, /* internal */ 760 CPUCP_PACKET_RESERVED9, /* not used */ 761 CPUCP_PACKET_RESERVED10, /* not used */ 762 CPUCP_PACKET_RESERVED11, /* not used */ 763 CPUCP_PACKET_RESERVED12, /* internal */ 764 CPUCP_PACKET_RESERVED13, /* internal */ 765 CPUCP_PACKET_SOFT_RESET, /* internal */ 766 CPUCP_PACKET_INTS_REGISTER, /* internal */ 767 CPUCP_PACKET_ID_MAX /* must be last */ 768}; 769 770#define CPUCP_PACKET_FENCE_VAL 0xFE8CE7A5 771 772#define CPUCP_PKT_CTL_RC_SHIFT 12 773#define CPUCP_PKT_CTL_RC_MASK 0x0000F000 774 775#define CPUCP_PKT_CTL_OPCODE_SHIFT 16 776#define CPUCP_PKT_CTL_OPCODE_MASK 0x1FFF0000 777 778#define CPUCP_PKT_RES_PLL_OUT0_SHIFT 0 779#define CPUCP_PKT_RES_PLL_OUT0_MASK 0x000000000000FFFFull 780#define CPUCP_PKT_RES_PLL_OUT1_SHIFT 16 781#define CPUCP_PKT_RES_PLL_OUT1_MASK 0x00000000FFFF0000ull 782#define CPUCP_PKT_RES_PLL_OUT2_SHIFT 32 783#define CPUCP_PKT_RES_PLL_OUT2_MASK 0x0000FFFF00000000ull 784#define CPUCP_PKT_RES_PLL_OUT3_SHIFT 48 785#define CPUCP_PKT_RES_PLL_OUT3_MASK 0xFFFF000000000000ull 786 787#define CPUCP_PKT_RES_EEPROM_OUT0_SHIFT 0 788#define CPUCP_PKT_RES_EEPROM_OUT0_MASK 0x000000000000FFFFull 789#define CPUCP_PKT_RES_EEPROM_OUT1_SHIFT 16 790#define CPUCP_PKT_RES_EEPROM_OUT1_MASK 0x0000000000FF0000ull 791 792#define CPUCP_PKT_VAL_PFC_IN1_SHIFT 0 793#define CPUCP_PKT_VAL_PFC_IN1_MASK 0x0000000000000001ull 794#define CPUCP_PKT_VAL_PFC_IN2_SHIFT 1 795#define CPUCP_PKT_VAL_PFC_IN2_MASK 0x000000000000001Eull 796 797#define CPUCP_PKT_VAL_LPBK_IN1_SHIFT 0 798#define CPUCP_PKT_VAL_LPBK_IN1_MASK 0x0000000000000001ull 799#define CPUCP_PKT_VAL_LPBK_IN2_SHIFT 1 800#define CPUCP_PKT_VAL_LPBK_IN2_MASK 0x000000000000001Eull 801 802#define CPUCP_PKT_VAL_MAC_CNT_IN1_SHIFT 0 803#define CPUCP_PKT_VAL_MAC_CNT_IN1_MASK 0x0000000000000001ull 804#define CPUCP_PKT_VAL_MAC_CNT_IN2_SHIFT 1 805#define CPUCP_PKT_VAL_MAC_CNT_IN2_MASK 0x00000000FFFFFFFEull 806 807/* heartbeat status bits */ 808#define CPUCP_PKT_HB_STATUS_EQ_FAULT_SHIFT 0 809#define CPUCP_PKT_HB_STATUS_EQ_FAULT_MASK 0x00000001 810 811struct cpucp_packet { 812 union { 813 __le64 value; /* For SET packets */ 814 __le64 result; /* For GET packets */ 815 __le64 addr; /* For PQ */ 816 }; 817 818 __le32 ctl; 819 820 __le32 fence; /* Signal to host that message is completed */ 821 822 union { 823 struct {/* For temperature/current/voltage/fan/pwm get/set */ 824 __le16 sensor_index; 825 __le16 type; 826 }; 827 828 struct { /* For I2C read/write */ 829 __u8 i2c_bus; 830 __u8 i2c_addr; 831 __u8 i2c_reg; 832 /* 833 * In legacy implemetations, i2c_len was not present, 834 * was unused and just added as pad. 835 * So if i2c_len is 0, it is treated as legacy 836 * and r/w 1 Byte, else if i2c_len is specified, 837 * its treated as new multibyte r/w support. 838 */ 839 __u8 i2c_len; 840 }; 841 842 struct {/* For PLL info fetch */ 843 __le16 pll_type; 844 /* TODO pll_reg is kept temporary before removal */ 845 __le16 pll_reg; 846 }; 847 848 /* For any general request */ 849 __le32 index; 850 851 /* For frequency get/set */ 852 __le32 pll_index; 853 854 /* For led set */ 855 __le32 led_index; 856 857 /* For get CpuCP info/EEPROM data/NIC info */ 858 __le32 data_max_size; 859 860 /* 861 * For any general status bitmask. Shall be used whenever the 862 * result cannot be used to hold general purpose data. 863 */ 864 __le32 status_mask; 865 }; 866 867 union { 868 /* For NIC requests */ 869 __le32 port_index; 870 871 /* For Generic packet sub index */ 872 __le32 pkt_subidx; 873 874 /* random, used once number, for security packets */ 875 __le32 nonce; 876 }; 877}; 878 879struct cpucp_unmask_irq_arr_packet { 880 struct cpucp_packet cpucp_pkt; 881 __le32 length; 882 __le32 irqs[]; 883}; 884 885struct cpucp_nic_status_packet { 886 struct cpucp_packet cpucp_pkt; 887 __le32 length; 888 __le32 data[]; 889}; 890 891struct cpucp_array_data_packet { 892 struct cpucp_packet cpucp_pkt; 893 __le32 length; 894 __le32 data[]; 895}; 896 897enum cpucp_led_index { 898 CPUCP_LED0_INDEX = 0, 899 CPUCP_LED1_INDEX, 900 CPUCP_LED2_INDEX, 901 CPUCP_LED_MAX_INDEX = CPUCP_LED2_INDEX 902}; 903 904/* 905 * enum cpucp_packet_rc - Error return code 906 * @cpucp_packet_success -> in case of success. 907 * @cpucp_packet_invalid -> this is to support first generation platforms. 908 * @cpucp_packet_fault -> in case of processing error like failing to 909 * get device binding or semaphore etc. 910 * @cpucp_packet_invalid_pkt -> when cpucp packet is un-supported. 911 * @cpucp_packet_invalid_params -> when checking parameter like length of buffer 912 * or attribute value etc. 913 * @cpucp_packet_rc_max -> It indicates size of enum so should be at last. 914 */ 915enum cpucp_packet_rc { 916 cpucp_packet_success, 917 cpucp_packet_invalid, 918 cpucp_packet_fault, 919 cpucp_packet_invalid_pkt, 920 cpucp_packet_invalid_params, 921 cpucp_packet_rc_max 922}; 923 924/* 925 * cpucp_temp_type should adhere to hwmon_temp_attributes 926 * defined in Linux kernel hwmon.h file 927 */ 928enum cpucp_temp_type { 929 cpucp_temp_input, 930 cpucp_temp_min = 4, 931 cpucp_temp_min_hyst, 932 cpucp_temp_max = 6, 933 cpucp_temp_max_hyst, 934 cpucp_temp_crit, 935 cpucp_temp_crit_hyst, 936 cpucp_temp_offset = 19, 937 cpucp_temp_lowest = 21, 938 cpucp_temp_highest = 22, 939 cpucp_temp_reset_history = 23, 940 cpucp_temp_warn = 24, 941 cpucp_temp_max_crit = 25, 942 cpucp_temp_max_warn = 26, 943}; 944 945enum cpucp_in_attributes { 946 cpucp_in_input, 947 cpucp_in_min, 948 cpucp_in_max, 949 cpucp_in_lowest = 6, 950 cpucp_in_highest = 7, 951 cpucp_in_reset_history, 952 cpucp_in_intr_alarm_a, 953 cpucp_in_intr_alarm_b, 954}; 955 956enum cpucp_curr_attributes { 957 cpucp_curr_input, 958 cpucp_curr_min, 959 cpucp_curr_max, 960 cpucp_curr_lowest = 6, 961 cpucp_curr_highest = 7, 962 cpucp_curr_reset_history 963}; 964 965enum cpucp_fan_attributes { 966 cpucp_fan_input, 967 cpucp_fan_min = 2, 968 cpucp_fan_max 969}; 970 971enum cpucp_pwm_attributes { 972 cpucp_pwm_input, 973 cpucp_pwm_enable 974}; 975 976enum cpucp_pcie_throughput_attributes { 977 cpucp_pcie_throughput_tx, 978 cpucp_pcie_throughput_rx 979}; 980 981/* TODO temporary kept before removal */ 982enum cpucp_pll_reg_attributes { 983 cpucp_pll_nr_reg, 984 cpucp_pll_nf_reg, 985 cpucp_pll_od_reg, 986 cpucp_pll_div_factor_reg, 987 cpucp_pll_div_sel_reg 988}; 989 990/* TODO temporary kept before removal */ 991enum cpucp_pll_type_attributes { 992 cpucp_pll_cpu, 993 cpucp_pll_pci, 994}; 995 996/* 997 * cpucp_power_type aligns with hwmon_power_attributes 998 * defined in Linux kernel hwmon.h file 999 */ 1000enum cpucp_power_type { 1001 CPUCP_POWER_INPUT = 8, 1002 CPUCP_POWER_INPUT_HIGHEST = 9, 1003 CPUCP_POWER_RESET_INPUT_HISTORY = 11 1004}; 1005 1006/* 1007 * MSI type enumeration table for all ASICs and future SW versions. 1008 * For future ASIC-LKD compatibility, we can only add new enumerations. 1009 * at the end of the table (before CPUCP_NUM_OF_MSI_TYPES). 1010 * Changing the order of entries or removing entries is not allowed. 1011 */ 1012enum cpucp_msi_type { 1013 CPUCP_EVENT_QUEUE_MSI_TYPE, 1014 CPUCP_NIC_PORT1_MSI_TYPE, 1015 CPUCP_NIC_PORT3_MSI_TYPE, 1016 CPUCP_NIC_PORT5_MSI_TYPE, 1017 CPUCP_NIC_PORT7_MSI_TYPE, 1018 CPUCP_NIC_PORT9_MSI_TYPE, 1019 CPUCP_EVENT_QUEUE_ERR_MSI_TYPE, 1020 CPUCP_NUM_OF_MSI_TYPES 1021}; 1022 1023/* 1024 * PLL enumeration table used for all ASICs and future SW versions. 1025 * For future ASIC-LKD compatibility, we can only add new enumerations. 1026 * at the end of the table. 1027 * Changing the order of entries or removing entries is not allowed. 1028 */ 1029enum pll_index { 1030 CPU_PLL = 0, 1031 PCI_PLL = 1, 1032 NIC_PLL = 2, 1033 DMA_PLL = 3, 1034 MESH_PLL = 4, 1035 MME_PLL = 5, 1036 TPC_PLL = 6, 1037 IF_PLL = 7, 1038 SRAM_PLL = 8, 1039 NS_PLL = 9, 1040 HBM_PLL = 10, 1041 MSS_PLL = 11, 1042 DDR_PLL = 12, 1043 VID_PLL = 13, 1044 BANK_PLL = 14, 1045 MMU_PLL = 15, 1046 IC_PLL = 16, 1047 MC_PLL = 17, 1048 EMMC_PLL = 18, 1049 D2D_PLL = 19, 1050 CS_PLL = 20, 1051 C2C_PLL = 21, 1052 NCH_PLL = 22, 1053 C2M_PLL = 23, 1054 PLL_MAX 1055}; 1056 1057enum rl_index { 1058 TPC_RL = 0, 1059 MME_RL, 1060 EDMA_RL, 1061}; 1062 1063enum pvt_index { 1064 PVT_SW, 1065 PVT_SE, 1066 PVT_NW, 1067 PVT_NE 1068}; 1069 1070/* Event Queue Packets */ 1071 1072struct eq_generic_event { 1073 __le64 data[7]; 1074}; 1075 1076/* 1077 * CpuCP info 1078 */ 1079 1080#define CARD_NAME_MAX_LEN 16 1081#define CPUCP_MAX_SENSORS 128 1082#define CPUCP_MAX_NICS 128 1083#define CPUCP_LANES_PER_NIC 4 1084#define CPUCP_NIC_QSFP_EEPROM_MAX_LEN 1024 1085#define CPUCP_MAX_NIC_LANES (CPUCP_MAX_NICS * CPUCP_LANES_PER_NIC) 1086#define CPUCP_NIC_MASK_ARR_LEN ((CPUCP_MAX_NICS + 63) / 64) 1087#define CPUCP_NIC_POLARITY_ARR_LEN ((CPUCP_MAX_NIC_LANES + 63) / 64) 1088#define CPUCP_HBM_ROW_REPLACE_MAX 32 1089 1090struct cpucp_sensor { 1091 __le32 type; 1092 __le32 flags; 1093}; 1094 1095/** 1096 * struct cpucp_card_types - ASIC card type. 1097 * @cpucp_card_type_pci: PCI card. 1098 * @cpucp_card_type_pmc: PCI Mezzanine Card. 1099 */ 1100enum cpucp_card_types { 1101 cpucp_card_type_pci, 1102 cpucp_card_type_pmc 1103}; 1104 1105#define CPUCP_SEC_CONF_ENABLED_SHIFT 0 1106#define CPUCP_SEC_CONF_ENABLED_MASK 0x00000001 1107 1108#define CPUCP_SEC_CONF_FLASH_WP_SHIFT 1 1109#define CPUCP_SEC_CONF_FLASH_WP_MASK 0x00000002 1110 1111#define CPUCP_SEC_CONF_EEPROM_WP_SHIFT 2 1112#define CPUCP_SEC_CONF_EEPROM_WP_MASK 0x00000004 1113 1114/** 1115 * struct cpucp_security_info - Security information. 1116 * @config: configuration bit field 1117 * @keys_num: number of stored keys 1118 * @revoked_keys: revoked keys bit field 1119 * @min_svn: minimal security version 1120 */ 1121struct cpucp_security_info { 1122 __u8 config; 1123 __u8 keys_num; 1124 __u8 revoked_keys; 1125 __u8 min_svn; 1126}; 1127 1128/** 1129 * struct cpucp_info - Info from CpuCP that is necessary to the host's driver 1130 * @sensors: available sensors description. 1131 * @kernel_version: CpuCP linux kernel version. 1132 * @reserved: reserved field. 1133 * @card_type: card configuration type. 1134 * @card_location: in a server, each card has different connections topology 1135 * depending on its location (relevant for PMC card type) 1136 * @cpld_version: CPLD programmed F/W version. 1137 * @infineon_version: Infineon main DC-DC version. 1138 * @fuse_version: silicon production FUSE information. 1139 * @thermal_version: thermald S/W version. 1140 * @cpucp_version: CpuCP S/W version. 1141 * @infineon_second_stage_version: Infineon 2nd stage DC-DC version. 1142 * @dram_size: available DRAM size. 1143 * @card_name: card name that will be displayed in HWMON subsystem on the host 1144 * @tpc_binning_mask: TPC binning mask, 1 bit per TPC instance 1145 * (0 = functional, 1 = binned) 1146 * @decoder_binning_mask: Decoder binning mask, 1 bit per decoder instance 1147 * (0 = functional, 1 = binned), maximum 1 per dcore 1148 * @sram_binning: Categorize SRAM functionality 1149 * (0 = fully functional, 1 = lower-half is not functional, 1150 * 2 = upper-half is not functional) 1151 * @sec_info: security information 1152 * @cpld_timestamp: CPLD programmed F/W timestamp. 1153 * @pll_map: Bit map of supported PLLs for current ASIC version. 1154 * @mme_binning_mask: MME binning mask, 1155 * bits [0:6] <==> dcore0 mme fma 1156 * bits [7:13] <==> dcore1 mme fma 1157 * bits [14:20] <==> dcore0 mme ima 1158 * bits [21:27] <==> dcore1 mme ima 1159 * For each group, if the 6th bit is set then first 5 bits 1160 * represent the col's idx [0-31], otherwise these bits are 1161 * ignored, and col idx 32 is binned. 7th bit is don't care. 1162 * @dram_binning_mask: DRAM binning mask, 1 bit per dram instance 1163 * (0 = functional 1 = binned) 1164 * @memory_repair_flag: eFuse flag indicating memory repair 1165 * @edma_binning_mask: EDMA binning mask, 1 bit per EDMA instance 1166 * (0 = functional 1 = binned) 1167 * @xbar_binning_mask: Xbar binning mask, 1 bit per Xbar instance 1168 * (0 = functional 1 = binned) 1169 * @interposer_version: Interposer version programmed in eFuse 1170 * @substrate_version: Substrate version programmed in eFuse 1171 * @eq_health_check_supported: eq health check feature supported in FW. 1172 * @fw_hbm_region_size: Size in bytes of FW reserved region in HBM. 1173 * @fw_os_version: Firmware OS Version 1174 */ 1175struct cpucp_info { 1176 struct cpucp_sensor sensors[CPUCP_MAX_SENSORS]; 1177 __u8 kernel_version[VERSION_MAX_LEN]; 1178 __le32 reserved1; 1179 __le32 card_type; 1180 __le32 card_location; 1181 __le32 cpld_version; 1182 __le32 infineon_version; 1183 __u8 fuse_version[VERSION_MAX_LEN]; 1184 __u8 thermal_version[VERSION_MAX_LEN]; 1185 __u8 cpucp_version[VERSION_MAX_LEN]; 1186 __le32 infineon_second_stage_version; 1187 __le64 dram_size; 1188 char card_name[CARD_NAME_MAX_LEN]; 1189 __le64 tpc_binning_mask; 1190 __le64 decoder_binning_mask; 1191 __u8 sram_binning; 1192 __u8 dram_binning_mask; 1193 __u8 memory_repair_flag; 1194 __u8 edma_binning_mask; 1195 __u8 xbar_binning_mask; 1196 __u8 interposer_version; 1197 __u8 substrate_version; 1198 __u8 eq_health_check_supported; 1199 struct cpucp_security_info sec_info; 1200 __le32 cpld_timestamp; 1201 __u8 pll_map[PLL_MAP_LEN]; 1202 __le64 mme_binning_mask; 1203 __u8 fw_os_version[VERSION_MAX_LEN]; 1204}; 1205 1206struct cpucp_mac_addr { 1207 __u8 mac_addr[ETH_ALEN]; 1208}; 1209 1210enum cpucp_serdes_type { 1211 TYPE_1_SERDES_TYPE, 1212 TYPE_2_SERDES_TYPE, 1213 HLS1_SERDES_TYPE, 1214 HLS1H_SERDES_TYPE, 1215 HLS2_SERDES_TYPE, 1216 HLS2_TYPE_1_SERDES_TYPE, 1217 MAX_NUM_SERDES_TYPE, /* number of types */ 1218 UNKNOWN_SERDES_TYPE = 0xFFFF /* serdes_type is u16 */ 1219}; 1220 1221struct cpucp_nic_info { 1222 struct cpucp_mac_addr mac_addrs[CPUCP_MAX_NICS]; 1223 __le64 link_mask[CPUCP_NIC_MASK_ARR_LEN]; 1224 __le64 pol_tx_mask[CPUCP_NIC_POLARITY_ARR_LEN]; 1225 __le64 pol_rx_mask[CPUCP_NIC_POLARITY_ARR_LEN]; 1226 __le64 link_ext_mask[CPUCP_NIC_MASK_ARR_LEN]; 1227 __u8 qsfp_eeprom[CPUCP_NIC_QSFP_EEPROM_MAX_LEN]; 1228 __le64 auto_neg_mask[CPUCP_NIC_MASK_ARR_LEN]; 1229 __le16 serdes_type; /* enum cpucp_serdes_type */ 1230 __le16 tx_swap_map[CPUCP_MAX_NICS]; 1231 __u8 reserved[6]; 1232}; 1233 1234#define PAGE_DISCARD_MAX 64 1235 1236struct page_discard_info { 1237 __u8 num_entries; 1238 __u8 reserved[7]; 1239 __le32 mmu_page_idx[PAGE_DISCARD_MAX]; 1240}; 1241 1242/* 1243 * struct frac_val - fracture value represented by "integer.frac". 1244 * @integer: the integer part of the fracture value; 1245 * @frac: the fracture part of the fracture value. 1246 */ 1247struct frac_val { 1248 union { 1249 struct { 1250 __le16 integer; 1251 __le16 frac; 1252 }; 1253 __le32 val; 1254 }; 1255}; 1256 1257/* 1258 * struct ser_val - the SER (symbol error rate) value is represented by "integer * 10 ^ -exp". 1259 * @integer: the integer part of the SER value; 1260 * @exp: the exponent part of the SER value. 1261 */ 1262struct ser_val { 1263 __le16 integer; 1264 __le16 exp; 1265}; 1266 1267/* 1268 * struct cpucp_nic_status - describes the status of a NIC port. 1269 * @port: NIC port index. 1270 * @bad_format_cnt: e.g. CRC. 1271 * @responder_out_of_sequence_psn_cnt: e.g NAK. 1272 * @high_ber_reinit_cnt: link reinit due to high BER. 1273 * @correctable_err_cnt: e.g. bit-flip. 1274 * @uncorrectable_err_cnt: e.g. MAC errors. 1275 * @retraining_cnt: re-training counter. 1276 * @up: is port up. 1277 * @pcs_link: has PCS link. 1278 * @phy_ready: is PHY ready. 1279 * @auto_neg: is Autoneg enabled. 1280 * @timeout_retransmission_cnt: timeout retransmission events. 1281 * @high_ber_cnt: high ber events. 1282 * @pre_fec_ser: pre FEC SER value. 1283 * @post_fec_ser: post FEC SER value. 1284 * @throughput: measured throughput. 1285 * @latency: measured latency. 1286 */ 1287struct cpucp_nic_status { 1288 __le32 port; 1289 __le32 bad_format_cnt; 1290 __le32 responder_out_of_sequence_psn_cnt; 1291 __le32 high_ber_reinit; 1292 __le32 correctable_err_cnt; 1293 __le32 uncorrectable_err_cnt; 1294 __le32 retraining_cnt; 1295 __u8 up; 1296 __u8 pcs_link; 1297 __u8 phy_ready; 1298 __u8 auto_neg; 1299 __le32 timeout_retransmission_cnt; 1300 __le32 high_ber_cnt; 1301 struct ser_val pre_fec_ser; 1302 struct ser_val post_fec_ser; 1303 struct frac_val bandwidth; 1304 struct frac_val lat; 1305}; 1306 1307enum cpucp_hbm_row_replace_cause { 1308 REPLACE_CAUSE_DOUBLE_ECC_ERR, 1309 REPLACE_CAUSE_MULTI_SINGLE_ECC_ERR, 1310}; 1311 1312struct cpucp_hbm_row_info { 1313 __u8 hbm_idx; 1314 __u8 pc; 1315 __u8 sid; 1316 __u8 bank_idx; 1317 __le16 row_addr; 1318 __u8 replaced_row_cause; /* enum cpucp_hbm_row_replace_cause */ 1319 __u8 pad; 1320}; 1321 1322struct cpucp_hbm_row_replaced_rows_info { 1323 __le16 num_replaced_rows; 1324 __u8 pad[6]; 1325 struct cpucp_hbm_row_info replaced_rows[CPUCP_HBM_ROW_REPLACE_MAX]; 1326}; 1327 1328enum cpu_reset_status { 1329 CPU_RST_STATUS_NA = 0, 1330 CPU_RST_STATUS_SOFT_RST_DONE = 1, 1331}; 1332 1333#define SEC_PCR_DATA_BUF_SZ 256 1334#define SEC_PCR_QUOTE_BUF_SZ 510 /* (512 - 2) 2 bytes used for size */ 1335#define SEC_SIGNATURE_BUF_SZ 255 /* (256 - 1) 1 byte used for size */ 1336#define SEC_PUB_DATA_BUF_SZ 510 /* (512 - 2) 2 bytes used for size */ 1337#define SEC_CERTIFICATE_BUF_SZ 2046 /* (2048 - 2) 2 bytes used for size */ 1338 1339/* 1340 * struct cpucp_sec_attest_info - attestation report of the boot 1341 * @pcr_data: raw values of the PCR registers 1342 * @pcr_num_reg: number of PCR registers in the pcr_data array 1343 * @pcr_reg_len: length of each PCR register in the pcr_data array (bytes) 1344 * @nonce: number only used once. random number provided by host. this also 1345 * passed to the quote command as a qualifying data. 1346 * @pcr_quote_len: length of the attestation quote data (bytes) 1347 * @pcr_quote: attestation report data structure 1348 * @quote_sig_len: length of the attestation report signature (bytes) 1349 * @quote_sig: signature structure of the attestation report 1350 * @pub_data_len: length of the public data (bytes) 1351 * @public_data: public key for the signed attestation 1352 * (outPublic + name + qualifiedName) 1353 * @certificate_len: length of the certificate (bytes) 1354 * @certificate: certificate for the attestation signing key 1355 */ 1356struct cpucp_sec_attest_info { 1357 __u8 pcr_data[SEC_PCR_DATA_BUF_SZ]; 1358 __u8 pcr_num_reg; 1359 __u8 pcr_reg_len; 1360 __le16 pad0; 1361 __le32 nonce; 1362 __le16 pcr_quote_len; 1363 __u8 pcr_quote[SEC_PCR_QUOTE_BUF_SZ]; 1364 __u8 quote_sig_len; 1365 __u8 quote_sig[SEC_SIGNATURE_BUF_SZ]; 1366 __le16 pub_data_len; 1367 __u8 public_data[SEC_PUB_DATA_BUF_SZ]; 1368 __le16 certificate_len; 1369 __u8 certificate[SEC_CERTIFICATE_BUF_SZ]; 1370}; 1371 1372/* 1373 * struct cpucp_dev_info_signed - device information signed by a secured device 1374 * @info: device information structure as defined above 1375 * @nonce: number only used once. random number provided by host. this number is 1376 * hashed and signed along with the device information. 1377 * @info_sig_len: length of the attestation signature (bytes) 1378 * @info_sig: signature of the info + nonce data. 1379 * @pub_data_len: length of the public data (bytes) 1380 * @public_data: public key info signed info data 1381 * (outPublic + name + qualifiedName) 1382 * @certificate_len: length of the certificate (bytes) 1383 * @certificate: certificate for the signing key 1384 */ 1385struct cpucp_dev_info_signed { 1386 struct cpucp_info info; /* assumed to be 64bit aligned */ 1387 __le32 nonce; 1388 __le32 pad0; 1389 __u8 info_sig_len; 1390 __u8 info_sig[SEC_SIGNATURE_BUF_SZ]; 1391 __le16 pub_data_len; 1392 __u8 public_data[SEC_PUB_DATA_BUF_SZ]; 1393 __le16 certificate_len; 1394 __u8 certificate[SEC_CERTIFICATE_BUF_SZ]; 1395}; 1396 1397#define DCORE_MON_REGS_SZ 512 1398/* 1399 * struct dcore_monitor_regs_data - DCORE monitor regs data. 1400 * the structure follows sync manager block layout. Obsolete. 1401 * @mon_pay_addrl: array of payload address low bits. 1402 * @mon_pay_addrh: array of payload address high bits. 1403 * @mon_pay_data: array of payload data. 1404 * @mon_arm: array of monitor arm. 1405 * @mon_status: array of monitor status. 1406 */ 1407struct dcore_monitor_regs_data { 1408 __le32 mon_pay_addrl[DCORE_MON_REGS_SZ]; 1409 __le32 mon_pay_addrh[DCORE_MON_REGS_SZ]; 1410 __le32 mon_pay_data[DCORE_MON_REGS_SZ]; 1411 __le32 mon_arm[DCORE_MON_REGS_SZ]; 1412 __le32 mon_status[DCORE_MON_REGS_SZ]; 1413}; 1414 1415/* contains SM data for each SYNC_MNGR (Obsolete) */ 1416struct cpucp_monitor_dump { 1417 struct dcore_monitor_regs_data sync_mngr_w_s; 1418 struct dcore_monitor_regs_data sync_mngr_e_s; 1419 struct dcore_monitor_regs_data sync_mngr_w_n; 1420 struct dcore_monitor_regs_data sync_mngr_e_n; 1421}; 1422 1423/* 1424 * The Type of the generic request (and other input arguments) will be fetched from user by reading 1425 * from "pkt_subidx" field in struct cpucp_packet. 1426 * 1427 * HL_PASSTHROUGHT_VERSIONS - Fetch all firmware versions. 1428 * HL_GET_ERR_COUNTERS_CMD - Command to get error counters 1429 * HL_GET_P_STATE - get performance state 1430 */ 1431enum hl_passthrough_type { 1432 HL_PASSTHROUGH_VERSIONS, 1433 HL_GET_ERR_COUNTERS_CMD, 1434 HL_GET_P_STATE, 1435}; 1436 1437#endif /* CPUCP_IF_H */
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