generic.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2
  3#ifndef __LINUX_GPIO_GENERIC_H
  4#define __LINUX_GPIO_GENERIC_H
  5
  6#include <linux/cleanup.h>
  7#include <linux/gpio/driver.h>
  8#include <linux/spinlock.h>
  9
 10struct device;
 11
 12#define GPIO_GENERIC_BIG_ENDIAN			BIT(0)
 13#define GPIO_GENERIC_UNREADABLE_REG_SET		BIT(1) /* reg_set is unreadable */
 14#define GPIO_GENERIC_UNREADABLE_REG_DIR		BIT(2) /* reg_dir is unreadable */
 15#define GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER	BIT(3)
 16#define GPIO_GENERIC_READ_OUTPUT_REG_SET	BIT(4) /* reg_set stores output value */
 17#define GPIO_GENERIC_NO_OUTPUT			BIT(5) /* only input */
 18#define GPIO_GENERIC_NO_SET_ON_INPUT		BIT(6)
 19#define GPIO_GENERIC_PINCTRL_BACKEND		BIT(7) /* Call pinctrl direction setters */
 20#define GPIO_GENERIC_NO_INPUT			BIT(8) /* only output */
 21
 22/**
 23 * struct gpio_generic_chip_config - Generic GPIO chip configuration data
 24 * @dev: Parent device of the new GPIO chip (compulsory).
 25 * @sz: Size (width) of the MMIO registers in bytes, typically 1, 2 or 4.
 26 * @dat: MMIO address for the register to READ the value of the GPIO lines, it
 27 *       is expected that a 1 in the corresponding bit in this register means
 28 *       the line is asserted.
 29 * @set: MMIO address for the register to SET the value of the GPIO lines, it
 30 *       is expected that we write the line with 1 in this register to drive
 31 *       the GPIO line high.
 32 * @clr: MMIO address for the register to CLEAR the value of the GPIO lines,
 33 *       it is expected that we write the line with 1 in this register to
 34 *       drive the GPIO line low. It is allowed to leave this address as NULL,
 35 *       in that case the SET register will be assumed to also clear the GPIO
 36 *       lines, by actively writing the line with 0.
 37 * @dirout: MMIO address for the register to set the line as OUTPUT. It is
 38 *          assumed that setting a line to 1 in this register will turn that
 39 *          line into an output line. Conversely, setting the line to 0 will
 40 *          turn that line into an input.
 41 * @dirin: MMIO address for the register to set this line as INPUT. It is
 42 *         assumed that setting a line to 1 in this register will turn that
 43 *         line into an input line. Conversely, setting the line to 0 will
 44 *         turn that line into an output.
 45 * @flags: Different flags that will affect the behaviour of the device, such
 46 *         as endianness etc.
 47 */
 48struct gpio_generic_chip_config {
 49	struct device *dev;
 50	unsigned long sz;
 51	void __iomem *dat;
 52	void __iomem *set;
 53	void __iomem *clr;
 54	void __iomem *dirout;
 55	void __iomem *dirin;
 56	unsigned long flags;
 57};
 58
 59/**
 60 * struct gpio_generic_chip - Generic GPIO chip implementation.
 61 * @gc: The underlying struct gpio_chip object, implementing low-level GPIO
 62 *      chip routines.
 63 * @read_reg: reader function for generic GPIO
 64 * @write_reg: writer function for generic GPIO
 65 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is
 66 *           representing line 0, bit 30 is line 1 ... bit 0 is line 31) this
 67 *           is set to true by the generic GPIO core. It is for internal
 68 *           housekeeping only.
 69 * @reg_dat: data (in) register for generic GPIO
 70 * @reg_set: output set register (out=high) for generic GPIO
 71 * @reg_clr: output clear register (out=low) for generic GPIO
 72 * @reg_dir_out: direction out setting register for generic GPIO
 73 * @reg_dir_in: direction in setting register for generic GPIO
 74 * @dir_unreadable: indicates that the direction register(s) cannot be read and
 75 *                  we need to rely on out internal state tracking.
 76 * @pinctrl: the generic GPIO uses a pin control backend.
 77 * @bits: number of register bits used for a generic GPIO
 78 *        i.e. <register width> * 8
 79 * @lock: used to lock chip->sdata. Also, this is needed to keep
 80 *        shadowed and real data registers writes together.
 81 * @sdata: shadowed data register for generic GPIO to clear/set bits safely.
 82 * @sdir: shadowed direction register for generic GPIO to clear/set direction
 83 *        safely. A "1" in this word means the line is set as output.
 84 */
 85struct gpio_generic_chip {
 86	struct gpio_chip gc;
 87	unsigned long (*read_reg)(void __iomem *reg);
 88	void (*write_reg)(void __iomem *reg, unsigned long data);
 89	bool be_bits;
 90	void __iomem *reg_dat;
 91	void __iomem *reg_set;
 92	void __iomem *reg_clr;
 93	void __iomem *reg_dir_out;
 94	void __iomem *reg_dir_in;
 95	bool dir_unreadable;
 96	bool pinctrl;
 97	int bits;
 98	raw_spinlock_t lock;
 99	unsigned long sdata;
100	unsigned long sdir;
101};
102
103static inline struct gpio_generic_chip *
104to_gpio_generic_chip(struct gpio_chip *gc)
105{
106	return container_of(gc, struct gpio_generic_chip, gc);
107}
108
109int gpio_generic_chip_init(struct gpio_generic_chip *chip,
110			   const struct gpio_generic_chip_config *cfg);
111
112/**
113 * gpio_generic_chip_set() - Set the GPIO line value of the generic GPIO chip.
114 * @chip: Generic GPIO chip to use.
115 * @offset: Hardware offset of the line to set.
116 * @value: New GPIO line value.
117 *
118 * Some modules using the generic GPIO chip, need to set line values in their
119 * direction setters but they don't have access to the gpio-mmio symbols so
120 * they use the function pointer in struct gpio_chip directly. This is not
121 * optimal and can lead to crashes at run-time in some instances. This wrapper
122 * provides a safe interface for users.
123 *
124 * Returns: 0 on success, negative error number of failure.
125 */
126static inline int
127gpio_generic_chip_set(struct gpio_generic_chip *chip, unsigned int offset,
128		      int value)
129{
130	if (WARN_ON(!chip->gc.set))
131		return -EOPNOTSUPP;
132
133	return chip->gc.set(&chip->gc, offset, value);
134}
135
136/**
137 * gpio_generic_read_reg() - Read a register using the underlying callback.
138 * @chip: Generic GPIO chip to use.
139 * @reg: Register to read.
140 *
141 * Returns: value read from register.
142 */
143static inline unsigned long
144gpio_generic_read_reg(struct gpio_generic_chip *chip, void __iomem *reg)
145{
146	if (WARN_ON(!chip->read_reg))
147		return 0;
148
149	return chip->read_reg(reg);
150}
151
152/**
153 * gpio_generic_write_reg() - Write a register using the underlying callback.
154 * @chip: Generic GPIO chip to use.
155 * @reg: Register to write to.
156 * @val: New value to write.
157 */
158static inline void gpio_generic_write_reg(struct gpio_generic_chip *chip,
159					  void __iomem *reg, unsigned long val)
160{
161	if (WARN_ON(!chip->write_reg))
162		return;
163
164	chip->write_reg(reg, val);
165}
166
167#define gpio_generic_chip_lock(gen_gc) \
168	raw_spin_lock(&(gen_gc)->lock)
169
170#define gpio_generic_chip_unlock(gen_gc) \
171	raw_spin_unlock(&(gen_gc)->lock)
172
173#define gpio_generic_chip_lock_irqsave(gen_gc, flags) \
174	raw_spin_lock_irqsave(&(gen_gc)->lock, flags)
175
176#define gpio_generic_chip_unlock_irqrestore(gen_gc, flags) \
177	raw_spin_unlock_irqrestore(&(gen_gc)->lock, flags)
178
179DEFINE_LOCK_GUARD_1(gpio_generic_lock,
180		    struct gpio_generic_chip,
181		    gpio_generic_chip_lock(_T->lock),
182		    gpio_generic_chip_unlock(_T->lock))
183
184DEFINE_LOCK_GUARD_1(gpio_generic_lock_irqsave,
185		    struct gpio_generic_chip,
186		    gpio_generic_chip_lock_irqsave(_T->lock, _T->flags),
187		    gpio_generic_chip_unlock_irqrestore(_T->lock, _T->flags),
188		    unsigned long flags)
189
190#endif /* __LINUX_GPIO_GENERIC_H */