dpll.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 *  Copyright (c) 2023 Meta Platforms, Inc. and affiliates
  4 *  Copyright (c) 2023 Intel and affiliates
  5 */
  6
  7#ifndef __DPLL_H__
  8#define __DPLL_H__
  9
 10#include <uapi/linux/dpll.h>
 11#include <linux/device.h>
 12#include <linux/netlink.h>
 13#include <linux/netdevice.h>
 14#include <linux/rtnetlink.h>
 15
 16struct dpll_device;
 17struct dpll_pin;
 18struct dpll_pin_esync;
 19
 20struct dpll_device_ops {
 21	int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv,
 22			enum dpll_mode *mode, struct netlink_ext_ack *extack);
 23	int (*lock_status_get)(const struct dpll_device *dpll, void *dpll_priv,
 24			       enum dpll_lock_status *status,
 25			       enum dpll_lock_status_error *status_error,
 26			       struct netlink_ext_ack *extack);
 27	int (*temp_get)(const struct dpll_device *dpll, void *dpll_priv,
 28			s32 *temp, struct netlink_ext_ack *extack);
 29	int (*clock_quality_level_get)(const struct dpll_device *dpll,
 30				       void *dpll_priv,
 31				       unsigned long *qls,
 32				       struct netlink_ext_ack *extack);
 33	int (*phase_offset_monitor_set)(const struct dpll_device *dpll,
 34					void *dpll_priv,
 35					enum dpll_feature_state state,
 36					struct netlink_ext_ack *extack);
 37	int (*phase_offset_monitor_get)(const struct dpll_device *dpll,
 38					void *dpll_priv,
 39					enum dpll_feature_state *state,
 40					struct netlink_ext_ack *extack);
 41	int (*phase_offset_avg_factor_set)(const struct dpll_device *dpll,
 42					   void *dpll_priv, u32 factor,
 43					   struct netlink_ext_ack *extack);
 44	int (*phase_offset_avg_factor_get)(const struct dpll_device *dpll,
 45					   void *dpll_priv, u32 *factor,
 46					   struct netlink_ext_ack *extack);
 47};
 48
 49struct dpll_pin_ops {
 50	int (*frequency_set)(const struct dpll_pin *pin, void *pin_priv,
 51			     const struct dpll_device *dpll, void *dpll_priv,
 52			     const u64 frequency,
 53			     struct netlink_ext_ack *extack);
 54	int (*frequency_get)(const struct dpll_pin *pin, void *pin_priv,
 55			     const struct dpll_device *dpll, void *dpll_priv,
 56			     u64 *frequency, struct netlink_ext_ack *extack);
 57	int (*direction_set)(const struct dpll_pin *pin, void *pin_priv,
 58			     const struct dpll_device *dpll, void *dpll_priv,
 59			     const enum dpll_pin_direction direction,
 60			     struct netlink_ext_ack *extack);
 61	int (*direction_get)(const struct dpll_pin *pin, void *pin_priv,
 62			     const struct dpll_device *dpll, void *dpll_priv,
 63			     enum dpll_pin_direction *direction,
 64			     struct netlink_ext_ack *extack);
 65	int (*state_on_pin_get)(const struct dpll_pin *pin, void *pin_priv,
 66				const struct dpll_pin *parent_pin,
 67				void *parent_pin_priv,
 68				enum dpll_pin_state *state,
 69				struct netlink_ext_ack *extack);
 70	int (*state_on_dpll_get)(const struct dpll_pin *pin, void *pin_priv,
 71				 const struct dpll_device *dpll,
 72				 void *dpll_priv, enum dpll_pin_state *state,
 73				 struct netlink_ext_ack *extack);
 74	int (*state_on_pin_set)(const struct dpll_pin *pin, void *pin_priv,
 75				const struct dpll_pin *parent_pin,
 76				void *parent_pin_priv,
 77				const enum dpll_pin_state state,
 78				struct netlink_ext_ack *extack);
 79	int (*state_on_dpll_set)(const struct dpll_pin *pin, void *pin_priv,
 80				 const struct dpll_device *dpll,
 81				 void *dpll_priv,
 82				 const enum dpll_pin_state state,
 83				 struct netlink_ext_ack *extack);
 84	int (*prio_get)(const struct dpll_pin *pin,  void *pin_priv,
 85			const struct dpll_device *dpll,  void *dpll_priv,
 86			u32 *prio, struct netlink_ext_ack *extack);
 87	int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
 88			const struct dpll_device *dpll, void *dpll_priv,
 89			const u32 prio, struct netlink_ext_ack *extack);
 90	int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv,
 91				const struct dpll_device *dpll, void *dpll_priv,
 92				s64 *phase_offset,
 93				struct netlink_ext_ack *extack);
 94	int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
 95				const struct dpll_device *dpll, void *dpll_priv,
 96				s32 *phase_adjust,
 97				struct netlink_ext_ack *extack);
 98	int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
 99				const struct dpll_device *dpll, void *dpll_priv,
100				const s32 phase_adjust,
101				struct netlink_ext_ack *extack);
102	int (*ffo_get)(const struct dpll_pin *pin, void *pin_priv,
103		       const struct dpll_device *dpll, void *dpll_priv,
104		       s64 *ffo, struct netlink_ext_ack *extack);
105	int (*esync_set)(const struct dpll_pin *pin, void *pin_priv,
106			 const struct dpll_device *dpll, void *dpll_priv,
107			 u64 freq, struct netlink_ext_ack *extack);
108	int (*esync_get)(const struct dpll_pin *pin, void *pin_priv,
109			 const struct dpll_device *dpll, void *dpll_priv,
110			 struct dpll_pin_esync *esync,
111			 struct netlink_ext_ack *extack);
112	int (*ref_sync_set)(const struct dpll_pin *pin, void *pin_priv,
113			    const struct dpll_pin *ref_sync_pin,
114			    void *ref_sync_pin_priv,
115			    const enum dpll_pin_state state,
116			    struct netlink_ext_ack *extack);
117	int (*ref_sync_get)(const struct dpll_pin *pin, void *pin_priv,
118			    const struct dpll_pin *ref_sync_pin,
119			    void *ref_sync_pin_priv,
120			    enum dpll_pin_state *state,
121			    struct netlink_ext_ack *extack);
122};
123
124struct dpll_pin_frequency {
125	u64 min;
126	u64 max;
127};
128
129#define DPLL_PIN_FREQUENCY_RANGE(_min, _max)	\
130	{					\
131		.min = _min,			\
132		.max = _max,			\
133	}
134
135#define DPLL_PIN_FREQUENCY(_val) DPLL_PIN_FREQUENCY_RANGE(_val, _val)
136#define DPLL_PIN_FREQUENCY_1PPS \
137	DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_1_HZ)
138#define DPLL_PIN_FREQUENCY_10MHZ \
139	DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_MHZ)
140#define DPLL_PIN_FREQUENCY_IRIG_B \
141	DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_KHZ)
142#define DPLL_PIN_FREQUENCY_DCF77 \
143	DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
144
145struct dpll_pin_phase_adjust_range {
146	s32 min;
147	s32 max;
148};
149
150struct dpll_pin_esync {
151	u64 freq;
152	const struct dpll_pin_frequency *range;
153	u8 range_num;
154	u8 pulse;
155};
156
157struct dpll_pin_properties {
158	const char *board_label;
159	const char *panel_label;
160	const char *package_label;
161	enum dpll_pin_type type;
162	unsigned long capabilities;
163	u32 freq_supported_num;
164	struct dpll_pin_frequency *freq_supported;
165	struct dpll_pin_phase_adjust_range phase_range;
166	u32 phase_gran;
167};
168
169#if IS_ENABLED(CONFIG_DPLL)
170void dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin);
171void dpll_netdev_pin_clear(struct net_device *dev);
172
173size_t dpll_netdev_pin_handle_size(const struct net_device *dev);
174int dpll_netdev_add_pin_handle(struct sk_buff *msg,
175			       const struct net_device *dev);
176#else
177static inline void
178dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin) { }
179static inline void dpll_netdev_pin_clear(struct net_device *dev) { }
180
181static inline size_t dpll_netdev_pin_handle_size(const struct net_device *dev)
182{
183	return 0;
184}
185
186static inline int
187dpll_netdev_add_pin_handle(struct sk_buff *msg, const struct net_device *dev)
188{
189	return 0;
190}
191#endif
192
193struct dpll_device *
194dpll_device_get(u64 clock_id, u32 dev_driver_id, struct module *module);
195
196void dpll_device_put(struct dpll_device *dpll);
197
198int dpll_device_register(struct dpll_device *dpll, enum dpll_type type,
199			 const struct dpll_device_ops *ops, void *priv);
200
201void dpll_device_unregister(struct dpll_device *dpll,
202			    const struct dpll_device_ops *ops, void *priv);
203
204struct dpll_pin *
205dpll_pin_get(u64 clock_id, u32 dev_driver_id, struct module *module,
206	     const struct dpll_pin_properties *prop);
207
208int dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin,
209		      const struct dpll_pin_ops *ops, void *priv);
210
211void dpll_pin_unregister(struct dpll_device *dpll, struct dpll_pin *pin,
212			 const struct dpll_pin_ops *ops, void *priv);
213
214void dpll_pin_put(struct dpll_pin *pin);
215
216int dpll_pin_on_pin_register(struct dpll_pin *parent, struct dpll_pin *pin,
217			     const struct dpll_pin_ops *ops, void *priv);
218
219void dpll_pin_on_pin_unregister(struct dpll_pin *parent, struct dpll_pin *pin,
220				const struct dpll_pin_ops *ops, void *priv);
221
222int dpll_pin_ref_sync_pair_add(struct dpll_pin *pin,
223			       struct dpll_pin *ref_sync_pin);
224
225int dpll_device_change_ntf(struct dpll_device *dpll);
226
227int dpll_pin_change_ntf(struct dpll_pin *pin);
228
229#endif