edma.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
  4 * Synopsys DesignWare eDMA core driver
  5 *
  6 * Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
  7 */
  8
  9#ifndef _DW_EDMA_H
 10#define _DW_EDMA_H
 11
 12#include <linux/device.h>
 13#include <linux/dmaengine.h>
 14
 15#define EDMA_MAX_WR_CH                                  8
 16#define EDMA_MAX_RD_CH                                  8
 17
 18struct dw_edma;
 19
 20struct dw_edma_region {
 21	u64		paddr;
 22	union {
 23		void		*mem;
 24		void __iomem	*io;
 25	} vaddr;
 26	size_t		sz;
 27};
 28
 29/**
 30 * struct dw_edma_core_ops - platform-specific eDMA methods
 31 * @irq_vector:		Get IRQ number of the passed eDMA channel. Note the
 32 *			method accepts the channel id in the end-to-end
 33 *			numbering with the eDMA write channels being placed
 34 *			first in the row.
 35 * @pci_address:	Get PCIe bus address corresponding to the passed CPU
 36 *			address. Note there is no need in specifying this
 37 *			function if the address translation is performed by
 38 *			the DW PCIe RP/EP controller with the DW eDMA device in
 39 *			subject and DMA_BYPASS isn't set for all the outbound
 40 *			iATU windows. That will be done by the controller
 41 *			automatically.
 42 */
 43struct dw_edma_plat_ops {
 44	int (*irq_vector)(struct device *dev, unsigned int nr);
 45	u64 (*pci_address)(struct device *dev, phys_addr_t cpu_addr);
 46};
 47
 48enum dw_edma_map_format {
 49	EDMA_MF_EDMA_LEGACY = 0x0,
 50	EDMA_MF_EDMA_UNROLL = 0x1,
 51	EDMA_MF_HDMA_COMPAT = 0x5,
 52	EDMA_MF_HDMA_NATIVE = 0x7,
 53};
 54
 55/**
 56 * enum dw_edma_chip_flags - Flags specific to an eDMA chip
 57 * @DW_EDMA_CHIP_LOCAL:		eDMA is used locally by an endpoint
 58 */
 59enum dw_edma_chip_flags {
 60	DW_EDMA_CHIP_LOCAL	= BIT(0),
 61};
 62
 63/**
 64 * struct dw_edma_chip - representation of DesignWare eDMA controller hardware
 65 * @dev:		 struct device of the eDMA controller
 66 * @id:			 instance ID
 67 * @nr_irqs:		 total number of DMA IRQs
 68 * @ops			 DMA channel to IRQ number mapping
 69 * @flags		 dw_edma_chip_flags
 70 * @reg_base		 DMA register base address
 71 * @ll_wr_cnt		 DMA write link list count
 72 * @ll_rd_cnt		 DMA read link list count
 73 * @rg_region		 DMA register region
 74 * @ll_region_wr	 DMA descriptor link list memory for write channel
 75 * @ll_region_rd	 DMA descriptor link list memory for read channel
 76 * @dt_region_wr	 DMA data memory for write channel
 77 * @dt_region_rd	 DMA data memory for read channel
 78 * @mf			 DMA register map format
 79 * @dw:			 struct dw_edma that is filled by dw_edma_probe()
 80 */
 81struct dw_edma_chip {
 82	struct device		*dev;
 83	int			nr_irqs;
 84	const struct dw_edma_plat_ops	*ops;
 85	u32			flags;
 86
 87	void __iomem		*reg_base;
 88
 89	u16			ll_wr_cnt;
 90	u16			ll_rd_cnt;
 91	/* link list address */
 92	struct dw_edma_region	ll_region_wr[EDMA_MAX_WR_CH];
 93	struct dw_edma_region	ll_region_rd[EDMA_MAX_RD_CH];
 94
 95	/* data region */
 96	struct dw_edma_region	dt_region_wr[EDMA_MAX_WR_CH];
 97	struct dw_edma_region	dt_region_rd[EDMA_MAX_RD_CH];
 98
 99	enum dw_edma_map_format	mf;
100
101	struct dw_edma		*dw;
102};
103
104/* Export to the platform drivers */
105#if IS_REACHABLE(CONFIG_DW_EDMA)
106int dw_edma_probe(struct dw_edma_chip *chip);
107int dw_edma_remove(struct dw_edma_chip *chip);
108#else
109static inline int dw_edma_probe(struct dw_edma_chip *chip)
110{
111	return -ENODEV;
112}
113
114static inline int dw_edma_remove(struct dw_edma_chip *chip)
115{
116	return 0;
117}
118#endif /* CONFIG_DW_EDMA */
119
120#endif /* _DW_EDMA_H */