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clk-provider.h
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linux-6.19.14/include/linux/clk-provider.h
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> 4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> 5 */ 6#ifndef __LINUX_CLK_PROVIDER_H 7#define __LINUX_CLK_PROVIDER_H 8 9#include <linux/of.h> 10#include <linux/of_clk.h> 11 12/* 13 * flags used across common struct clk. these flags should only affect the 14 * top-level framework. custom flags for dealing with hardware specifics 15 * belong in struct clk_foo 16 * 17 * Please update clk_flags[] in drivers/clk/clk.c when making changes here! 18 */ 19#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 20#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 21#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 22#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 23 /* unused */ 24 /* unused */ 25#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 26#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ 27#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ 28#define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ 29#define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ 30#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ 31/* parents need enable during gate/ungate, set rate and re-parent */ 32#define CLK_OPS_PARENT_ENABLE BIT(12) 33/* duty cycle call may be forwarded to the parent clock */ 34#define CLK_DUTY_CYCLE_PARENT BIT(13) 35 36struct clk; 37struct clk_hw; 38struct clk_core; 39struct dentry; 40 41/** 42 * struct clk_rate_request - Structure encoding the clk constraints that 43 * a clock user might require. 44 * 45 * Should be initialized by calling clk_hw_init_rate_request(). 46 * 47 * @core: Pointer to the struct clk_core affected by this request 48 * @rate: Requested clock rate. This field will be adjusted by 49 * clock drivers according to hardware capabilities. 50 * @min_rate: Minimum rate imposed by clk users. 51 * @max_rate: Maximum rate imposed by clk users. 52 * @best_parent_rate: The best parent rate a parent can provide to fulfill the 53 * requested constraints. 54 * @best_parent_hw: The most appropriate parent clock that fulfills the 55 * requested constraints. 56 * 57 */ 58struct clk_rate_request { 59 struct clk_core *core; 60 unsigned long rate; 61 unsigned long min_rate; 62 unsigned long max_rate; 63 unsigned long best_parent_rate; 64 struct clk_hw *best_parent_hw; 65}; 66 67void clk_hw_init_rate_request(const struct clk_hw *hw, 68 struct clk_rate_request *req, 69 unsigned long rate); 70void clk_hw_forward_rate_request(const struct clk_hw *core, 71 const struct clk_rate_request *old_req, 72 const struct clk_hw *parent, 73 struct clk_rate_request *req, 74 unsigned long parent_rate); 75 76/** 77 * struct clk_duty - Structure encoding the duty cycle ratio of a clock 78 * 79 * @num: Numerator of the duty cycle ratio 80 * @den: Denominator of the duty cycle ratio 81 */ 82struct clk_duty { 83 unsigned int num; 84 unsigned int den; 85}; 86 87/** 88 * struct clk_ops - Callback operations for hardware clocks; these are to 89 * be provided by the clock implementation, and will be called by drivers 90 * through the clk_* api. 91 * 92 * @prepare: Prepare the clock for enabling. This must not return until 93 * the clock is fully prepared, and it's safe to call clk_enable. 94 * This callback is intended to allow clock implementations to 95 * do any initialisation that may sleep. Called with 96 * prepare_lock held. 97 * 98 * @unprepare: Release the clock from its prepared state. This will typically 99 * undo any work done in the @prepare callback. Called with 100 * prepare_lock held. 101 * 102 * @is_prepared: Queries the hardware to determine if the clock is prepared. 103 * This function is allowed to sleep. Optional, if this op is not 104 * set then the prepare count will be used. 105 * 106 * @unprepare_unused: Unprepare the clock atomically. Only called from 107 * clk_disable_unused for prepare clocks with special needs. 108 * Called with prepare mutex held. This function may sleep. 109 * 110 * @enable: Enable the clock atomically. This must not return until the 111 * clock is generating a valid clock signal, usable by consumer 112 * devices. Called with enable_lock held. This function must not 113 * sleep. 114 * 115 * @disable: Disable the clock atomically. Called with enable_lock held. 116 * This function must not sleep. 117 * 118 * @is_enabled: Queries the hardware to determine if the clock is enabled. 119 * This function must not sleep. Optional, if this op is not 120 * set then the enable count will be used. 121 * 122 * @disable_unused: Disable the clock atomically. Only called from 123 * clk_disable_unused for gate clocks with special needs. 124 * Called with enable_lock held. This function must not 125 * sleep. 126 * 127 * @save_context: Save the context of the clock in prepration for poweroff. 128 * 129 * @restore_context: Restore the context of the clock after a restoration 130 * of power. 131 * 132 * @recalc_rate: Recalculate the rate of this clock, by querying hardware. The 133 * parent rate is an input parameter. It is up to the caller to 134 * ensure that the prepare_mutex is held across this call. If the 135 * driver cannot figure out a rate for this clock, it must return 136 * 0. Returns the calculated rate. Optional, but recommended - if 137 * this op is not set then clock rate will be initialized to 0. 138 * 139 * @round_rate: Given a target rate as input, returns the closest rate actually 140 * supported by the clock. The parent rate is an input/output 141 * parameter. 142 * 143 * @determine_rate: Given a target rate as input, returns the closest rate 144 * actually supported by the clock, and optionally the parent clock 145 * that should be used to provide the clock rate. 146 * 147 * @set_parent: Change the input source of this clock; for clocks with multiple 148 * possible parents specify a new parent by passing in the index 149 * as a u8 corresponding to the parent in either the .parent_names 150 * or .parents arrays. This function in affect translates an 151 * array index into the value programmed into the hardware. 152 * Returns 0 on success, -EERROR otherwise. 153 * 154 * @get_parent: Queries the hardware to determine the parent of a clock. The 155 * return value is a u8 which specifies the index corresponding to 156 * the parent clock. This index can be applied to either the 157 * .parent_names or .parents arrays. In short, this function 158 * translates the parent value read from hardware into an array 159 * index. Currently only called when the clock is initialized by 160 * __clk_init. This callback is mandatory for clocks with 161 * multiple parents. It is optional (and unnecessary) for clocks 162 * with 0 or 1 parents. 163 * 164 * @set_rate: Change the rate of this clock. The requested rate is specified 165 * by the second argument, which should typically be the return 166 * of .round_rate call. The third argument gives the parent rate 167 * which is likely helpful for most .set_rate implementation. 168 * Returns 0 on success, -EERROR otherwise. 169 * 170 * @set_rate_and_parent: Change the rate and the parent of this clock. The 171 * requested rate is specified by the second argument, which 172 * should typically be the return of .round_rate call. The 173 * third argument gives the parent rate which is likely helpful 174 * for most .set_rate_and_parent implementation. The fourth 175 * argument gives the parent index. This callback is optional (and 176 * unnecessary) for clocks with 0 or 1 parents as well as 177 * for clocks that can tolerate switching the rate and the parent 178 * separately via calls to .set_parent and .set_rate. 179 * Returns 0 on success, -EERROR otherwise. 180 * 181 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy 182 * is expressed in ppb (parts per billion). The parent accuracy is 183 * an input parameter. 184 * Returns the calculated accuracy. Optional - if this op is not 185 * set then clock accuracy will be initialized to parent accuracy 186 * or 0 (perfect clock) if clock has no parent. 187 * 188 * @get_phase: Queries the hardware to get the current phase of a clock. 189 * Returned values are 0-359 degrees on success, negative 190 * error codes on failure. 191 * 192 * @set_phase: Shift the phase this clock signal in degrees specified 193 * by the second argument. Valid values for degrees are 194 * 0-359. Return 0 on success, otherwise -EERROR. 195 * 196 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio 197 * of a clock. Returned values denominator cannot be 0 and must be 198 * superior or equal to the numerator. 199 * 200 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by 201 * the numerator (2nd argurment) and denominator (3rd argument). 202 * Argument must be a valid ratio (denominator > 0 203 * and >= numerator) Return 0 on success, otherwise -EERROR. 204 * 205 * @init: Perform platform-specific initialization magic. 206 * This is not used by any of the basic clock types. 207 * This callback exist for HW which needs to perform some 208 * initialisation magic for CCF to get an accurate view of the 209 * clock. It may also be used dynamic resource allocation is 210 * required. It shall not used to deal with clock parameters, 211 * such as rate or parents. 212 * Returns 0 on success, -EERROR otherwise. 213 * 214 * @terminate: Free any resource allocated by init. 215 * 216 * @debug_init: Set up type-specific debugfs entries for this clock. This 217 * is called once, after the debugfs directory entry for this 218 * clock has been created. The dentry pointer representing that 219 * directory is provided as an argument. Called with 220 * prepare_lock held. Returns 0 on success, -EERROR otherwise. 221 * 222 * 223 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow 224 * implementations to split any work between atomic (enable) and sleepable 225 * (prepare) contexts. If enabling a clock requires code that might sleep, 226 * this must be done in clk_prepare. Clock enable code that will never be 227 * called in a sleepable context may be implemented in clk_enable. 228 * 229 * Typically, drivers will call clk_prepare when a clock may be needed later 230 * (eg. when a device is opened), and clk_enable when the clock is actually 231 * required (eg. from an interrupt). Note that clk_prepare MUST have been 232 * called before clk_enable. 233 */ 234struct clk_ops { 235 int (*prepare)(struct clk_hw *hw); 236 void (*unprepare)(struct clk_hw *hw); 237 int (*is_prepared)(struct clk_hw *hw); 238 void (*unprepare_unused)(struct clk_hw *hw); 239 int (*enable)(struct clk_hw *hw); 240 void (*disable)(struct clk_hw *hw); 241 int (*is_enabled)(struct clk_hw *hw); 242 void (*disable_unused)(struct clk_hw *hw); 243 int (*save_context)(struct clk_hw *hw); 244 void (*restore_context)(struct clk_hw *hw); 245 unsigned long (*recalc_rate)(struct clk_hw *hw, 246 unsigned long parent_rate); 247 long (*round_rate)(struct clk_hw *hw, unsigned long rate, 248 unsigned long *parent_rate); 249 int (*determine_rate)(struct clk_hw *hw, 250 struct clk_rate_request *req); 251 int (*set_parent)(struct clk_hw *hw, u8 index); 252 u8 (*get_parent)(struct clk_hw *hw); 253 int (*set_rate)(struct clk_hw *hw, unsigned long rate, 254 unsigned long parent_rate); 255 int (*set_rate_and_parent)(struct clk_hw *hw, 256 unsigned long rate, 257 unsigned long parent_rate, u8 index); 258 unsigned long (*recalc_accuracy)(struct clk_hw *hw, 259 unsigned long parent_accuracy); 260 int (*get_phase)(struct clk_hw *hw); 261 int (*set_phase)(struct clk_hw *hw, int degrees); 262 int (*get_duty_cycle)(struct clk_hw *hw, 263 struct clk_duty *duty); 264 int (*set_duty_cycle)(struct clk_hw *hw, 265 struct clk_duty *duty); 266 int (*init)(struct clk_hw *hw); 267 void (*terminate)(struct clk_hw *hw); 268 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry); 269}; 270 271/** 272 * struct clk_parent_data - clk parent information 273 * @hw: parent clk_hw pointer (used for clk providers with internal clks) 274 * @fw_name: parent name local to provider registering clk 275 * @name: globally unique parent name (used as a fallback) 276 * @index: parent index local to provider registering clk (if @fw_name absent) 277 */ 278struct clk_parent_data { 279 const struct clk_hw *hw; 280 const char *fw_name; 281 const char *name; 282 int index; 283}; 284 285/** 286 * struct clk_init_data - holds init data that's common to all clocks and is 287 * shared between the clock provider and the common clock framework. 288 * 289 * @name: clock name 290 * @ops: operations this clock supports 291 * @parent_names: array of string names for all possible parents 292 * @parent_data: array of parent data for all possible parents (when some 293 * parents are external to the clk controller) 294 * @parent_hws: array of pointers to all possible parents (when all parents 295 * are internal to the clk controller) 296 * @num_parents: number of possible parents 297 * @flags: framework-level hints and quirks 298 */ 299struct clk_init_data { 300 const char *name; 301 const struct clk_ops *ops; 302 /* Only one of the following three should be assigned */ 303 const char * const *parent_names; 304 const struct clk_parent_data *parent_data; 305 const struct clk_hw **parent_hws; 306 u8 num_parents; 307 unsigned long flags; 308}; 309 310/** 311 * struct clk_hw - handle for traversing from a struct clk to its corresponding 312 * hardware-specific structure. struct clk_hw should be declared within struct 313 * clk_foo and then referenced by the struct clk instance that uses struct 314 * clk_foo's clk_ops 315 * 316 * @core: pointer to the struct clk_core instance that points back to this 317 * struct clk_hw instance 318 * 319 * @clk: pointer to the per-user struct clk instance that can be used to call 320 * into the clk API 321 * 322 * @init: pointer to struct clk_init_data that contains the init data shared 323 * with the common clock framework. This pointer will be set to NULL once 324 * a clk_register() variant is called on this clk_hw pointer. 325 */ 326struct clk_hw { 327 struct clk_core *core; 328 struct clk *clk; 329 const struct clk_init_data *init; 330}; 331 332/* 333 * DOC: Basic clock implementations common to many platforms 334 * 335 * Each basic clock hardware type is comprised of a structure describing the 336 * clock hardware, implementations of the relevant callbacks in struct clk_ops, 337 * unique flags for that hardware type, a registration function and an 338 * alternative macro for static initialization 339 */ 340 341/** 342 * struct clk_fixed_rate - fixed-rate clock 343 * @hw: handle between common and hardware-specific interfaces 344 * @fixed_rate: constant frequency of clock 345 * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion) 346 * @flags: hardware specific flags 347 * 348 * Flags: 349 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk 350 * instead of what's set in @fixed_accuracy. 351 */ 352struct clk_fixed_rate { 353 struct clk_hw hw; 354 unsigned long fixed_rate; 355 unsigned long fixed_accuracy; 356 unsigned long flags; 357}; 358 359#define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0) 360 361extern const struct clk_ops clk_fixed_rate_ops; 362struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev, 363 struct device_node *np, const char *name, 364 const char *parent_name, const struct clk_hw *parent_hw, 365 const struct clk_parent_data *parent_data, unsigned long flags, 366 unsigned long fixed_rate, unsigned long fixed_accuracy, 367 unsigned long clk_fixed_flags, bool devm); 368struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 369 const char *parent_name, unsigned long flags, 370 unsigned long fixed_rate); 371/** 372 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock 373 * framework 374 * @dev: device that is registering this clock 375 * @name: name of this clock 376 * @parent_name: name of clock's parent 377 * @flags: framework-specific flags 378 * @fixed_rate: non-adjustable clock rate 379 */ 380#define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \ 381 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \ 382 NULL, (flags), (fixed_rate), 0, 0, false) 383 384/** 385 * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock 386 * framework 387 * @dev: device that is registering this clock 388 * @name: name of this clock 389 * @parent_name: name of clock's parent 390 * @flags: framework-specific flags 391 * @fixed_rate: non-adjustable clock rate 392 */ 393#define devm_clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \ 394 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \ 395 NULL, (flags), (fixed_rate), 0, 0, true) 396/** 397 * devm_clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with 398 * the clock framework 399 * @dev: device that is registering this clock 400 * @name: name of this clock 401 * @parent_data: parent clk data 402 * @flags: framework-specific flags 403 * @fixed_rate: non-adjustable clock rate 404 */ 405#define devm_clk_hw_register_fixed_rate_parent_data(dev, name, parent_data, flags, \ 406 fixed_rate) \ 407 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ 408 (parent_data), (flags), (fixed_rate), 0, \ 409 0, true) 410/** 411 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with 412 * the clock framework 413 * @dev: device that is registering this clock 414 * @name: name of this clock 415 * @parent_hw: pointer to parent clk 416 * @flags: framework-specific flags 417 * @fixed_rate: non-adjustable clock rate 418 */ 419#define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \ 420 fixed_rate) \ 421 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \ 422 NULL, (flags), (fixed_rate), 0, 0, false) 423/** 424 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with 425 * the clock framework 426 * @dev: device that is registering this clock 427 * @name: name of this clock 428 * @parent_data: parent clk data 429 * @flags: framework-specific flags 430 * @fixed_rate: non-adjustable clock rate 431 */ 432#define clk_hw_register_fixed_rate_parent_data(dev, name, parent_data, flags, \ 433 fixed_rate) \ 434 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ 435 (parent_data), (flags), (fixed_rate), 0, \ 436 0, false) 437/** 438 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with 439 * the clock framework 440 * @dev: device that is registering this clock 441 * @name: name of this clock 442 * @parent_name: name of clock's parent 443 * @flags: framework-specific flags 444 * @fixed_rate: non-adjustable clock rate 445 * @fixed_accuracy: non-adjustable clock accuracy 446 */ 447#define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \ 448 flags, fixed_rate, \ 449 fixed_accuracy) \ 450 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \ 451 NULL, NULL, (flags), (fixed_rate), \ 452 (fixed_accuracy), 0, false) 453/** 454 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate 455 * clock with the clock framework 456 * @dev: device that is registering this clock 457 * @name: name of this clock 458 * @parent_hw: pointer to parent clk 459 * @flags: framework-specific flags 460 * @fixed_rate: non-adjustable clock rate 461 * @fixed_accuracy: non-adjustable clock accuracy 462 */ 463#define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \ 464 parent_hw, flags, fixed_rate, fixed_accuracy) \ 465 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \ 466 NULL, (flags), (fixed_rate), \ 467 (fixed_accuracy), 0, false) 468/** 469 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate 470 * clock with the clock framework 471 * @dev: device that is registering this clock 472 * @name: name of this clock 473 * @parent_data: name of clock's parent 474 * @flags: framework-specific flags 475 * @fixed_rate: non-adjustable clock rate 476 * @fixed_accuracy: non-adjustable clock accuracy 477 */ 478#define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \ 479 parent_data, flags, fixed_rate, fixed_accuracy) \ 480 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ 481 (parent_data), NULL, (flags), \ 482 (fixed_rate), (fixed_accuracy), 0, false) 483/** 484 * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with 485 * the clock framework 486 * @dev: device that is registering this clock 487 * @name: name of this clock 488 * @parent_data: name of clock's parent 489 * @flags: framework-specific flags 490 * @fixed_rate: non-adjustable clock rate 491 */ 492#define clk_hw_register_fixed_rate_parent_accuracy(dev, name, parent_data, \ 493 flags, fixed_rate) \ 494 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ 495 (parent_data), (flags), (fixed_rate), 0, \ 496 CLK_FIXED_RATE_PARENT_ACCURACY, false) 497 498void clk_unregister_fixed_rate(struct clk *clk); 499void clk_hw_unregister_fixed_rate(struct clk_hw *hw); 500 501void of_fixed_clk_setup(struct device_node *np); 502 503/** 504 * struct clk_gate - gating clock 505 * 506 * @hw: handle between common and hardware-specific interfaces 507 * @reg: register controlling gate 508 * @bit_idx: single bit controlling gate 509 * @flags: hardware-specific flags 510 * @lock: register lock 511 * 512 * Clock which can gate its output. Implements .enable & .disable 513 * 514 * Flags: 515 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to 516 * enable the clock. Setting this flag does the opposite: setting the bit 517 * disable the clock and clearing it enables the clock 518 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit 519 * of this register, and mask of gate bits are in higher 16-bit of this 520 * register. While setting the gate bits, higher 16-bit should also be 521 * updated to indicate changing gate bits. 522 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for 523 * the gate register. Setting this flag makes the register accesses big 524 * endian. 525 */ 526struct clk_gate { 527 struct clk_hw hw; 528 void __iomem *reg; 529 u8 bit_idx; 530 u8 flags; 531 spinlock_t *lock; 532}; 533 534#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) 535 536#define CLK_GATE_SET_TO_DISABLE BIT(0) 537#define CLK_GATE_HIWORD_MASK BIT(1) 538#define CLK_GATE_BIG_ENDIAN BIT(2) 539 540extern const struct clk_ops clk_gate_ops; 541struct clk_hw *__clk_hw_register_gate(struct device *dev, 542 struct device_node *np, const char *name, 543 const char *parent_name, const struct clk_hw *parent_hw, 544 const struct clk_parent_data *parent_data, 545 unsigned long flags, 546 void __iomem *reg, u8 bit_idx, 547 u8 clk_gate_flags, spinlock_t *lock); 548struct clk_hw *__devm_clk_hw_register_gate(struct device *dev, 549 struct device_node *np, const char *name, 550 const char *parent_name, const struct clk_hw *parent_hw, 551 const struct clk_parent_data *parent_data, 552 unsigned long flags, 553 void __iomem *reg, u8 bit_idx, 554 u8 clk_gate_flags, spinlock_t *lock); 555struct clk *clk_register_gate(struct device *dev, const char *name, 556 const char *parent_name, unsigned long flags, 557 void __iomem *reg, u8 bit_idx, 558 u8 clk_gate_flags, spinlock_t *lock); 559/** 560 * clk_hw_register_gate - register a gate clock with the clock framework 561 * @dev: device that is registering this clock 562 * @name: name of this clock 563 * @parent_name: name of this clock's parent 564 * @flags: framework-specific flags for this clock 565 * @reg: register address to control gating of this clock 566 * @bit_idx: which bit in the register controls gating of this clock 567 * @clk_gate_flags: gate-specific flags for this clock 568 * @lock: shared register lock for this clock 569 */ 570#define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \ 571 clk_gate_flags, lock) \ 572 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ 573 NULL, (flags), (reg), (bit_idx), \ 574 (clk_gate_flags), (lock)) 575/** 576 * clk_hw_register_gate_parent_hw - register a gate clock with the clock 577 * framework 578 * @dev: device that is registering this clock 579 * @name: name of this clock 580 * @parent_hw: pointer to parent clk 581 * @flags: framework-specific flags for this clock 582 * @reg: register address to control gating of this clock 583 * @bit_idx: which bit in the register controls gating of this clock 584 * @clk_gate_flags: gate-specific flags for this clock 585 * @lock: shared register lock for this clock 586 */ 587#define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \ 588 bit_idx, clk_gate_flags, lock) \ 589 __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \ 590 NULL, (flags), (reg), (bit_idx), \ 591 (clk_gate_flags), (lock)) 592/** 593 * clk_hw_register_gate_parent_data - register a gate clock with the clock 594 * framework 595 * @dev: device that is registering this clock 596 * @name: name of this clock 597 * @parent_data: parent clk data 598 * @flags: framework-specific flags for this clock 599 * @reg: register address to control gating of this clock 600 * @bit_idx: which bit in the register controls gating of this clock 601 * @clk_gate_flags: gate-specific flags for this clock 602 * @lock: shared register lock for this clock 603 */ 604#define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \ 605 bit_idx, clk_gate_flags, lock) \ 606 __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \ 607 (flags), (reg), (bit_idx), \ 608 (clk_gate_flags), (lock)) 609/** 610 * devm_clk_hw_register_gate - register a gate clock with the clock framework 611 * @dev: device that is registering this clock 612 * @name: name of this clock 613 * @parent_name: name of this clock's parent 614 * @flags: framework-specific flags for this clock 615 * @reg: register address to control gating of this clock 616 * @bit_idx: which bit in the register controls gating of this clock 617 * @clk_gate_flags: gate-specific flags for this clock 618 * @lock: shared register lock for this clock 619 */ 620#define devm_clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,\ 621 clk_gate_flags, lock) \ 622 __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ 623 NULL, (flags), (reg), (bit_idx), \ 624 (clk_gate_flags), (lock)) 625/** 626 * devm_clk_hw_register_gate_parent_hw - register a gate clock with the clock 627 * framework 628 * @dev: device that is registering this clock 629 * @name: name of this clock 630 * @parent_hw: pointer to parent clk 631 * @flags: framework-specific flags for this clock 632 * @reg: register address to control gating of this clock 633 * @bit_idx: which bit in the register controls gating of this clock 634 * @clk_gate_flags: gate-specific flags for this clock 635 * @lock: shared register lock for this clock 636 */ 637#define devm_clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, \ 638 reg, bit_idx, clk_gate_flags, \ 639 lock) \ 640 __devm_clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \ 641 NULL, (flags), (reg), (bit_idx), \ 642 (clk_gate_flags), (lock)) 643/** 644 * devm_clk_hw_register_gate_parent_data - register a gate clock with the 645 * clock framework 646 * @dev: device that is registering this clock 647 * @name: name of this clock 648 * @parent_data: parent clk data 649 * @flags: framework-specific flags for this clock 650 * @reg: register address to control gating of this clock 651 * @bit_idx: which bit in the register controls gating of this clock 652 * @clk_gate_flags: gate-specific flags for this clock 653 * @lock: shared register lock for this clock 654 */ 655#define devm_clk_hw_register_gate_parent_data(dev, name, parent_data, flags, \ 656 reg, bit_idx, clk_gate_flags, \ 657 lock) \ 658 __devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL, \ 659 (parent_data), (flags), (reg), (bit_idx), \ 660 (clk_gate_flags), (lock)) 661 662void clk_unregister_gate(struct clk *clk); 663void clk_hw_unregister_gate(struct clk_hw *hw); 664int clk_gate_is_enabled(struct clk_hw *hw); 665 666struct clk_div_table { 667 unsigned int val; 668 unsigned int div; 669}; 670 671/** 672 * struct clk_divider - adjustable divider clock 673 * 674 * @hw: handle between common and hardware-specific interfaces 675 * @reg: register containing the divider 676 * @shift: shift to the divider bit field 677 * @width: width of the divider bit field 678 * @table: array of value/divider pairs, last entry should have div = 0 679 * @lock: register lock 680 * 681 * Clock with an adjustable divider affecting its output frequency. Implements 682 * .recalc_rate, .set_rate and .round_rate 683 * 684 * @flags: 685 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the 686 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is 687 * the raw value read from the register, with the value of zero considered 688 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. 689 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from 690 * the hardware register 691 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have 692 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. 693 * Some hardware implementations gracefully handle this case and allow a 694 * zero divisor by not modifying their input clock 695 * (divide by one / bypass). 696 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit 697 * of this register, and mask of divider bits are in higher 16-bit of this 698 * register. While setting the divider bits, higher 16-bit should also be 699 * updated to indicate changing divider bits. 700 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded 701 * to the closest integer instead of the up one. 702 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should 703 * not be changed by the clock framework. 704 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED 705 * except when the value read from the register is zero, the divisor is 706 * 2^width of the field. 707 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used 708 * for the divider register. Setting this flag makes the register accesses 709 * big endian. 710 * CLK_DIVIDER_EVEN_INTEGERS - clock divisor is 2, 4, 6, 8, 10, etc. 711 * Formula is 2 * (value read from hardware + 1). 712 */ 713struct clk_divider { 714 struct clk_hw hw; 715 void __iomem *reg; 716 u8 shift; 717 u8 width; 718 u16 flags; 719 const struct clk_div_table *table; 720 spinlock_t *lock; 721}; 722 723#define clk_div_mask(width) ((1 << (width)) - 1) 724#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) 725 726#define CLK_DIVIDER_ONE_BASED BIT(0) 727#define CLK_DIVIDER_POWER_OF_TWO BIT(1) 728#define CLK_DIVIDER_ALLOW_ZERO BIT(2) 729#define CLK_DIVIDER_HIWORD_MASK BIT(3) 730#define CLK_DIVIDER_ROUND_CLOSEST BIT(4) 731#define CLK_DIVIDER_READ_ONLY BIT(5) 732#define CLK_DIVIDER_MAX_AT_ZERO BIT(6) 733#define CLK_DIVIDER_BIG_ENDIAN BIT(7) 734#define CLK_DIVIDER_EVEN_INTEGERS BIT(8) 735 736extern const struct clk_ops clk_divider_ops; 737extern const struct clk_ops clk_divider_ro_ops; 738 739unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, 740 unsigned int val, const struct clk_div_table *table, 741 unsigned long flags, unsigned long width); 742long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, 743 unsigned long rate, unsigned long *prate, 744 const struct clk_div_table *table, 745 u8 width, unsigned long flags); 746long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, 747 unsigned long rate, unsigned long *prate, 748 const struct clk_div_table *table, u8 width, 749 unsigned long flags, unsigned int val); 750int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, 751 const struct clk_div_table *table, u8 width, 752 unsigned long flags); 753int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, 754 const struct clk_div_table *table, u8 width, 755 unsigned long flags, unsigned int val); 756int divider_get_val(unsigned long rate, unsigned long parent_rate, 757 const struct clk_div_table *table, u8 width, 758 unsigned long flags); 759 760struct clk_hw *__clk_hw_register_divider(struct device *dev, 761 struct device_node *np, const char *name, 762 const char *parent_name, const struct clk_hw *parent_hw, 763 const struct clk_parent_data *parent_data, unsigned long flags, 764 void __iomem *reg, u8 shift, u8 width, 765 unsigned long clk_divider_flags, 766 const struct clk_div_table *table, spinlock_t *lock); 767struct clk_hw *__devm_clk_hw_register_divider(struct device *dev, 768 struct device_node *np, const char *name, 769 const char *parent_name, const struct clk_hw *parent_hw, 770 const struct clk_parent_data *parent_data, unsigned long flags, 771 void __iomem *reg, u8 shift, u8 width, 772 unsigned long clk_divider_flags, 773 const struct clk_div_table *table, spinlock_t *lock); 774struct clk *clk_register_divider_table(struct device *dev, const char *name, 775 const char *parent_name, unsigned long flags, 776 void __iomem *reg, u8 shift, u8 width, 777 unsigned long clk_divider_flags, 778 const struct clk_div_table *table, spinlock_t *lock); 779/** 780 * clk_register_divider - register a divider clock with the clock framework 781 * @dev: device registering this clock 782 * @name: name of this clock 783 * @parent_name: name of clock's parent 784 * @flags: framework-specific flags 785 * @reg: register address to adjust divider 786 * @shift: number of bits to shift the bitfield 787 * @width: width of the bitfield 788 * @clk_divider_flags: divider-specific flags for this clock 789 * @lock: shared register lock for this clock 790 */ 791#define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \ 792 clk_divider_flags, lock) \ 793 clk_register_divider_table((dev), (name), (parent_name), (flags), \ 794 (reg), (shift), (width), \ 795 (clk_divider_flags), NULL, (lock)) 796/** 797 * clk_hw_register_divider - register a divider clock with the clock framework 798 * @dev: device registering this clock 799 * @name: name of this clock 800 * @parent_name: name of clock's parent 801 * @flags: framework-specific flags 802 * @reg: register address to adjust divider 803 * @shift: number of bits to shift the bitfield 804 * @width: width of the bitfield 805 * @clk_divider_flags: divider-specific flags for this clock 806 * @lock: shared register lock for this clock 807 */ 808#define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ 809 width, clk_divider_flags, lock) \ 810 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ 811 NULL, (flags), (reg), (shift), (width), \ 812 (clk_divider_flags), NULL, (lock)) 813/** 814 * clk_hw_register_divider_parent_hw - register a divider clock with the clock 815 * framework 816 * @dev: device registering this clock 817 * @name: name of this clock 818 * @parent_hw: pointer to parent clk 819 * @flags: framework-specific flags 820 * @reg: register address to adjust divider 821 * @shift: number of bits to shift the bitfield 822 * @width: width of the bitfield 823 * @clk_divider_flags: divider-specific flags for this clock 824 * @lock: shared register lock for this clock 825 */ 826#define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \ 827 shift, width, clk_divider_flags, \ 828 lock) \ 829 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \ 830 NULL, (flags), (reg), (shift), (width), \ 831 (clk_divider_flags), NULL, (lock)) 832/** 833 * clk_hw_register_divider_parent_data - register a divider clock with the clock 834 * framework 835 * @dev: device registering this clock 836 * @name: name of this clock 837 * @parent_data: parent clk data 838 * @flags: framework-specific flags 839 * @reg: register address to adjust divider 840 * @shift: number of bits to shift the bitfield 841 * @width: width of the bitfield 842 * @clk_divider_flags: divider-specific flags for this clock 843 * @lock: shared register lock for this clock 844 */ 845#define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \ 846 reg, shift, width, \ 847 clk_divider_flags, lock) \ 848 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \ 849 (parent_data), (flags), (reg), (shift), \ 850 (width), (clk_divider_flags), NULL, (lock)) 851/** 852 * clk_hw_register_divider_table - register a table based divider clock with 853 * the clock framework 854 * @dev: device registering this clock 855 * @name: name of this clock 856 * @parent_name: name of clock's parent 857 * @flags: framework-specific flags 858 * @reg: register address to adjust divider 859 * @shift: number of bits to shift the bitfield 860 * @width: width of the bitfield 861 * @clk_divider_flags: divider-specific flags for this clock 862 * @table: array of divider/value pairs ending with a div set to 0 863 * @lock: shared register lock for this clock 864 */ 865#define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \ 866 shift, width, clk_divider_flags, table, \ 867 lock) \ 868 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ 869 NULL, (flags), (reg), (shift), (width), \ 870 (clk_divider_flags), (table), (lock)) 871/** 872 * clk_hw_register_divider_table_parent_hw - register a table based divider 873 * clock with the clock framework 874 * @dev: device registering this clock 875 * @name: name of this clock 876 * @parent_hw: pointer to parent clk 877 * @flags: framework-specific flags 878 * @reg: register address to adjust divider 879 * @shift: number of bits to shift the bitfield 880 * @width: width of the bitfield 881 * @clk_divider_flags: divider-specific flags for this clock 882 * @table: array of divider/value pairs ending with a div set to 0 883 * @lock: shared register lock for this clock 884 */ 885#define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \ 886 reg, shift, width, \ 887 clk_divider_flags, table, \ 888 lock) \ 889 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \ 890 NULL, (flags), (reg), (shift), (width), \ 891 (clk_divider_flags), (table), (lock)) 892/** 893 * clk_hw_register_divider_table_parent_data - register a table based divider 894 * clock with the clock framework 895 * @dev: device registering this clock 896 * @name: name of this clock 897 * @parent_data: parent clk data 898 * @flags: framework-specific flags 899 * @reg: register address to adjust divider 900 * @shift: number of bits to shift the bitfield 901 * @width: width of the bitfield 902 * @clk_divider_flags: divider-specific flags for this clock 903 * @table: array of divider/value pairs ending with a div set to 0 904 * @lock: shared register lock for this clock 905 */ 906#define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \ 907 flags, reg, shift, width, \ 908 clk_divider_flags, table, \ 909 lock) \ 910 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \ 911 (parent_data), (flags), (reg), (shift), \ 912 (width), (clk_divider_flags), (table), \ 913 (lock)) 914/** 915 * devm_clk_hw_register_divider - register a divider clock with the clock framework 916 * @dev: device registering this clock 917 * @name: name of this clock 918 * @parent_name: name of clock's parent 919 * @flags: framework-specific flags 920 * @reg: register address to adjust divider 921 * @shift: number of bits to shift the bitfield 922 * @width: width of the bitfield 923 * @clk_divider_flags: divider-specific flags for this clock 924 * @lock: shared register lock for this clock 925 */ 926#define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ 927 width, clk_divider_flags, lock) \ 928 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ 929 NULL, (flags), (reg), (shift), (width), \ 930 (clk_divider_flags), NULL, (lock)) 931/** 932 * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework 933 * @dev: device registering this clock 934 * @name: name of this clock 935 * @parent_hw: pointer to parent clk 936 * @flags: framework-specific flags 937 * @reg: register address to adjust divider 938 * @shift: number of bits to shift the bitfield 939 * @width: width of the bitfield 940 * @clk_divider_flags: divider-specific flags for this clock 941 * @lock: shared register lock for this clock 942 */ 943#define devm_clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, \ 944 reg, shift, width, \ 945 clk_divider_flags, lock) \ 946 __devm_clk_hw_register_divider((dev), NULL, (name), NULL, \ 947 (parent_hw), NULL, (flags), (reg), \ 948 (shift), (width), (clk_divider_flags), \ 949 NULL, (lock)) 950/** 951 * devm_clk_hw_register_divider_table - register a table based divider clock 952 * with the clock framework (devres variant) 953 * @dev: device registering this clock 954 * @name: name of this clock 955 * @parent_name: name of clock's parent 956 * @flags: framework-specific flags 957 * @reg: register address to adjust divider 958 * @shift: number of bits to shift the bitfield 959 * @width: width of the bitfield 960 * @clk_divider_flags: divider-specific flags for this clock 961 * @table: array of divider/value pairs ending with a div set to 0 962 * @lock: shared register lock for this clock 963 */ 964#define devm_clk_hw_register_divider_table(dev, name, parent_name, flags, \ 965 reg, shift, width, \ 966 clk_divider_flags, table, lock) \ 967 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), \ 968 NULL, NULL, (flags), (reg), (shift), \ 969 (width), (clk_divider_flags), (table), \ 970 (lock)) 971 972void clk_unregister_divider(struct clk *clk); 973void clk_hw_unregister_divider(struct clk_hw *hw); 974 975/** 976 * struct clk_mux - multiplexer clock 977 * 978 * @hw: handle between common and hardware-specific interfaces 979 * @reg: register controlling multiplexer 980 * @table: array of register values corresponding to the parent index 981 * @shift: shift to multiplexer bit field 982 * @mask: mask of mutliplexer bit field 983 * @flags: hardware-specific flags 984 * @lock: register lock 985 * 986 * Clock with multiple selectable parents. Implements .get_parent, .set_parent 987 * and .recalc_rate 988 * 989 * Flags: 990 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 991 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) 992 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this 993 * register, and mask of mux bits are in higher 16-bit of this register. 994 * While setting the mux bits, higher 16-bit should also be updated to 995 * indicate changing mux bits. 996 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the 997 * .get_parent clk_op. 998 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired 999 * frequency. 1000 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for 1001 * the mux register. Setting this flag makes the register accesses big 1002 * endian. 1003 */ 1004struct clk_mux { 1005 struct clk_hw hw; 1006 void __iomem *reg; 1007 const u32 *table; 1008 u32 mask; 1009 u8 shift; 1010 u8 flags; 1011 spinlock_t *lock; 1012}; 1013 1014#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) 1015 1016#define CLK_MUX_INDEX_ONE BIT(0) 1017#define CLK_MUX_INDEX_BIT BIT(1) 1018#define CLK_MUX_HIWORD_MASK BIT(2) 1019#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ 1020#define CLK_MUX_ROUND_CLOSEST BIT(4) 1021#define CLK_MUX_BIG_ENDIAN BIT(5) 1022 1023extern const struct clk_ops clk_mux_ops; 1024extern const struct clk_ops clk_mux_ro_ops; 1025 1026struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np, 1027 const char *name, u8 num_parents, 1028 const char * const *parent_names, 1029 const struct clk_hw **parent_hws, 1030 const struct clk_parent_data *parent_data, 1031 unsigned long flags, void __iomem *reg, u8 shift, u32 mask, 1032 u8 clk_mux_flags, const u32 *table, spinlock_t *lock); 1033struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np, 1034 const char *name, u8 num_parents, 1035 const char * const *parent_names, 1036 const struct clk_hw **parent_hws, 1037 const struct clk_parent_data *parent_data, 1038 unsigned long flags, void __iomem *reg, u8 shift, u32 mask, 1039 u8 clk_mux_flags, const u32 *table, spinlock_t *lock); 1040struct clk *clk_register_mux_table(struct device *dev, const char *name, 1041 const char * const *parent_names, u8 num_parents, 1042 unsigned long flags, void __iomem *reg, u8 shift, u32 mask, 1043 u8 clk_mux_flags, const u32 *table, spinlock_t *lock); 1044 1045#define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \ 1046 shift, width, clk_mux_flags, lock) \ 1047 clk_register_mux_table((dev), (name), (parent_names), (num_parents), \ 1048 (flags), (reg), (shift), BIT((width)) - 1, \ 1049 (clk_mux_flags), NULL, (lock)) 1050#define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \ 1051 flags, reg, shift, mask, clk_mux_flags, \ 1052 table, lock) \ 1053 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \ 1054 (parent_names), NULL, NULL, (flags), (reg), \ 1055 (shift), (mask), (clk_mux_flags), (table), \ 1056 (lock)) 1057#define clk_hw_register_mux_table_parent_data(dev, name, parent_data, \ 1058 num_parents, flags, reg, shift, mask, \ 1059 clk_mux_flags, table, lock) \ 1060 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \ 1061 NULL, NULL, (parent_data), (flags), (reg), \ 1062 (shift), (mask), (clk_mux_flags), (table), \ 1063 (lock)) 1064#define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ 1065 shift, width, clk_mux_flags, lock) \ 1066 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \ 1067 (parent_names), NULL, NULL, (flags), (reg), \ 1068 (shift), BIT((width)) - 1, (clk_mux_flags), \ 1069 NULL, (lock)) 1070#define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \ 1071 reg, shift, width, clk_mux_flags, lock) \ 1072 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ 1073 (parent_hws), NULL, (flags), (reg), (shift), \ 1074 BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) 1075#define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \ 1076 flags, reg, shift, width, \ 1077 clk_mux_flags, lock) \ 1078 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ 1079 (parent_data), (flags), (reg), (shift), \ 1080 BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) 1081#define clk_hw_register_mux_parent_data_table(dev, name, parent_data, \ 1082 num_parents, flags, reg, shift, \ 1083 width, clk_mux_flags, table, \ 1084 lock) \ 1085 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ 1086 (parent_data), (flags), (reg), (shift), \ 1087 BIT((width)) - 1, (clk_mux_flags), table, (lock)) 1088#define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ 1089 shift, width, clk_mux_flags, lock) \ 1090 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \ 1091 (parent_names), NULL, NULL, (flags), (reg), \ 1092 (shift), BIT((width)) - 1, (clk_mux_flags), \ 1093 NULL, (lock)) 1094#define devm_clk_hw_register_mux_parent_hws(dev, name, parent_hws, \ 1095 num_parents, flags, reg, shift, \ 1096 width, clk_mux_flags, lock) \ 1097 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ 1098 (parent_hws), NULL, (flags), (reg), \ 1099 (shift), BIT((width)) - 1, \ 1100 (clk_mux_flags), NULL, (lock)) 1101#define devm_clk_hw_register_mux_parent_data_table(dev, name, parent_data, \ 1102 num_parents, flags, reg, shift, \ 1103 width, clk_mux_flags, table, \ 1104 lock) \ 1105 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ 1106 NULL, (parent_data), (flags), (reg), (shift), \ 1107 BIT((width)) - 1, (clk_mux_flags), table, (lock)) 1108 1109int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int flags, 1110 unsigned int val); 1111unsigned int clk_mux_index_to_val(const u32 *table, unsigned int flags, u8 index); 1112 1113void clk_unregister_mux(struct clk *clk); 1114void clk_hw_unregister_mux(struct clk_hw *hw); 1115 1116void of_fixed_factor_clk_setup(struct device_node *node); 1117 1118/** 1119 * struct clk_fixed_factor - fixed multiplier and divider clock 1120 * 1121 * @hw: handle between common and hardware-specific interfaces 1122 * @mult: multiplier 1123 * @div: divider 1124 * @acc: fixed accuracy in ppb 1125 * @flags: behavior modifying flags 1126 * 1127 * Clock with a fixed multiplier and divider. The output frequency is the 1128 * parent clock rate divided by div and multiplied by mult. 1129 * Implements .recalc_rate, .set_rate, .round_rate and .recalc_accuracy 1130 * 1131 * Flags: 1132 * * CLK_FIXED_FACTOR_FIXED_ACCURACY - Use the value in @acc instead of the 1133 * parent clk accuracy. 1134 */ 1135 1136struct clk_fixed_factor { 1137 struct clk_hw hw; 1138 unsigned int mult; 1139 unsigned int div; 1140 unsigned long acc; 1141 unsigned int flags; 1142}; 1143 1144#define CLK_FIXED_FACTOR_FIXED_ACCURACY BIT(0) 1145 1146#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) 1147 1148extern const struct clk_ops clk_fixed_factor_ops; 1149struct clk *clk_register_fixed_factor(struct device *dev, const char *name, 1150 const char *parent_name, unsigned long flags, 1151 unsigned int mult, unsigned int div); 1152void clk_unregister_fixed_factor(struct clk *clk); 1153struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, 1154 const char *name, const char *parent_name, unsigned long flags, 1155 unsigned int mult, unsigned int div); 1156struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev, 1157 struct device_node *np, const char *name, const char *fw_name, 1158 unsigned long flags, unsigned int mult, unsigned int div); 1159struct clk_hw *clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev, 1160 struct device_node *np, const char *name, const char *fw_name, 1161 unsigned long flags, unsigned int mult, unsigned int div, 1162 unsigned long acc); 1163struct clk_hw *clk_hw_register_fixed_factor_index(struct device *dev, 1164 const char *name, unsigned int index, unsigned long flags, 1165 unsigned int mult, unsigned int div); 1166void clk_hw_unregister_fixed_factor(struct clk_hw *hw); 1167struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, 1168 const char *name, const char *parent_name, unsigned long flags, 1169 unsigned int mult, unsigned int div); 1170struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev, 1171 struct device_node *np, const char *name, const char *fw_name, 1172 unsigned long flags, unsigned int mult, unsigned int div); 1173struct clk_hw *devm_clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev, 1174 struct device_node *np, const char *name, const char *fw_name, 1175 unsigned long flags, unsigned int mult, unsigned int div, 1176 unsigned long acc); 1177struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, 1178 const char *name, unsigned int index, unsigned long flags, 1179 unsigned int mult, unsigned int div); 1180 1181struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev, 1182 const char *name, const struct clk_hw *parent_hw, 1183 unsigned long flags, unsigned int mult, unsigned int div); 1184 1185struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev, 1186 const char *name, const struct clk_hw *parent_hw, 1187 unsigned long flags, unsigned int mult, unsigned int div); 1188/** 1189 * struct clk_fractional_divider - adjustable fractional divider clock 1190 * 1191 * @hw: handle between common and hardware-specific interfaces 1192 * @reg: register containing the divider 1193 * @mshift: shift to the numerator bit field 1194 * @mwidth: width of the numerator bit field 1195 * @nshift: shift to the denominator bit field 1196 * @nwidth: width of the denominator bit field 1197 * @approximation: clk driver's callback for calculating the divider clock 1198 * @lock: register lock 1199 * 1200 * Clock with adjustable fractional divider affecting its output frequency. 1201 * 1202 * @flags: 1203 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator 1204 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED 1205 * is set then the numerator and denominator are both the value read 1206 * plus one. 1207 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are 1208 * used for the divider register. Setting this flag makes the register 1209 * accesses big endian. 1210 * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might 1211 * be saturated and the caller will get quite far from the good enough 1212 * approximation. Instead the caller may require, by setting this flag, 1213 * to shift left by a few bits in case, when the asked one is quite small 1214 * to satisfy the desired range of denominator. It assumes that on the 1215 * caller's side the power-of-two capable prescaler exists. 1216 */ 1217struct clk_fractional_divider { 1218 struct clk_hw hw; 1219 void __iomem *reg; 1220 u8 mshift; 1221 u8 mwidth; 1222 u8 nshift; 1223 u8 nwidth; 1224 u8 flags; 1225 void (*approximation)(struct clk_hw *hw, 1226 unsigned long rate, unsigned long *parent_rate, 1227 unsigned long *m, unsigned long *n); 1228 spinlock_t *lock; 1229}; 1230 1231#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) 1232 1233#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) 1234#define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1) 1235#define CLK_FRAC_DIVIDER_POWER_OF_TWO_PS BIT(2) 1236 1237struct clk *clk_register_fractional_divider(struct device *dev, 1238 const char *name, const char *parent_name, unsigned long flags, 1239 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, 1240 u8 clk_divider_flags, spinlock_t *lock); 1241struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, 1242 const char *name, const char *parent_name, unsigned long flags, 1243 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, 1244 u8 clk_divider_flags, spinlock_t *lock); 1245void clk_hw_unregister_fractional_divider(struct clk_hw *hw); 1246 1247/** 1248 * struct clk_multiplier - adjustable multiplier clock 1249 * 1250 * @hw: handle between common and hardware-specific interfaces 1251 * @reg: register containing the multiplier 1252 * @shift: shift to the multiplier bit field 1253 * @width: width of the multiplier bit field 1254 * @lock: register lock 1255 * 1256 * Clock with an adjustable multiplier affecting its output frequency. 1257 * Implements .recalc_rate, .set_rate and .round_rate 1258 * 1259 * @flags: 1260 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read 1261 * from the register, with 0 being a valid value effectively 1262 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is 1263 * set, then a null multiplier will be considered as a bypass, 1264 * leaving the parent rate unmodified. 1265 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be 1266 * rounded to the closest integer instead of the down one. 1267 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are 1268 * used for the multiplier register. Setting this flag makes the register 1269 * accesses big endian. 1270 */ 1271struct clk_multiplier { 1272 struct clk_hw hw; 1273 void __iomem *reg; 1274 u8 shift; 1275 u8 width; 1276 u8 flags; 1277 spinlock_t *lock; 1278}; 1279 1280#define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw) 1281 1282#define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) 1283#define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) 1284#define CLK_MULTIPLIER_BIG_ENDIAN BIT(2) 1285 1286extern const struct clk_ops clk_multiplier_ops; 1287 1288/*** 1289 * struct clk_composite - aggregate clock of mux, divider and gate clocks 1290 * 1291 * @hw: handle between common and hardware-specific interfaces 1292 * @mux_hw: handle between composite and hardware-specific mux clock 1293 * @rate_hw: handle between composite and hardware-specific rate clock 1294 * @gate_hw: handle between composite and hardware-specific gate clock 1295 * @mux_ops: clock ops for mux 1296 * @rate_ops: clock ops for rate 1297 * @gate_ops: clock ops for gate 1298 */ 1299struct clk_composite { 1300 struct clk_hw hw; 1301 struct clk_ops ops; 1302 1303 struct clk_hw *mux_hw; 1304 struct clk_hw *rate_hw; 1305 struct clk_hw *gate_hw; 1306 1307 const struct clk_ops *mux_ops; 1308 const struct clk_ops *rate_ops; 1309 const struct clk_ops *gate_ops; 1310}; 1311 1312#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) 1313 1314struct clk *clk_register_composite(struct device *dev, const char *name, 1315 const char * const *parent_names, int num_parents, 1316 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 1317 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 1318 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 1319 unsigned long flags); 1320struct clk *clk_register_composite_pdata(struct device *dev, const char *name, 1321 const struct clk_parent_data *parent_data, int num_parents, 1322 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 1323 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 1324 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 1325 unsigned long flags); 1326void clk_unregister_composite(struct clk *clk); 1327struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, 1328 const char * const *parent_names, int num_parents, 1329 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 1330 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 1331 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 1332 unsigned long flags); 1333struct clk_hw *clk_hw_register_composite_pdata(struct device *dev, 1334 const char *name, 1335 const struct clk_parent_data *parent_data, int num_parents, 1336 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 1337 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 1338 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 1339 unsigned long flags); 1340struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev, 1341 const char *name, const struct clk_parent_data *parent_data, 1342 int num_parents, 1343 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 1344 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 1345 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 1346 unsigned long flags); 1347void clk_hw_unregister_composite(struct clk_hw *hw); 1348 1349struct clk *clk_register(struct device *dev, struct clk_hw *hw); 1350struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); 1351 1352int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw); 1353int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw); 1354int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw); 1355 1356void clk_unregister(struct clk *clk); 1357 1358void clk_hw_unregister(struct clk_hw *hw); 1359 1360/* helper functions */ 1361const char *__clk_get_name(const struct clk *clk); 1362const char *clk_hw_get_name(const struct clk_hw *hw); 1363 1364/** 1365 * clk_hw_get_dev() - get device from an hardware clock. 1366 * @hw: the clk_hw pointer to get the struct device from 1367 * 1368 * This is a helper to get the struct device associated with a hardware 1369 * clock. Some clock controllers, such as the one registered with 1370 * CLK_OF_DECLARE(), may have not provided a device pointer while 1371 * registering the clock. 1372 * 1373 * Return: the struct device associated with the clock, or NULL if there 1374 * is none. 1375 */ 1376struct device *clk_hw_get_dev(const struct clk_hw *hw); 1377 1378/** 1379 * clk_hw_get_of_node() - get device_node from a hardware clock. 1380 * @hw: the clk_hw pointer to get the struct device_node from 1381 * 1382 * This is a helper to get the struct device_node associated with a 1383 * hardware clock. 1384 * 1385 * Return: the struct device_node associated with the clock, or NULL 1386 * if there is none. 1387 */ 1388struct device_node *clk_hw_get_of_node(const struct clk_hw *hw); 1389#ifdef CONFIG_COMMON_CLK 1390struct clk_hw *__clk_get_hw(struct clk *clk); 1391#else 1392static inline struct clk_hw *__clk_get_hw(struct clk *clk) 1393{ 1394 return (struct clk_hw *)clk; 1395} 1396#endif 1397 1398struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id); 1399struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw, 1400 const char *con_id); 1401 1402unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); 1403struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); 1404struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, 1405 unsigned int index); 1406int clk_hw_get_parent_index(struct clk_hw *hw); 1407int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent); 1408unsigned int __clk_get_enable_count(struct clk *clk); 1409unsigned long clk_hw_get_rate(const struct clk_hw *hw); 1410unsigned long clk_hw_get_flags(const struct clk_hw *hw); 1411#define clk_hw_can_set_rate_parent(hw) \ 1412 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT) 1413 1414bool clk_hw_is_prepared(const struct clk_hw *hw); 1415bool clk_hw_is_enabled(const struct clk_hw *hw); 1416bool __clk_is_enabled(struct clk *clk); 1417struct clk *__clk_lookup(const char *name); 1418int __clk_mux_determine_rate(struct clk_hw *hw, 1419 struct clk_rate_request *req); 1420int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req); 1421int __clk_mux_determine_rate_closest(struct clk_hw *hw, 1422 struct clk_rate_request *req); 1423int clk_mux_determine_rate_flags(struct clk_hw *hw, 1424 struct clk_rate_request *req, 1425 unsigned long flags); 1426int clk_hw_determine_rate_no_reparent(struct clk_hw *hw, 1427 struct clk_rate_request *req); 1428void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent); 1429void clk_hw_get_rate_range(struct clk_hw *hw, unsigned long *min_rate, 1430 unsigned long *max_rate); 1431void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, 1432 unsigned long max_rate); 1433 1434static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) 1435{ 1436 dst->clk = src->clk; 1437 dst->core = src->core; 1438} 1439 1440static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, 1441 unsigned long *prate, 1442 const struct clk_div_table *table, 1443 u8 width, unsigned long flags) 1444{ 1445 return divider_round_rate_parent(hw, clk_hw_get_parent(hw), 1446 rate, prate, table, width, flags); 1447} 1448 1449static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate, 1450 unsigned long *prate, 1451 const struct clk_div_table *table, 1452 u8 width, unsigned long flags, 1453 unsigned int val) 1454{ 1455 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw), 1456 rate, prate, table, width, flags, 1457 val); 1458} 1459 1460/* 1461 * FIXME clock api without lock protection 1462 */ 1463unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate); 1464 1465struct clk_onecell_data { 1466 struct clk **clks; 1467 unsigned int clk_num; 1468}; 1469 1470struct clk_hw_onecell_data { 1471 unsigned int num; 1472 struct clk_hw *hws[] __counted_by(num); 1473}; 1474 1475#define CLK_OF_DECLARE(name, compat, fn) \ 1476 static void __init __##name##_of_clk_init_declare(struct device_node *np) \ 1477 { \ 1478 fn(np); \ 1479 fwnode_dev_initialized(of_fwnode_handle(np), true); \ 1480 } \ 1481 OF_DECLARE_1(clk, name, compat, __##name##_of_clk_init_declare) 1482 1483/* 1484 * Use this macro when you have a driver that requires two initialization 1485 * routines, one at of_clk_init(), and one at platform device probe 1486 */ 1487#define CLK_OF_DECLARE_DRIVER(name, compat, fn) \ 1488 static void __init name##_of_clk_init_driver(struct device_node *np) \ 1489 { \ 1490 of_node_clear_flag(np, OF_POPULATED); \ 1491 fn(np); \ 1492 } \ 1493 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver) 1494 1495#define CLK_HW_INIT(_name, _parent, _ops, _flags) \ 1496 (&(struct clk_init_data) { \ 1497 .flags = _flags, \ 1498 .name = _name, \ 1499 .parent_names = (const char *[]) { _parent }, \ 1500 .num_parents = 1, \ 1501 .ops = _ops, \ 1502 }) 1503 1504#define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \ 1505 (&(struct clk_init_data) { \ 1506 .flags = _flags, \ 1507 .name = _name, \ 1508 .parent_hws = (const struct clk_hw*[]) { _parent }, \ 1509 .num_parents = 1, \ 1510 .ops = _ops, \ 1511 }) 1512 1513/* 1514 * This macro is intended for drivers to be able to share the otherwise 1515 * individual struct clk_hw[] compound literals created by the compiler 1516 * when using CLK_HW_INIT_HW. It does NOT support multiple parents. 1517 */ 1518#define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \ 1519 (&(struct clk_init_data) { \ 1520 .flags = _flags, \ 1521 .name = _name, \ 1522 .parent_hws = _parent, \ 1523 .num_parents = 1, \ 1524 .ops = _ops, \ 1525 }) 1526 1527#define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \ 1528 (&(struct clk_init_data) { \ 1529 .flags = _flags, \ 1530 .name = _name, \ 1531 .parent_data = (const struct clk_parent_data[]) { \ 1532 { .fw_name = _parent }, \ 1533 }, \ 1534 .num_parents = 1, \ 1535 .ops = _ops, \ 1536 }) 1537 1538#define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ 1539 (&(struct clk_init_data) { \ 1540 .flags = _flags, \ 1541 .name = _name, \ 1542 .parent_names = _parents, \ 1543 .num_parents = ARRAY_SIZE(_parents), \ 1544 .ops = _ops, \ 1545 }) 1546 1547#define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \ 1548 (&(struct clk_init_data) { \ 1549 .flags = _flags, \ 1550 .name = _name, \ 1551 .parent_hws = _parents, \ 1552 .num_parents = ARRAY_SIZE(_parents), \ 1553 .ops = _ops, \ 1554 }) 1555 1556#define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \ 1557 (&(struct clk_init_data) { \ 1558 .flags = _flags, \ 1559 .name = _name, \ 1560 .parent_data = _parents, \ 1561 .num_parents = ARRAY_SIZE(_parents), \ 1562 .ops = _ops, \ 1563 }) 1564 1565#define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \ 1566 (&(struct clk_init_data) { \ 1567 .flags = _flags, \ 1568 .name = _name, \ 1569 .parent_names = NULL, \ 1570 .num_parents = 0, \ 1571 .ops = _ops, \ 1572 }) 1573 1574#define CLK_FIXED_FACTOR(_struct, _name, _parent, \ 1575 _div, _mult, _flags) \ 1576 struct clk_fixed_factor _struct = { \ 1577 .div = _div, \ 1578 .mult = _mult, \ 1579 .hw.init = CLK_HW_INIT(_name, \ 1580 _parent, \ 1581 &clk_fixed_factor_ops, \ 1582 _flags), \ 1583 } 1584 1585#define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \ 1586 _div, _mult, _flags) \ 1587 struct clk_fixed_factor _struct = { \ 1588 .div = _div, \ 1589 .mult = _mult, \ 1590 .hw.init = CLK_HW_INIT_HW(_name, \ 1591 _parent, \ 1592 &clk_fixed_factor_ops, \ 1593 _flags), \ 1594 } 1595 1596/* 1597 * This macro allows the driver to reuse the _parent array for multiple 1598 * fixed factor clk declarations. 1599 */ 1600#define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \ 1601 _div, _mult, _flags) \ 1602 struct clk_fixed_factor _struct = { \ 1603 .div = _div, \ 1604 .mult = _mult, \ 1605 .hw.init = CLK_HW_INIT_HWS(_name, \ 1606 _parent, \ 1607 &clk_fixed_factor_ops, \ 1608 _flags), \ 1609 } 1610 1611#define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \ 1612 _div, _mult, _flags) \ 1613 struct clk_fixed_factor _struct = { \ 1614 .div = _div, \ 1615 .mult = _mult, \ 1616 .hw.init = CLK_HW_INIT_FW_NAME(_name, \ 1617 _parent, \ 1618 &clk_fixed_factor_ops, \ 1619 _flags), \ 1620 } 1621 1622#ifdef CONFIG_OF 1623int of_clk_add_provider(struct device_node *np, 1624 struct clk *(*clk_src_get)(struct of_phandle_args *args, 1625 void *data), 1626 void *data); 1627int of_clk_add_hw_provider(struct device_node *np, 1628 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 1629 void *data), 1630 void *data); 1631int devm_of_clk_add_hw_provider(struct device *dev, 1632 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 1633 void *data), 1634 void *data); 1635void of_clk_del_provider(struct device_node *np); 1636 1637struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, 1638 void *data); 1639struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, 1640 void *data); 1641struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); 1642struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec, 1643 void *data); 1644int of_clk_parent_fill(struct device_node *np, const char **parents, 1645 unsigned int size); 1646int of_clk_detect_critical(struct device_node *np, int index, 1647 unsigned long *flags); 1648 1649#else /* !CONFIG_OF */ 1650 1651static inline int of_clk_add_provider(struct device_node *np, 1652 struct clk *(*clk_src_get)(struct of_phandle_args *args, 1653 void *data), 1654 void *data) 1655{ 1656 return 0; 1657} 1658static inline int of_clk_add_hw_provider(struct device_node *np, 1659 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 1660 void *data), 1661 void *data) 1662{ 1663 return 0; 1664} 1665static inline int devm_of_clk_add_hw_provider(struct device *dev, 1666 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 1667 void *data), 1668 void *data) 1669{ 1670 return 0; 1671} 1672static inline void of_clk_del_provider(struct device_node *np) {} 1673 1674static inline struct clk *of_clk_src_simple_get( 1675 struct of_phandle_args *clkspec, void *data) 1676{ 1677 return ERR_PTR(-ENOENT); 1678} 1679static inline struct clk_hw * 1680of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data) 1681{ 1682 return ERR_PTR(-ENOENT); 1683} 1684static inline struct clk *of_clk_src_onecell_get( 1685 struct of_phandle_args *clkspec, void *data) 1686{ 1687 return ERR_PTR(-ENOENT); 1688} 1689static inline struct clk_hw * 1690of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data) 1691{ 1692 return ERR_PTR(-ENOENT); 1693} 1694static inline int of_clk_parent_fill(struct device_node *np, 1695 const char **parents, unsigned int size) 1696{ 1697 return 0; 1698} 1699static inline int of_clk_detect_critical(struct device_node *np, int index, 1700 unsigned long *flags) 1701{ 1702 return 0; 1703} 1704#endif /* CONFIG_OF */ 1705 1706void clk_gate_restore_context(struct clk_hw *hw); 1707 1708#endif /* CLK_PROVIDER_H */
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