aer.h

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * Copyright (C) 2006 Intel Corp.
 4 *     Tom Long Nguyen (tom.l.nguyen@intel.com)
 5 *     Zhang Yanmin (yanmin.zhang@intel.com)
 6 */
 7
 8#ifndef _AER_H_
 9#define _AER_H_
10
11#include <linux/errno.h>
12#include <linux/types.h>
13
14#define AER_NONFATAL			0
15#define AER_FATAL			1
16#define AER_CORRECTABLE			2
17#define DPC_FATAL			3
18
19/*
20 * AER and DPC capabilities TLP Logging register sizes (PCIe r6.2, sec 7.8.4
21 * & 7.9.14).
22 */
23#define PCIE_STD_NUM_TLP_HEADERLOG     4
24#define PCIE_STD_MAX_TLP_PREFIXLOG     4
25#define PCIE_STD_MAX_TLP_HEADERLOG	(PCIE_STD_NUM_TLP_HEADERLOG + 10)
26
27struct pci_dev;
28
29struct pcie_tlp_log {
30	union {
31		u32 dw[PCIE_STD_MAX_TLP_HEADERLOG];
32		struct {
33			u32 _do_not_use[PCIE_STD_NUM_TLP_HEADERLOG];
34			u32 prefix[PCIE_STD_MAX_TLP_PREFIXLOG];
35		};
36	};
37	u8 header_len;		/* Length of the Logged TLP Header in DWORDs */
38	bool flit;		/* TLP was logged when in Flit mode */
39};
40
41struct aer_capability_regs {
42	u32 header;
43	u32 uncor_status;
44	u32 uncor_mask;
45	u32 uncor_severity;
46	u32 cor_status;
47	u32 cor_mask;
48	u32 cap_control;
49	struct pcie_tlp_log header_log;
50	u32 root_command;
51	u32 root_status;
52	u16 cor_err_source;
53	u16 uncor_err_source;
54};
55
56#if defined(CONFIG_PCIEAER)
57int pci_aer_clear_nonfatal_status(struct pci_dev *dev);
58int pcie_aer_is_native(struct pci_dev *dev);
59#else
60static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev)
61{
62	return -EINVAL;
63}
64static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; }
65#endif
66
67void pci_print_aer(struct pci_dev *dev, int aer_severity,
68		    struct aer_capability_regs *aer);
69int cper_severity_to_aer(int cper_severity);
70void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
71		       int severity, struct aer_capability_regs *aer_regs);
72#endif //_AER_H_
73