adi-axi-common.h

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * Analog Devices AXI common registers & definitions
 4 *
 5 * Copyright 2019 Analog Devices Inc.
 6 *
 7 * https://wiki.analog.com/resources/fpga/docs/axi_ip
 8 * https://wiki.analog.com/resources/fpga/docs/hdl/regmap
 9 */
10
11#include <linux/types.h>
12
13#ifndef ADI_AXI_COMMON_H_
14#define ADI_AXI_COMMON_H_
15
16#define ADI_AXI_REG_VERSION			0x0000
17#define ADI_AXI_REG_FPGA_INFO			0x001C
18
19#define ADI_AXI_PCORE_VER(major, minor, patch)	\
20	(((major) << 16) | ((minor) << 8) | (patch))
21
22#define ADI_AXI_PCORE_VER_MAJOR(version)	(((version) >> 16) & 0xff)
23#define ADI_AXI_PCORE_VER_MINOR(version)	(((version) >> 8) & 0xff)
24#define ADI_AXI_PCORE_VER_PATCH(version)	((version) & 0xff)
25
26/**
27 * adi_axi_pcore_ver_gteq() - check if a version is satisfied
28 * @version: the full version read from the hardware
29 * @major: the major version to compare against
30 * @minor: the minor version to compare against
31 *
32 * ADI AXI IP Cores use semantic versioning, so this can be used to check for
33 * feature availability.
34 *
35 * Return: true if the version is greater than or equal to the specified
36 *         major and minor version, false otherwise.
37 */
38static inline bool adi_axi_pcore_ver_gteq(u32 version, u32 major, u32 minor)
39{
40	return ADI_AXI_PCORE_VER_MAJOR(version) > (major) ||
41	       (ADI_AXI_PCORE_VER_MAJOR(version) == (major) &&
42		ADI_AXI_PCORE_VER_MINOR(version) >= (minor));
43}
44
45#define ADI_AXI_INFO_FPGA_TECH(info)            (((info) >> 24) & 0xff)
46#define ADI_AXI_INFO_FPGA_FAMILY(info)          (((info) >> 16) & 0xff)
47#define ADI_AXI_INFO_FPGA_SPEED_GRADE(info)     (((info) >> 8) & 0xff)
48
49enum adi_axi_fpga_technology {
50	ADI_AXI_FPGA_TECH_UNKNOWN = 0,
51	ADI_AXI_FPGA_TECH_SERIES7,
52	ADI_AXI_FPGA_TECH_ULTRASCALE,
53	ADI_AXI_FPGA_TECH_ULTRASCALE_PLUS,
54};
55
56enum adi_axi_fpga_family {
57	ADI_AXI_FPGA_FAMILY_UNKNOWN = 0,
58	ADI_AXI_FPGA_FAMILY_ARTIX,
59	ADI_AXI_FPGA_FAMILY_KINTEX,
60	ADI_AXI_FPGA_FAMILY_VIRTEX,
61	ADI_AXI_FPGA_FAMILY_ZYNQ,
62};
63
64enum adi_axi_fpga_speed_grade {
65	ADI_AXI_FPGA_SPEED_UNKNOWN      = 0,
66	ADI_AXI_FPGA_SPEED_1    = 10,
67	ADI_AXI_FPGA_SPEED_1L   = 11,
68	ADI_AXI_FPGA_SPEED_1H   = 12,
69	ADI_AXI_FPGA_SPEED_1HV  = 13,
70	ADI_AXI_FPGA_SPEED_1LV  = 14,
71	ADI_AXI_FPGA_SPEED_2    = 20,
72	ADI_AXI_FPGA_SPEED_2L   = 21,
73	ADI_AXI_FPGA_SPEED_2LV  = 22,
74	ADI_AXI_FPGA_SPEED_3    = 30,
75};
76
77#endif /* ADI_AXI_COMMON_H_ */