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thead,th1520-reset.h

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linux-6.19.14/include/dt-bindings/reset/thead,th1520-reset.h C 
  1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  2/*
  3 * Copyright (c) 2024 Samsung Electronics Co., Ltd.
  4 * Author: Michal Wilczynski <m.wilczynski@samsung.com>
  5 */
  6
  7#ifndef _DT_BINDINGS_TH1520_RESET_H
  8#define _DT_BINDINGS_TH1520_RESET_H
  9
 10/* AO Subsystem */
 11#define TH1520_RESET_ID_SYSTEM		0
 12#define TH1520_RESET_ID_RTC_APB		1
 13#define TH1520_RESET_ID_RTC_REF		2
 14#define TH1520_RESET_ID_AOGPIO_DB	3
 15#define TH1520_RESET_ID_AOGPIO_APB	4
 16#define TH1520_RESET_ID_AOI2C_APB	5
 17#define TH1520_RESET_ID_PVT_APB		6
 18#define TH1520_RESET_ID_E902_CORE	7
 19#define TH1520_RESET_ID_E902_HAD	8
 20#define TH1520_RESET_ID_AOTIMER_APB	9
 21#define TH1520_RESET_ID_AOTIMER_CORE	10
 22#define TH1520_RESET_ID_AOWDT_APB	11
 23#define TH1520_RESET_ID_APSYS		12
 24#define TH1520_RESET_ID_NPUSYS		13
 25#define TH1520_RESET_ID_DDRSYS		14
 26#define TH1520_RESET_ID_AXI_AP2CP	15
 27#define TH1520_RESET_ID_AXI_CP2AP	16
 28#define TH1520_RESET_ID_AXI_CP2SRAM	17
 29#define TH1520_RESET_ID_AUDSYS_CORE	18
 30#define TH1520_RESET_ID_AUDSYS_IOPMP	19
 31#define TH1520_RESET_ID_AUDSYS		20
 32#define TH1520_RESET_ID_DSP0		21
 33#define TH1520_RESET_ID_DSP1		22
 34#define TH1520_RESET_ID_GPU_MODULE	23
 35#define TH1520_RESET_ID_VDEC		24
 36#define TH1520_RESET_ID_VENC		25
 37#define TH1520_RESET_ID_ADC_APB		26
 38#define TH1520_RESET_ID_AUDGPIO_DB	27
 39#define TH1520_RESET_ID_AUDGPIO_APB	28
 40#define TH1520_RESET_ID_AOUART_IF	29
 41#define TH1520_RESET_ID_AOUART_APB	30
 42#define TH1520_RESET_ID_SRAM_AXI_P0	31
 43#define TH1520_RESET_ID_SRAM_AXI_P1	32
 44#define TH1520_RESET_ID_SRAM_AXI_P2	33
 45#define TH1520_RESET_ID_SRAM_AXI_P3	34
 46#define TH1520_RESET_ID_SRAM_AXI_P4	35
 47#define TH1520_RESET_ID_SRAM_AXI_CORE	36
 48#define TH1520_RESET_ID_SE		37
 49
 50/* AP Subsystem */
 51#define TH1520_RESET_ID_BROM			0
 52#define TH1520_RESET_ID_C910_TOP		1
 53#define TH1520_RESET_ID_NPU			2
 54#define TH1520_RESET_ID_WDT0			3
 55#define TH1520_RESET_ID_WDT1			4
 56#define TH1520_RESET_ID_C910_C0			5
 57#define TH1520_RESET_ID_C910_C1			6
 58#define TH1520_RESET_ID_C910_C2			7
 59#define TH1520_RESET_ID_C910_C3			8
 60#define TH1520_RESET_ID_CHIP_DBG_CORE		9
 61#define TH1520_RESET_ID_CHIP_DBG_AXI		10
 62#define TH1520_RESET_ID_AXI4_CPUSYS2_AXI	11
 63#define TH1520_RESET_ID_AXI4_CPUSYS2_APB	12
 64#define TH1520_RESET_ID_X2H_CPUSYS		13
 65#define TH1520_RESET_ID_AHB2_CPUSYS		14
 66#define TH1520_RESET_ID_APB3_CPUSYS		15
 67#define TH1520_RESET_ID_MBOX0_APB		16
 68#define TH1520_RESET_ID_MBOX1_APB		17
 69#define TH1520_RESET_ID_MBOX2_APB		18
 70#define TH1520_RESET_ID_MBOX3_APB		19
 71#define TH1520_RESET_ID_TIMER0_APB		20
 72#define TH1520_RESET_ID_TIMER0_CORE		21
 73#define TH1520_RESET_ID_TIMER1_APB		22
 74#define TH1520_RESET_ID_TIMER1_CORE		23
 75#define TH1520_RESET_ID_PERISYS_AHB		24
 76#define TH1520_RESET_ID_PERISYS_APB1		25
 77#define TH1520_RESET_ID_PERISYS_APB2		26
 78#define TH1520_RESET_ID_GMAC0_APB		27
 79#define TH1520_RESET_ID_GMAC0_AHB		28
 80#define TH1520_RESET_ID_GMAC0_CLKGEN		29
 81#define TH1520_RESET_ID_GMAC0_AXI		30
 82#define TH1520_RESET_ID_UART0_APB		31
 83#define TH1520_RESET_ID_UART0_IF		32
 84#define TH1520_RESET_ID_UART1_APB		33
 85#define TH1520_RESET_ID_UART1_IF		34
 86#define TH1520_RESET_ID_UART2_APB		35
 87#define TH1520_RESET_ID_UART2_IF		36
 88#define TH1520_RESET_ID_UART3_APB		37
 89#define TH1520_RESET_ID_UART3_IF		38
 90#define TH1520_RESET_ID_UART4_APB		39
 91#define TH1520_RESET_ID_UART4_IF		40
 92#define TH1520_RESET_ID_UART5_APB		41
 93#define TH1520_RESET_ID_UART5_IF		42
 94#define TH1520_RESET_ID_QSPI0_IF		43
 95#define TH1520_RESET_ID_QSPI0_APB		44
 96#define TH1520_RESET_ID_QSPI1_IF		45
 97#define TH1520_RESET_ID_QSPI1_APB		46
 98#define TH1520_RESET_ID_SPI_IF			47
 99#define TH1520_RESET_ID_SPI_APB			48
100#define TH1520_RESET_ID_I2C0_APB		49
101#define TH1520_RESET_ID_I2C0_CORE		50
102#define TH1520_RESET_ID_I2C1_APB		51
103#define TH1520_RESET_ID_I2C1_CORE		52
104#define TH1520_RESET_ID_I2C2_APB		53
105#define TH1520_RESET_ID_I2C2_CORE		54
106#define TH1520_RESET_ID_I2C3_APB		55
107#define TH1520_RESET_ID_I2C3_CORE		56
108#define TH1520_RESET_ID_I2C4_APB		57
109#define TH1520_RESET_ID_I2C4_CORE		58
110#define TH1520_RESET_ID_I2C5_APB		59
111#define TH1520_RESET_ID_I2C5_CORE		60
112#define TH1520_RESET_ID_GPIO0_DB		61
113#define TH1520_RESET_ID_GPIO0_APB		62
114#define TH1520_RESET_ID_GPIO1_DB		63
115#define TH1520_RESET_ID_GPIO1_APB		64
116#define TH1520_RESET_ID_GPIO2_DB		65
117#define TH1520_RESET_ID_GPIO2_APB		66
118#define TH1520_RESET_ID_PWM_COUNTER		67
119#define TH1520_RESET_ID_PWM_APB			68
120#define TH1520_RESET_ID_PADCTRL0_APB		69
121#define TH1520_RESET_ID_CPU2PERI_X2H		70
122#define TH1520_RESET_ID_CPU2AON_X2H		71
123#define TH1520_RESET_ID_AON2CPU_A2X		72
124#define TH1520_RESET_ID_NPUSYS_AXI		73
125#define TH1520_RESET_ID_NPUSYS_AXI_APB		74
126#define TH1520_RESET_ID_CPU2VP_X2P		75
127#define TH1520_RESET_ID_CPU2VI_X2H		76
128#define TH1520_RESET_ID_BMU_AXI			77
129#define TH1520_RESET_ID_BMU_APB			78
130#define TH1520_RESET_ID_DMAC_CPUSYS_AXI		79
131#define TH1520_RESET_ID_DMAC_CPUSYS_AHB		80
132#define TH1520_RESET_ID_SPINLOCK		81
133#define TH1520_RESET_ID_CFG2TEE			82
134#define TH1520_RESET_ID_DSMART			83
135#define TH1520_RESET_ID_GPIO3_DB		84
136#define TH1520_RESET_ID_GPIO3_APB		85
137#define TH1520_RESET_ID_PERI_I2S		86
138#define TH1520_RESET_ID_PERI_APB3		87
139#define TH1520_RESET_ID_PERI2PERI1_APB		88
140#define TH1520_RESET_ID_VPSYS_APB		89
141#define TH1520_RESET_ID_PERISYS_APB4		90
142#define TH1520_RESET_ID_GMAC1_APB		91
143#define TH1520_RESET_ID_GMAC1_AHB		92
144#define TH1520_RESET_ID_GMAC1_CLKGEN		93
145#define TH1520_RESET_ID_GMAC1_AXI		94
146#define TH1520_RESET_ID_GMAC_AXI		95
147#define TH1520_RESET_ID_GMAC_AXI_APB		96
148#define TH1520_RESET_ID_PADCTRL1_APB		97
149#define TH1520_RESET_ID_VOSYS_AXI		98
150#define TH1520_RESET_ID_VOSYS_AXI_APB		99
151#define TH1520_RESET_ID_VOSYS_AXI_X2X		100
152#define TH1520_RESET_ID_MISC2VP_X2X		101
153#define TH1520_RESET_ID_DSPSYS			102
154#define TH1520_RESET_ID_VISYS			103
155#define TH1520_RESET_ID_VOSYS			104
156#define TH1520_RESET_ID_VPSYS			105
157
158/* DSP Subsystem */
159#define TH1520_RESET_ID_X2X_DSP1	0
160#define TH1520_RESET_ID_X2X_DSP0	1
161#define TH1520_RESET_ID_X2X_SLAVE_DSP1	2
162#define TH1520_RESET_ID_X2X_SLAVE_DSP0	3
163#define TH1520_RESET_ID_DSP0_CORE	4
164#define TH1520_RESET_ID_DSP0_DEBUG	5
165#define TH1520_RESET_ID_DSP0_APB	6
166#define TH1520_RESET_ID_DSP1_CORE	7
167#define TH1520_RESET_ID_DSP1_DEBUG	8
168#define TH1520_RESET_ID_DSP1_APB	9
169#define TH1520_RESET_ID_DSPSYS_APB	10
170#define TH1520_RESET_ID_AXI4_DSPSYS_SLV	11
171#define TH1520_RESET_ID_AXI4_DSPSYS	12
172#define TH1520_RESET_ID_AXI4_DSP_RS	13
173
174/* MISC Subsystem */
175#define TH1520_RESET_ID_EMMC_SDIO_CLKGEN	0
176#define TH1520_RESET_ID_EMMC			1
177#define TH1520_RESET_ID_MISCSYS_AXI		2
178#define TH1520_RESET_ID_MISCSYS_AXI_APB		3
179#define TH1520_RESET_ID_SDIO0			4
180#define TH1520_RESET_ID_SDIO1			5
181#define TH1520_RESET_ID_USB3_APB		6
182#define TH1520_RESET_ID_USB3_PHY		7
183#define TH1520_RESET_ID_USB3_VCC		8
184
185/* VI Subsystem */
186#define TH1520_RESET_ID_ISP0		0
187#define TH1520_RESET_ID_ISP1		1
188#define TH1520_RESET_ID_CSI0_APB	2
189#define TH1520_RESET_ID_CSI1_APB	3
190#define TH1520_RESET_ID_CSI2_APB	4
191#define TH1520_RESET_ID_MIPI_FIFO	5
192#define TH1520_RESET_ID_ISP_VENC_APB	6
193#define TH1520_RESET_ID_VIPRE_APB	7
194#define TH1520_RESET_ID_VIPRE_AXI	8
195#define TH1520_RESET_ID_DW200_APB	9
196#define TH1520_RESET_ID_VISYS3_AXI	10
197#define TH1520_RESET_ID_VISYS2_AXI	11
198#define TH1520_RESET_ID_VISYS1_AXI	12
199#define TH1520_RESET_ID_VISYS_AXI	13
200#define TH1520_RESET_ID_VISYS_APB	14
201#define TH1520_RESET_ID_ISP_VENC_AXI	15
202
203/* VO Subsystem */
204#define TH1520_RESET_ID_GPU		0
205#define TH1520_RESET_ID_GPU_CLKGEN	1
206#define TH1520_RESET_ID_DPU_AHB		5
207#define TH1520_RESET_ID_DPU_AXI		6
208#define TH1520_RESET_ID_DPU_CORE	7
209#define TH1520_RESET_ID_DSI0_APB	8
210#define TH1520_RESET_ID_DSI1_APB	9
211#define TH1520_RESET_ID_HDMI		10
212#define TH1520_RESET_ID_HDMI_APB	11
213#define TH1520_RESET_ID_VOAXI		12
214#define TH1520_RESET_ID_VOAXI_APB	13
215#define TH1520_RESET_ID_X2H_DPU_AXI	14
216#define TH1520_RESET_ID_X2H_DPU_AHB	15
217#define TH1520_RESET_ID_X2H_DPU1_AXI	16
218#define TH1520_RESET_ID_X2H_DPU1_AHB	17
219
220/* VP Subsystem */
221#define TH1520_RESET_ID_VPSYS_AXI_APB	0
222#define TH1520_RESET_ID_VPSYS_AXI	1
223#define TH1520_RESET_ID_FCE_APB		2
224#define TH1520_RESET_ID_FCE_CORE	3
225#define TH1520_RESET_ID_FCE_X2X_MASTER	4
226#define TH1520_RESET_ID_FCE_X2X_SLAVE	5
227#define TH1520_RESET_ID_G2D_APB		6
228#define TH1520_RESET_ID_G2D_ACLK	7
229#define TH1520_RESET_ID_G2D_CORE	8
230#define TH1520_RESET_ID_VDEC_APB	9
231#define TH1520_RESET_ID_VDEC_ACLK	10
232#define TH1520_RESET_ID_VDEC_CORE	11
233#define TH1520_RESET_ID_VENC_APB	12
234#define TH1520_RESET_ID_VENC_CORE	13
235
236#endif /* _DT_BINDINGS_TH1520_RESET_H */
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