st,stm32mp21-rcc.h

  1/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
  2/*
  3 * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
  4 * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
  5 */
  6
  7#ifndef _DT_BINDINGS_STM32MP21_RESET_H_
  8#define _DT_BINDINGS_STM32MP21_RESET_H_
  9
 10#define TIM1_R		0
 11#define TIM2_R		1
 12#define TIM3_R		2
 13#define TIM4_R		3
 14#define TIM5_R		4
 15#define TIM6_R		5
 16#define TIM7_R		6
 17#define TIM8_R		7
 18#define TIM10_R		8
 19#define TIM11_R		9
 20#define TIM12_R		10
 21#define TIM13_R		11
 22#define TIM14_R		12
 23#define TIM15_R		13
 24#define TIM16_R		14
 25#define TIM17_R		15
 26#define LPTIM1_R	16
 27#define LPTIM2_R	17
 28#define LPTIM3_R	18
 29#define LPTIM4_R	19
 30#define LPTIM5_R	20
 31#define SPI1_R		21
 32#define SPI2_R		22
 33#define SPI3_R		23
 34#define SPI4_R		24
 35#define SPI5_R		25
 36#define SPI6_R		26
 37#define SPDIFRX_R	27
 38#define USART1_R	28
 39#define USART2_R	29
 40#define USART3_R	30
 41#define UART4_R		31
 42#define UART5_R		32
 43#define USART6_R	33
 44#define UART7_R		34
 45#define LPUART1_R	35
 46#define I2C1_R		36
 47#define I2C2_R		37
 48#define I2C3_R		38
 49#define SAI1_R		39
 50#define SAI2_R		40
 51#define SAI3_R		41
 52#define SAI4_R		42
 53#define MDF1_R		43
 54#define FDCAN_R		44
 55#define HDP_R		45
 56#define ADC1_R		46
 57#define ADC2_R		47
 58#define ETH1_R		48
 59#define ETH2_R		49
 60#define USBH_R		50
 61#define USB2PHY1_R	51
 62#define USB2PHY2_R	52
 63#define SDMMC1_R	53
 64#define SDMMC1DLL_R	54
 65#define SDMMC2_R	55
 66#define SDMMC2DLL_R	56
 67#define SDMMC3_R	57
 68#define SDMMC3DLL_R	58
 69#define LTDC_R		59
 70#define CSI_R		60
 71#define DCMIPP_R	61
 72#define DCMIPSSI_R	62
 73#define WWDG1_R		63
 74#define VREF_R		64
 75#define DTS_R		65
 76#define CRC_R		66
 77#define SERC_R		67
 78#define I3C1_R		68
 79#define I3C2_R		69
 80#define I3C3_R		70
 81#define IWDG2_KER_R	71
 82#define IWDG4_KER_R	72
 83#define RNG1_R		73
 84#define RNG2_R		74
 85#define PKA_R		75
 86#define SAES_R		76
 87#define HASH1_R		77
 88#define HASH2_R		78
 89#define CRYP1_R		79
 90#define CRYP2_R		80
 91#define OSPI1_R		81
 92#define OSPI1DLL_R	82
 93#define OTG_R		83
 94#define FMC_R		84
 95#define DBG_R		85
 96#define GPIOA_R		86
 97#define GPIOB_R		87
 98#define GPIOC_R		88
 99#define GPIOD_R		89
100#define GPIOE_R		90
101#define GPIOF_R		91
102#define GPIOG_R		92
103#define GPIOH_R		93
104#define GPIOI_R		94
105#define GPIOZ_R		95
106#define HPDMA1_R	96
107#define HPDMA2_R	97
108#define HPDMA3_R	98
109#define IPCC1_R		99
110#define C2_HOLDBOOT_R	100
111#define C1_HOLDBOOT_R	101
112#define C1_R		102
113#define C1P1POR_R	103
114#define C1P1_R		104
115#define C2_R		105
116#define SYS_R		106
117#define VSW_R		107
118#define C1MS_R		108
119#define DDRCP_R		109
120#define DDRCAPB_R	110
121#define DDRPHYCAPB_R	111
122#define DDRCFG_R	112
123#define DDR_R		113
124#define DDRPERFM_R	114
125#define IWDG1_SYS_R	116
126#define IWDG2_SYS_R	117
127#define IWDG3_SYS_R	118
128#define IWDG4_SYS_R	119
129
130#define RST_SCMI_C1_R		0
131#define RST_SCMI_C2_R		1
132#define RST_SCMI_C1_HOLDBOOT_R	2
133#define RST_SCMI_C2_HOLDBOOT_R	3
134#define RST_SCMI_FMC		4
135#define RST_SCMI_OSPI1		5
136#define RST_SCMI_OSPI1DLL	6
137
138#endif /* _DT_BINDINGS_STM32MP21_RESET_H_ */