rockchip,rk3562-cru.h

  1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  2/*
  3 * Copyright (c) 2024-2025 Rockchip Electronics Co. Ltd.
  4 *
  5 * Author: Elaine Zhang <zhangqing@rock-chips.com>
  6 */
  7
  8#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3562_H
  9#define _DT_BINDINGS_RESET_ROCKCHIP_RK3562_H
 10
 11/********Name=SOFTRST_CON01,Offset=0x404********/
 12#define SRST_A_TOP_BIU			0
 13#define SRST_A_TOP_VIO_BIU		1
 14#define SRST_REF_PVTPLL_LOGIC		2
 15/********Name=SOFTRST_CON03,Offset=0x40C********/
 16#define SRST_NCOREPORESET0		3
 17#define SRST_NCOREPORESET1		4
 18#define SRST_NCOREPORESET2		5
 19#define SRST_NCOREPORESET3		6
 20#define SRST_NCORESET0			7
 21#define SRST_NCORESET1			8
 22#define SRST_NCORESET2			9
 23#define SRST_NCORESET3			10
 24#define SRST_NL2RESET			11
 25/********Name=SOFTRST_CON04,Offset=0x410********/
 26#define SRST_DAP			12
 27#define SRST_P_DBG_DAPLITE		13
 28#define SRST_REF_PVTPLL_CORE		14
 29/********Name=SOFTRST_CON05,Offset=0x414********/
 30#define SRST_A_CORE_BIU			15
 31#define SRST_P_CORE_BIU			16
 32#define SRST_H_CORE_BIU			17
 33/********Name=SOFTRST_CON06,Offset=0x418********/
 34#define SRST_A_NPU_BIU			18
 35#define SRST_H_NPU_BIU			19
 36#define SRST_A_RKNN			20
 37#define SRST_H_RKNN			21
 38#define SRST_REF_PVTPLL_NPU		22
 39/********Name=SOFTRST_CON08,Offset=0x420********/
 40#define SRST_A_GPU_BIU			23
 41#define SRST_GPU			24
 42#define SRST_REF_PVTPLL_GPU		25
 43#define SRST_GPU_BRG_BIU		26
 44/********Name=SOFTRST_CON09,Offset=0x424********/
 45#define SRST_RKVENC_CORE		27
 46#define SRST_A_VEPU_BIU			28
 47#define SRST_H_VEPU_BIU			29
 48#define SRST_A_RKVENC			30
 49#define SRST_H_RKVENC			31
 50/********Name=SOFTRST_CON10,Offset=0x428********/
 51#define SRST_RKVDEC_HEVC_CA		32
 52#define SRST_A_VDPU_BIU			33
 53#define SRST_H_VDPU_BIU			34
 54#define SRST_A_RKVDEC			35
 55#define SRST_H_RKVDEC			36
 56/********Name=SOFTRST_CON11,Offset=0x42C********/
 57#define SRST_A_VI_BIU			37
 58#define SRST_H_VI_BIU			38
 59#define SRST_P_VI_BIU			39
 60#define SRST_ISP			40
 61#define SRST_A_VICAP			41
 62#define SRST_H_VICAP			42
 63#define SRST_D_VICAP			43
 64#define SRST_I0_VICAP			44
 65#define SRST_I1_VICAP			45
 66#define SRST_I2_VICAP			46
 67#define SRST_I3_VICAP			47
 68/********Name=SOFTRST_CON12,Offset=0x430********/
 69#define SRST_P_CSIHOST0			48
 70#define SRST_P_CSIHOST1			49
 71#define SRST_P_CSIHOST2			50
 72#define SRST_P_CSIHOST3			51
 73#define SRST_P_CSIPHY0			52
 74#define SRST_P_CSIPHY1			53
 75/********Name=SOFTRST_CON13,Offset=0x434********/
 76#define SRST_A_VO_BIU			54
 77#define SRST_H_VO_BIU			55
 78#define SRST_A_VOP			56
 79#define SRST_H_VOP			57
 80#define SRST_D_VOP			58
 81#define SRST_D_VOP1			59
 82/********Name=SOFTRST_CON14,Offset=0x438********/
 83#define SRST_A_RGA_BIU			60
 84#define SRST_H_RGA_BIU			61
 85#define SRST_A_RGA			62
 86#define SRST_H_RGA			63
 87#define SRST_RGA_CORE			64
 88#define SRST_A_JDEC			65
 89#define SRST_H_JDEC			66
 90/********Name=SOFTRST_CON15,Offset=0x43C********/
 91#define SRST_B_EBK_BIU			67
 92#define SRST_P_EBK_BIU			68
 93#define SRST_AHB2AXI_EBC		69
 94#define SRST_H_EBC			70
 95#define SRST_D_EBC			71
 96#define SRST_H_EINK			72
 97#define SRST_P_EINK			73
 98/********Name=SOFTRST_CON16,Offset=0x440********/
 99#define SRST_P_PHP_BIU			74
100#define SRST_A_PHP_BIU			75
101#define SRST_P_PCIE20			76
102#define SRST_PCIE20_POWERUP		77
103#define SRST_USB3OTG			78
104/********Name=SOFTRST_CON17,Offset=0x444********/
105#define SRST_PIPEPHY			79
106/********Name=SOFTRST_CON18,Offset=0x448********/
107#define SRST_A_BUS_BIU			80
108#define SRST_H_BUS_BIU			81
109#define SRST_P_BUS_BIU			82
110/********Name=SOFTRST_CON19,Offset=0x44C********/
111#define SRST_P_I2C1			83
112#define SRST_P_I2C2			84
113#define SRST_P_I2C3			85
114#define SRST_P_I2C4			86
115#define SRST_P_I2C5			87
116#define SRST_I2C1			88
117#define SRST_I2C2			89
118#define SRST_I2C3			90
119#define SRST_I2C4			91
120#define SRST_I2C5			92
121/********Name=SOFTRST_CON20,Offset=0x450********/
122#define SRST_BUS_GPIO3			93
123#define SRST_BUS_GPIO4			94
124/********Name=SOFTRST_CON21,Offset=0x454********/
125#define SRST_P_TIMER			95
126#define SRST_TIMER0			96
127#define SRST_TIMER1			97
128#define SRST_TIMER2			98
129#define SRST_TIMER3			99
130#define SRST_TIMER4			100
131#define SRST_TIMER5			101
132#define SRST_P_STIMER			102
133#define SRST_STIMER0			103
134#define SRST_STIMER1			104
135/********Name=SOFTRST_CON22,Offset=0x458********/
136#define SRST_P_WDTNS			105
137#define SRST_WDTNS			106
138#define SRST_P_GRF			107
139#define SRST_P_SGRF			108
140#define SRST_P_MAILBOX			109
141#define SRST_P_INTC			110
142#define SRST_A_BUS_GIC400		111
143#define SRST_A_BUS_GIC400_DEBUG		112
144/********Name=SOFTRST_CON23,Offset=0x45C********/
145#define SRST_A_BUS_SPINLOCK		113
146#define SRST_A_DCF			114
147#define SRST_P_DCF			115
148#define SRST_F_BUS_CM0_CORE		116
149#define SRST_T_BUS_CM0_JTAG		117
150#define SRST_H_ICACHE			118
151#define SRST_H_DCACHE			119
152/********Name=SOFTRST_CON24,Offset=0x460********/
153#define SRST_P_TSADC			120
154#define SRST_TSADC			121
155#define SRST_TSADCPHY			122
156#define SRST_P_DFT2APB			123
157/********Name=SOFTRST_CON25,Offset=0x464********/
158#define SRST_A_GMAC			124
159#define SRST_P_APB2ASB_VCCIO156		125
160#define SRST_P_DSIPHY			126
161#define SRST_P_DSITX			127
162#define SRST_P_CPU_EMA_DET		128
163#define SRST_P_HASH			129
164#define SRST_P_TOPCRU			130
165/********Name=SOFTRST_CON26,Offset=0x468********/
166#define SRST_P_ASB2APB_VCCIO156		131
167#define SRST_P_IOC_VCCIO156		132
168#define SRST_P_GPIO3_VCCIO156		133
169#define SRST_P_GPIO4_VCCIO156		134
170#define SRST_P_SARADC_VCCIO156		135
171#define SRST_SARADC_VCCIO156		136
172#define SRST_SARADC_VCCIO156_PHY	137
173/********Name=SOFTRST_CON27,Offset=0x46c********/
174#define SRST_A_MAC100			138
175
176/********Name=PMU0SOFTRST_CON00,Offset=0x10200********/
177#define SRST_P_PMU0_CRU			139
178#define SRST_P_PMU0_PMU			140
179#define SRST_PMU0_PMU			141
180#define SRST_P_PMU0_HP_TIMER		142
181#define SRST_PMU0_HP_TIMER		143
182#define SRST_PMU0_32K_HP_TIMER		144
183#define SRST_P_PMU0_PVTM		145
184#define SRST_PMU0_PVTM			146
185#define SRST_P_IOC_PMUIO		147
186#define SRST_P_PMU0_GPIO0		148
187#define SRST_PMU0_GPIO0			149
188#define SRST_P_PMU0_GRF			150
189#define SRST_P_PMU0_SGRF		151
190/********Name=PMU0SOFTRST_CON01,Offset=0x10204********/
191#define SRST_DDR_FAIL_SAFE		152
192#define SRST_P_PMU0_SCRKEYGEN		153
193/********Name=PMU0SOFTRST_CON02,Offset=0x10208********/
194#define SRST_P_PMU0_I2C0		154
195#define SRST_PMU0_I2C0			155
196
197/********Name=PMU1SOFTRST_CON00,Offset=0x18200********/
198#define SRST_P_PMU1_CRU			156
199#define SRST_H_PMU1_MEM			157
200#define SRST_H_PMU1_BIU			158
201#define SRST_P_PMU1_BIU			159
202#define SRST_P_PMU1_UART0		160
203#define SRST_S_PMU1_UART0		161
204/********Name=PMU1SOFTRST_CON01,Offset=0x18204********/
205#define SRST_P_PMU1_SPI0		162
206#define SRST_PMU1_SPI0			163
207#define SRST_P_PMU1_PWM0		164
208#define SRST_PMU1_PWM0			165
209/********Name=PMU1SOFTRST_CON02,Offset=0x18208********/
210#define SRST_F_PMU1_CM0_CORE		166
211#define SRST_T_PMU1_CM0_JTAG		167
212#define SRST_P_PMU1_WDTNS		168
213#define SRST_PMU1_WDTNS			169
214#define SRST_PMU1_MAILBOX		170
215
216/********Name=DDRSOFTRST_CON00,Offset=0x20200********/
217#define SRST_MSCH_BRG_BIU		171
218#define SRST_P_MSCH_BIU			172
219#define SRST_P_DDR_HWLP			173
220#define SRST_P_DDR_PHY			290
221#define SRST_P_DDR_DFICTL		174
222#define SRST_P_DDR_DMA2DDR		175
223/********Name=DDRSOFTRST_CON01,Offset=0x20204********/
224#define SRST_P_DDR_MON			176
225#define SRST_TM_DDR_MON			177
226#define SRST_P_DDR_GRF			178
227#define SRST_P_DDR_CRU			179
228#define SRST_P_SUBDDR_CRU		180
229
230/********Name=SUBDDRSOFTRST_CON00,Offset=0x28200********/
231#define SRST_MSCH_BIU			181
232#define SRST_DDR_PHY			182
233#define SRST_DDR_DFICTL			183
234#define SRST_DDR_SCRAMBLE		184
235#define SRST_DDR_MON			185
236#define SRST_A_DDR_SPLIT		186
237#define SRST_DDR_DMA2DDR		187
238
239/********Name=PERISOFTRST_CON01,Offset=0x30404********/
240#define SRST_A_PERI_BIU			188
241#define SRST_H_PERI_BIU			189
242#define SRST_P_PERI_BIU			190
243#define SRST_P_PERICRU			191
244/********Name=PERISOFTRST_CON02,Offset=0x30408********/
245#define SRST_H_SAI0_8CH			192
246#define SRST_M_SAI0_8CH			193
247#define SRST_H_SAI1_8CH			194
248#define SRST_M_SAI1_8CH			195
249#define SRST_H_SAI2_2CH			196
250#define SRST_M_SAI2_2CH			197
251/********Name=PERISOFTRST_CON03,Offset=0x3040C********/
252#define SRST_H_DSM			198
253#define SRST_DSM			199
254#define SRST_H_PDM			200
255#define SRST_M_PDM			201
256#define SRST_H_SPDIF			202
257#define SRST_M_SPDIF			203
258/********Name=PERISOFTRST_CON04,Offset=0x30410********/
259#define SRST_H_SDMMC0			204
260#define SRST_H_SDMMC1			205
261#define SRST_H_EMMC			206
262#define SRST_A_EMMC			207
263#define SRST_C_EMMC			208
264#define SRST_B_EMMC			209
265#define SRST_T_EMMC			210
266#define SRST_S_SFC			211
267#define SRST_H_SFC			212
268/********Name=PERISOFTRST_CON05,Offset=0x30414********/
269#define SRST_H_USB2HOST			213
270#define SRST_H_USB2HOST_ARB		214
271#define SRST_USB2HOST_UTMI		215
272/********Name=PERISOFTRST_CON06,Offset=0x30418********/
273#define SRST_P_SPI1			216
274#define SRST_SPI1			217
275#define SRST_P_SPI2			218
276#define SRST_SPI2			219
277/********Name=PERISOFTRST_CON07,Offset=0x3041C********/
278#define SRST_P_UART1			220
279#define SRST_P_UART2			221
280#define SRST_P_UART3			222
281#define SRST_P_UART4			223
282#define SRST_P_UART5			224
283#define SRST_P_UART6			225
284#define SRST_P_UART7			226
285#define SRST_P_UART8			227
286#define SRST_P_UART9			228
287#define SRST_S_UART1			229
288#define SRST_S_UART2			230
289/********Name=PERISOFTRST_CON08,Offset=0x30420********/
290#define SRST_S_UART3			231
291#define SRST_S_UART4			232
292#define SRST_S_UART5			233
293#define SRST_S_UART6			234
294#define SRST_S_UART7			235
295/********Name=PERISOFTRST_CON09,Offset=0x30424********/
296#define SRST_S_UART8			236
297#define SRST_S_UART9			237
298/********Name=PERISOFTRST_CON10,Offset=0x30428********/
299#define SRST_P_PWM1_PERI		238
300#define SRST_PWM1_PERI			239
301#define SRST_P_PWM2_PERI		240
302#define SRST_PWM2_PERI			241
303#define SRST_P_PWM3_PERI		242
304#define SRST_PWM3_PERI			243
305/********Name=PERISOFTRST_CON11,Offset=0x3042C********/
306#define SRST_P_CAN0			244
307#define SRST_CAN0			245
308#define SRST_P_CAN1			246
309#define SRST_CAN1			247
310/********Name=PERISOFTRST_CON12,Offset=0x30430********/
311#define SRST_A_CRYPTO			248
312#define SRST_H_CRYPTO			249
313#define SRST_P_CRYPTO			250
314#define SRST_CORE_CRYPTO		251
315#define SRST_PKA_CRYPTO			252
316#define SRST_H_KLAD			253
317#define SRST_P_KEY_READER		254
318#define SRST_H_RK_RNG_NS		255
319#define SRST_H_RK_RNG_S			256
320#define SRST_H_TRNG_NS			257
321#define SRST_H_TRNG_S			258
322#define SRST_H_CRYPTO_S			259
323/********Name=PERISOFTRST_CON13,Offset=0x30434********/
324#define SRST_P_PERI_WDT			260
325#define SRST_T_PERI_WDT			261
326#define SRST_A_SYSMEM			262
327#define SRST_H_BOOTROM			263
328#define SRST_P_PERI_GRF			264
329#define SRST_A_DMAC			265
330#define SRST_A_RKDMAC			267
331/********Name=PERISOFTRST_CON14,Offset=0x30438********/
332#define SRST_P_OTPC_NS			268
333#define SRST_SBPI_OTPC_NS		269
334#define SRST_USER_OTPC_NS		270
335#define SRST_P_OTPC_S			271
336#define SRST_SBPI_OTPC_S		272
337#define SRST_USER_OTPC_S		273
338#define SRST_OTPC_ARB			274
339#define SRST_P_OTPPHY			275
340#define SRST_OTP_NPOR			276
341/********Name=PERISOFTRST_CON15,Offset=0x3043C********/
342#define SRST_P_USB2PHY			277
343#define SRST_USB2PHY_POR		278
344#define SRST_USB2PHY_OTG		279
345#define SRST_USB2PHY_HOST		280
346#define SRST_P_PIPEPHY			281
347/********Name=PERISOFTRST_CON16,Offset=0x30440********/
348#define SRST_P_SARADC			282
349#define SRST_SARADC			283
350#define SRST_SARADC_PHY			284
351#define SRST_P_IOC_VCCIO234		285
352/********Name=PERISOFTRST_CON17,Offset=0x30444********/
353#define SRST_P_PERI_GPIO1		286
354#define SRST_P_PERI_GPIO2		287
355#define SRST_PERI_GPIO1			288
356#define SRST_PERI_GPIO2			289
357
358#endif