qcom,ipq5424-nsscc.h

 1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
 2/*
 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
 4 */
 5
 6#ifndef _DT_BINDINGS_RESET_QCOM_IPQ5424_NSSCC_H
 7#define _DT_BINDINGS_RESET_QCOM_IPQ5424_NSSCC_H
 8
 9#define NSS_CC_CE_APB_CLK_ARES					0
10#define NSS_CC_CE_AXI_CLK_ARES					1
11#define NSS_CC_DEBUG_CLK_ARES					2
12#define NSS_CC_EIP_CLK_ARES					3
13#define NSS_CC_NSS_CSR_CLK_ARES					4
14#define NSS_CC_NSSNOC_CE_APB_CLK_ARES				5
15#define NSS_CC_NSSNOC_CE_AXI_CLK_ARES				6
16#define NSS_CC_NSSNOC_EIP_CLK_ARES				7
17#define NSS_CC_NSSNOC_NSS_CSR_CLK_ARES				8
18#define NSS_CC_NSSNOC_PPE_CLK_ARES				9
19#define NSS_CC_NSSNOC_PPE_CFG_CLK_ARES				10
20#define NSS_CC_PORT1_MAC_CLK_ARES				11
21#define NSS_CC_PORT1_RX_CLK_ARES				12
22#define NSS_CC_PORT1_TX_CLK_ARES				13
23#define NSS_CC_PORT2_MAC_CLK_ARES				14
24#define NSS_CC_PORT2_RX_CLK_ARES				15
25#define NSS_CC_PORT2_TX_CLK_ARES				16
26#define NSS_CC_PORT3_MAC_CLK_ARES				17
27#define NSS_CC_PORT3_RX_CLK_ARES				18
28#define NSS_CC_PORT3_TX_CLK_ARES				19
29#define NSS_CC_PPE_BCR						20
30#define NSS_CC_PPE_EDMA_CLK_ARES				21
31#define NSS_CC_PPE_EDMA_CFG_CLK_ARES				22
32#define NSS_CC_PPE_SWITCH_BTQ_CLK_ARES				23
33#define NSS_CC_PPE_SWITCH_CLK_ARES				24
34#define NSS_CC_PPE_SWITCH_CFG_CLK_ARES				25
35#define NSS_CC_PPE_SWITCH_IPE_CLK_ARES				26
36#define NSS_CC_UNIPHY_PORT1_RX_CLK_ARES				27
37#define NSS_CC_UNIPHY_PORT1_TX_CLK_ARES				28
38#define NSS_CC_UNIPHY_PORT2_RX_CLK_ARES				29
39#define NSS_CC_UNIPHY_PORT2_TX_CLK_ARES				30
40#define NSS_CC_UNIPHY_PORT3_RX_CLK_ARES				31
41#define NSS_CC_UNIPHY_PORT3_TX_CLK_ARES				32
42#define NSS_CC_XGMAC0_PTP_REF_CLK_ARES				33
43#define NSS_CC_XGMAC1_PTP_REF_CLK_ARES				34
44#define NSS_CC_XGMAC2_PTP_REF_CLK_ARES				35
45
46#endif